From 9de97c1e20d5b66a2a4562e58d463cebf4057c32 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Tue, 13 Jul 2021 14:17:36 -0400
Subject: [PATCH] Fixed busybear by restoring InstrValidW needed by testbench

---
 wally-pipelined/regression/wave-all.do | 12 ++++++------
 wally-pipelined/src/ieu/controller.sv  |  8 ++++----
 wally-pipelined/src/ieu/ieu.sv         |  3 ++-
 3 files changed, 12 insertions(+), 11 deletions(-)

diff --git a/wally-pipelined/regression/wave-all.do b/wally-pipelined/regression/wave-all.do
index 6adbf226..f587ec8f 100644
--- a/wally-pipelined/regression/wave-all.do
+++ b/wally-pipelined/regression/wave-all.do
@@ -152,7 +152,7 @@ add wave -noupdate -radix hexadecimal /testbench/dut/hart/PCTargetE
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/CSRReadValW
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/PrivilegedNextPCM
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/MemRWM
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/InstrValidW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/InstrValidM
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/InstrMisalignedFaultM
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/DataMisalignedM
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/IllegalBaseInstrFaultD
@@ -337,7 +337,7 @@ add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/Funct3M
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/ReadDataW
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/CSRReadValW
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/PCLinkW
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/InstrValidW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/InstrValidM
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/StallD
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/FlushD
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/FlushE
@@ -397,7 +397,7 @@ add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/RegWriteM
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/FlushW
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/RegWriteW
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/ResultSrcW
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/InstrValidW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/InstrValidM
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/CSRWritePendingDEM
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/RegWriteD
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/RegWriteE
@@ -740,7 +740,7 @@ add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/CSRReadValW
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/PrivilegedNextPCM
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/RetM
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/TrapM
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/InstrValidW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/InstrValidM
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/FRegWriteM
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/LoadStallD
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/PrivilegedM
@@ -842,7 +842,7 @@ add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/uretM
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/TimerIntM
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/ExtIntM
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/SwIntM
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/InstrValidW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/InstrValidM
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/FRegWriteM
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/LoadStallD
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/NextPrivilegeModeM
@@ -972,7 +972,7 @@ add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrsr
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrsr/STATUS_UIE
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/clk
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/reset
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/InstrValidW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/InstrValidM
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/LoadStallD
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/CSRMWriteM
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/counters/CSRAdrM
diff --git a/wally-pipelined/src/ieu/controller.sv b/wally-pipelined/src/ieu/controller.sv
index a48191f0..257dc6eb 100644
--- a/wally-pipelined/src/ieu/controller.sv
+++ b/wally-pipelined/src/ieu/controller.sv
@@ -55,7 +55,7 @@ module controller(
   output logic [1:0] AtomicM,
   output logic [2:0] Funct3M,
   output logic       RegWriteM,     // for Hazard Unit
-  output logic       InstrValidM,
+  output logic       InstrValidM, InstrValidW,
   // Writeback stage control signals
   input  logic       StallW, FlushW,
   output logic 	     RegWriteW,     // for datapath and Hazard Unit
@@ -213,9 +213,9 @@ module controller(
                          {RegWriteM, ResultSrcM, MemRWM, CSRReadM, CSRWriteM, PrivilegedM, Funct3M, AtomicM, InstrValidM});
   
   // Writeback stage pipeline control register
-  flopenrc #(4) controlregW(clk, reset, FlushW, ~StallW,
-                         {RegWriteM, ResultSrcM},
-                         {RegWriteW, ResultSrcW});  
+  flopenrc #(5) controlregW(clk, reset, FlushW, ~StallW,
+                         {RegWriteM, ResultSrcM, InstrValidM},
+                         {RegWriteW, ResultSrcW, InstrValidW});  
 
   assign CSRWritePendingDEM = CSRWriteD | CSRWriteE | CSRWriteM;   
 endmodule
diff --git a/wally-pipelined/src/ieu/ieu.sv b/wally-pipelined/src/ieu/ieu.sv
index 3a80c3e9..56e11d0f 100644
--- a/wally-pipelined/src/ieu/ieu.sv
+++ b/wally-pipelined/src/ieu/ieu.sv
@@ -60,7 +60,7 @@ module ieu (
   input logic [`XLEN-1:0]  CSRReadValW, ReadDataW, MulDivResultW,
   input logic 		   FWriteIntW,
   // input  logic [`XLEN-1:0] PCLinkW,
-  output logic 		   InstrValidM,
+  output logic 		   InstrValidM, 
   // hazards
   input logic 		   StallD, StallE, StallM, StallW,
   input logic 		   FlushD, FlushE, FlushM, FlushW,
@@ -79,6 +79,7 @@ module ieu (
   logic [2:0]  ResultSrcW;
   logic        TargetSrcE;
   logic        SCE;
+  logic        InstrValidW;
 
   // forwarding signals
   logic [4:0]       Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW;