From 9ddd065340e5e41112f12fb4dc79189085bfb4c7 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 8 Dec 2021 13:40:32 -0600 Subject: [PATCH] Updated coremark testbench with the extra ports from FPGA merge. Fixed coremark Makefile to create work directory. --- benchmarks/riscv-coremark/Makefile | 7 ++++--- wally-pipelined/regression/wally-coremark.do | 2 +- wally-pipelined/testbench/testbench-coremark_bare.sv | 11 ++++++++--- 3 files changed, 13 insertions(+), 7 deletions(-) diff --git a/benchmarks/riscv-coremark/Makefile b/benchmarks/riscv-coremark/Makefile index a5b47239..1247d3d7 100644 --- a/benchmarks/riscv-coremark/Makefile +++ b/benchmarks/riscv-coremark/Makefile @@ -14,10 +14,11 @@ work/coremark.bare.riscv.objdump: work/coremark.bare.riscv work/coremark.bare.riscv: $(sources) # make -C $(cmbase) PORT_DIR=/home/harris/riscv-wally/benchmarks/riscv-coremark/riscv64-baremetal compile RISCV=/courses/e190ax/riscvcompiler XCFLAGS="-march=rv64g" - make -C $(cmbase) PORT_DIR=$(PORT_DIR) compile RISCV=/courses/e190ax/riscvcompiler XCFLAGS="-march=rv64im" - mv $(cmbase)/coremark.bare.riscv work + make -C $(cmbase) PORT_DIR=$(PORT_DIR) compile RISCV=/opt/riscv XCFLAGS="-march=rv64imd" + mkdir -p work/ + mv $(cmbase)/coremark.bare.riscv work/ .PHONY: clean clean: - rm -f work/* \ No newline at end of file + rm -f work/* diff --git a/wally-pipelined/regression/wally-coremark.do b/wally-pipelined/regression/wally-coremark.do index 37b26f8b..b403016a 100644 --- a/wally-pipelined/regression/wally-coremark.do +++ b/wally-pipelined/regression/wally-coremark.do @@ -35,7 +35,7 @@ vlog +incdir+../config/coremark_bare +incdir+../config/shared ../testbench/testb vopt +acc work.testbench -o workopt vsim workopt -mem load -startaddress 268435456 -endaddress 268566527 -filltype value -fillradix hex -filldata 0 /testbench/dut/uncore/dtim/RAM +mem load -startaddress 268435456 -endaddress 268566527 -filltype value -fillradix hex -filldata 0 /testbench/dut/uncore/dtim/dtim/RAM view wave diff --git a/wally-pipelined/testbench/testbench-coremark_bare.sv b/wally-pipelined/testbench/testbench-coremark_bare.sv index ebf6e29a..06ca47b0 100644 --- a/wally-pipelined/testbench/testbench-coremark_bare.sv +++ b/wally-pipelined/testbench/testbench-coremark_bare.sv @@ -54,8 +54,13 @@ module testbench(); logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn; logic UARTSin, UARTSout; logic SDCCLK; - tri1 SDCCmd; - tri1 [3:0] SDCDat; + logic SDCCmdIn; + logic SDCCmdOut; + logic SDCCmdOE; + logic [3:0] SDCDatIn; + + logic HREADY; + logic HSELEXT; assign SDCmd = 1'bz; assign SDCDat = 4'bz; @@ -95,7 +100,7 @@ module testbench(); totalerrors = 0; // read test vectors into memory memfilename = tests[0]; - $readmemh(memfilename, dut.uncore.dtim.RAM); + $readmemh(memfilename, dut.uncore.dtim.dtim.RAM); //for(j=268437955; j < 268566528; j = j+1) //dut.uncore.dtim.RAM[j] = 64'b0; // ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.objdump.addr";