From 9dce2a06794b0ddb6a50910b641b7624ebcc0968 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 11 Mar 2022 14:58:21 -0600 Subject: [PATCH] Towards allowing dtim + bus. --- pipelined/src/cache/cache.sv | 3 +-- pipelined/src/cache/subcachelineread.sv | 5 +---- pipelined/src/ifu/ifu.sv | 2 +- pipelined/src/lsu/dtim.sv | 2 -- pipelined/src/lsu/lsu.sv | 3 ++- 5 files changed, 5 insertions(+), 10 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index 02f2c040..067bfb74 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -144,12 +144,11 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTER mux2 #(NUMWAYS) saverestoremux(HitWay, HitWaySaved, restore, HitWayFinal); end else assign HitWayFinal = HitWay; - // like to fix this. if(DCACHE) mux2 #(LOGWPL) WordAdrrMux(.d0(PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)]), .d1(WordCount), .s(LSUBusWriteCrit), - .y(WordOffsetAddr)); // *** can reduce width of mux. only need the offset. + .y(WordOffsetAddr)); else assign WordOffsetAddr = PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)]; subcachelineread #(LINELEN, WORDLEN, MUXINTERVAL, LOGWPL) subcachelineread( diff --git a/pipelined/src/cache/subcachelineread.sv b/pipelined/src/cache/subcachelineread.sv index 47fc993a..2a3395ea 100644 --- a/pipelined/src/cache/subcachelineread.sv +++ b/pipelined/src/cache/subcachelineread.sv @@ -39,11 +39,8 @@ module subcachelineread #(parameter LINELEN, WORDLEN, MUXINTERVAL, LOGWPL)( output logic [WORDLEN-1:0] ReadDataWord); localparam WORDSPERLINE = LINELEN/MUXINTERVAL; + // pad is for icache. Muxing extends over the cacheline boundary. localparam PADLEN = WORDLEN-MUXINTERVAL; - // Convert the Read data bus ReadDataSelectWay into sets of XLEN so we can - // easily build a variable input mux. - // *** move this to LSU and IFU, also remove mux from busdp into LSU. - // *** give this a module name to match block diagram logic [LINELEN+(WORDLEN-MUXINTERVAL)-1:0] ReadDataLinePad; logic [WORDLEN-1:0] ReadDataLineSets [(LINELEN/MUXINTERVAL)-1:0]; logic [WORDLEN-1:0] ReadDataWordRaw, ReadDataWordSaved; diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index f59af0ab..87015f39 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -177,7 +177,7 @@ module ifu ( dtim irom(.clk, .reset, .CPUBusy, .LSURWM(2'b10), .IEUAdrM(PCPF[31:0]), .IEUAdrE(PCNextFSpill), .TrapM(1'b0), .FinalWriteDataM(), .ByteMaskM('0), .ReadDataWordM(AllInstrRawF), .BusStall, .LSUBusWrite(), .LSUBusRead(IFUBusRead), - .BusCommittedM(), .ReadDataWordMuxM(), .DCacheStallM(ICacheStallF), + .BusCommittedM(), .DCacheStallM(ICacheStallF), .DCacheCommittedM(), .DCacheMiss(ICacheMiss), .DCacheAccess(ICacheAccess)); end else begin : bus diff --git a/pipelined/src/lsu/dtim.sv b/pipelined/src/lsu/dtim.sv index bbbe664d..38a12c75 100644 --- a/pipelined/src/lsu/dtim.sv +++ b/pipelined/src/lsu/dtim.sv @@ -43,7 +43,6 @@ module dtim( output logic LSUBusWrite, output logic LSUBusRead, output logic BusCommittedM, - output logic [`XLEN-1:0] ReadDataWordMuxM, output logic DCacheStallM, output logic DCacheCommittedM, output logic DCacheMiss, @@ -58,7 +57,6 @@ module dtim( // since we have a local memory the bus connections are all disabled. // There are no peripherals supported. assign {BusStall, LSUBusWrite, LSUBusRead, BusCommittedM} = '0; - assign ReadDataWordMuxM = ReadDataWordM; assign {DCacheStallM, DCacheCommittedM} = '0; assign {DCacheMiss, DCacheAccess} = '0; diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 70291381..9fa50115 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -194,9 +194,10 @@ module lsu ( // Merge SimpleRAM and SRAM1p1rw into one that is good for synthesis and RAM libraries and flops dtim dtim(.clk, .reset, .CPUBusy, .LSURWM, .IEUAdrM, .IEUAdrE, .TrapM, .FinalWriteDataM, .ReadDataWordM, .BusStall, .LSUBusWrite,.LSUBusRead, .BusCommittedM, - .ReadDataWordMuxM, .DCacheStallM, .DCacheCommittedM, .ByteMaskM, + .DCacheStallM, .DCacheCommittedM, .ByteMaskM, .DCacheMiss, .DCacheAccess); assign SelUncachedAdr = '0; // value does not matter. + assign ReadDataWordMuxM = ReadDataWordM; end else begin : bus localparam integer WORDSPERLINE = (CACHE_ENABLED) ? `DCACHE_LINELENINBITS/`XLEN : 1; localparam integer LINELEN = (CACHE_ENABLED) ? `DCACHE_LINELENINBITS : `XLEN;