From 9c8edb9cb6a1ef254c3edf48c242d884424b6097 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Tue, 20 Sep 2022 19:29:23 -0700
Subject: [PATCH] renamed u to udigit to avoid conflict with U

---
 pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv  | 10 +++++-----
 pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv  |  4 ++--
 pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv | 12 ++++++------
 pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv | 12 ++++++------
 4 files changed, 19 insertions(+), 19 deletions(-)

diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv
index 01b067c6..9b0427aa 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv
@@ -31,7 +31,7 @@
 `include "wally-config.vh"
 
 module fdivsqrtfgen4 (
-  input  logic [3:0] u,
+  input  logic [3:0] udigit,
   input  logic [`DIVb+3:0] C, U, UM,
   output logic [`DIVb+3:0] F
 );
@@ -47,9 +47,9 @@ module fdivsqrtfgen4 (
   // Choose which adder input will be used
 
   always_comb
-    if (u[3])       F = F2;
-    else if (u[2])  F = F1;
-    else if (u[1])  F = FN1;
-    else if (u[0])  F = FN2;
+    if (udigit[3])       F = F2;
+    else if (udigit[2])  F = F1;
+    else if (udigit[1])  F = FN1;
+    else if (udigit[0])  F = FN2;
     else            F = F0;
 endmodule
\ No newline at end of file
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv
index f0a6cae0..4379724f 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv
@@ -35,7 +35,7 @@ module fdivsqrtqsel4 (
   input logic [4:0] Smsbs,
   input logic [`DIVb+3:0] WS, WC,
   input logic Sqrt, j1,
-  output logic [3:0] u
+  output logic [3:0] udigit
 );
 	logic [6:0] Wmsbs;
 	logic [7:0] PreWmsbs;
@@ -107,6 +107,6 @@ module fdivsqrtqsel4 (
       else if (Smsbs == 5'b10000) A = 3'b111;
       else A = Smsbs[2:0];
     end else A = Dmsbs;
-	assign u = USel4[{A,Wmsbs}];
+	assign udigit = USel4[{A,Wmsbs}];
 	
 endmodule
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv
index 9fa655c3..e463762a 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv
@@ -46,7 +46,7 @@ module fdivsqrtstage4 (
  /* verilator lint_on UNOPTFLAT */
 
   logic [`DIVb+3:0]  Dsel;
-  logic [3:0]     u;
+  logic [3:0]     udigit;
   logic [`DIVb+3:0] F;
   logic [`DIVb+3:0] AddIn;
   logic [4:0] Smsbs;
@@ -61,11 +61,11 @@ module fdivsqrtstage4 (
 	// 0010 = -1
 	// 0001 = -2
   assign Smsbs = U[`DIVb:`DIVb-4];
-  fdivsqrtqsel4 qsel4(.D, .Smsbs, .WS, .WC, .Sqrt(SqrtM), .j1, .u);
-  fdivsqrtfgen4 fgen4(.u, .C({2'b11, CNext}), .U({3'b000, U}), .UM({3'b000, UM}), .F);
+  fdivsqrtqsel4 qsel4(.D, .Smsbs, .WS, .WC, .Sqrt(SqrtM), .j1, .udigit);
+  fdivsqrtfgen4 fgen4(.udigit, .C({2'b11, CNext}), .U({3'b000, U}), .UM({3'b000, UM}), .F);
 
   always_comb
-  case (u)
+  case (udigit)
     4'b1000: Dsel = DBar2;
     4'b0100: Dsel = DBar;
     4'b0000: Dsel = '0;
@@ -77,10 +77,10 @@ module fdivsqrtstage4 (
   // Partial Product Generation
   //  WSA, WCA = WS + WC - qD
   assign AddIn = SqrtM ? F : Dsel;
-  assign CarryIn = ~SqrtM & (u[3] | u[2]); // +1 for 2's complement of -D and -2D 
+  assign CarryIn = ~SqrtM & (udigit[3] | udigit[2]); // +1 for 2's complement of -D and -2D 
   csa #(`DIVb+4) csa(WS, WC, AddIn, CarryIn, WSA, WCA);
  
-  fdivsqrtuotfc4 fdivsqrtuotfc4(.u, .Sqrt(SqrtM), .C(CNext[`DIVb:0]), .U, .UM, .UNext, .UMNext);
+  fdivsqrtuotfc4 fdivsqrtuotfc4(.udigit, .Sqrt(SqrtM), .C(CNext[`DIVb:0]), .U, .UM, .UNext, .UMNext);
 
   assign un = 0; // unused for radix 4
 endmodule
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv
index c3c64bbb..d0524ac8 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv
@@ -31,7 +31,7 @@
 `include "wally-config.vh"
 
 module fdivsqrtuotfc4(
-  input  logic [3:0]   u,
+  input  logic [3:0]   udigit,
   input  logic         Sqrt,
   input  logic [`DIVb:0] U, UM,
   input  logic [`DIVb:0] C,
@@ -47,19 +47,19 @@ module fdivsqrtuotfc4(
   assign K3 = (C & ~(C << 2));      // 3K
 
   always_comb begin
-    if (u[3]) begin
+    if (udigit[3]) begin
       UNext  = U | K2;
       UMNext = U | K1;
-    end else if (u[2]) begin
+    end else if (udigit[2]) begin
       UNext  = U | K1;
       UMNext = U;
-    end else if (u[1]) begin
+    end else if (udigit[1]) begin
       UNext  = UM | K3;
       UMNext = UM | K2;
-    end else if (u[0]) begin
+    end else if (udigit[0]) begin
       UNext  = UM | K2;
       UMNext = UM | K1;
-    end else begin        // digit = 0
+    end else begin        // udigit = 0
       UNext  = U;
       UMNext = UM | K3;
     end