From 9c70ab917c36ab007f67c07c6de01fe3c2ec4d5c Mon Sep 17 00:00:00 2001
From: cturek <cturek@hmc.edu>
Date: Sun, 13 Nov 2022 22:40:26 +0000
Subject: [PATCH] Added A<B signal to fdivsqrt, started postprocessing merge

---
 pipelined/config/shared/wally-shared.vh        |  4 ++--
 pipelined/src/fpu/fdivsqrt/fdivsqrt.sv         |  9 +++++----
 pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv | 11 +++++++----
 pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv  |  8 ++++----
 4 files changed, 18 insertions(+), 14 deletions(-)

diff --git a/pipelined/config/shared/wally-shared.vh b/pipelined/config/shared/wally-shared.vh
index 506cc7c5..ee09a426 100644
--- a/pipelined/config/shared/wally-shared.vh
+++ b/pipelined/config/shared/wally-shared.vh
@@ -123,11 +123,11 @@
 `define LOGRK ($clog2(`RK))
 // FPDUR = ceil(DIVRESLEN/(LOGR*DIVCOPIES)) 
 // one iteration is required for the integer bit for minimally redundent radix-4
-`define FPDUR ((`DIVN+2+(`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES)+(`RADIX/4))
+`define FPDUR ((`DIVN+1+(`LOGR*`DIVCOPIES))/(`LOGR*`DIVCOPIES)+(`RADIX/4))
 `define DURLEN ($clog2(`FPDUR+1))
 `define QLEN (`FPDUR*`LOGR*`DIVCOPIES)
 `define DIVb (`QLEN-1)
-`define DIVa (`DIVb+4-`XLEN)
+`define DIVa (`DIVb+1-`XLEN)
 `define DIVBLEN ($clog2(`DIVb+1)-1)
 
 
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
index 65ea6cc5..f5cf2e3f 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
@@ -64,12 +64,13 @@ module fdivsqrt(
   logic Firstun;
   logic WZero;
   logic SpecialCaseM;
-  logic [`DIVBLEN:0] n, p, m;
-  logic OTFCSwap;
+  logic [`DIVBLEN:0] n, p, m, L;
+  logic OTFCSwap, ALTB;
 
   fdivsqrtpreproc fdivsqrtpreproc(
     .clk, .DivStartE, .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE), 
-    .Sqrt(SqrtE), .Ym(YmE), .XZero(XZeroE), .X, .Dpreproc, .n, .p, .m, .OTFCSwap,
+    .Sqrt(SqrtE), .Ym(YmE), .XZero(XZeroE), .X, .Dpreproc, 
+    .n, .p, .m, .L, .OTFCSwap, .ALTB,
     .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E);
   fdivsqrtfsm fdivsqrtfsm(
     .clk, .reset, .FmtE, .XsE, .SqrtE, 
@@ -84,6 +85,6 @@ module fdivsqrt(
   fdivsqrtpostproc fdivsqrtpostproc(
     .WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun, 
     .SqrtM, .SpecialCaseM, .RemOp(Funct3E[1]),
-    .n, .p, .m,
+    .MDUE, .n, .ALTB, .m,
     .QmM, .WZero, .DivSM);
 endmodule
\ No newline at end of file
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
index 9e9bdb10..44c7f901 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
@@ -35,11 +35,11 @@ module fdivsqrtpostproc(
   input  logic [`DIVN-2:0]  D, // U0.N-1
   input  logic [`DIVb:0] FirstU, FirstUM, 
   input  logic [`DIVb+1:0] FirstC,
-  input  logic  Firstun,
+  input  logic Firstun,
   input  logic SqrtM,
   input  logic SpecialCaseM,
-  input  logic RemOp,
-  input  logic [`DIVBLEN:0] n, p, m,
+  input  logic RemOp, MDUE, ALTB,
+  input  logic [`DIVBLEN:0] n, m,
   output logic [`DIVb:0] QmM, 
   output logic WZero,
   output logic DivSM
@@ -49,6 +49,7 @@ module fdivsqrtpostproc(
   logic [`DIVb:0] PreQmM;
   logic NegSticky;
   logic weq0;
+  logic [`DIVb:0] IntQuot, IntRem;
 
   // check for early termination on an exact result.  If the result is not exact, the sticky should be set
   aplusbeq0 #(`DIVb+4) wspluswceq0(WS, WC, weq0);
@@ -69,8 +70,10 @@ module fdivsqrtpostproc(
   end 
   assign DivSM = ~WZero & ~(SpecialCaseM & SqrtM); // ***unsure why SpecialCaseM has to be gated by SqrtM, but otherwise fails regression on divide
 
+
+
   // Determine if sticky bit is negative
-  assign W = WC+WS;
+  assign W = WC + WS;
   assign NegSticky = W[`DIVb+3];
 
    // division takes the result from the next cycle, which is shifted to the left one more time so the square root also needs to be shifted
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
index b3d81705..0ee67019 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
@@ -41,8 +41,8 @@ module fdivsqrtpreproc (
   input  logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
 	input  logic [2:0] 	Funct3E, Funct3M,
 	input  logic MDUE, W64E,
-  output logic [`DIVBLEN:0] n, p, m,
-  output logic OTFCSwap,
+  output logic [`DIVBLEN:0] n, p, m, L,
+  output logic OTFCSwap, ALTB,
   output logic [`NE+1:0] QeM,
   output logic [`DIVb+3:0] X,
   output logic [`DIVN-2:0] Dpreproc
@@ -52,7 +52,6 @@ module fdivsqrtpreproc (
   logic  [`NF-1:0] PreprocB, PreprocY;
   logic  [`NF+1:0] SqrtX;
   logic  [`DIVb+3:0] DivX;
-  logic  [`DIVBLEN:0] L;
   logic  [`NE+1:0] Qe;
   // Intdiv signals
   logic  [`DIVb-1:0] ZeroBufX, ZeroBufY;
@@ -86,7 +85,8 @@ module fdivsqrtpreproc (
   assign PreprocY = Ym[`NF-1:0]<<m;
 
   assign ZeroDiff = m - L;
-  assign p = ZeroDiff[`DIVBLEN] ? '0 : ZeroDiff;
+  assign ALTB = ZeroDiff[`DIVBLEN]; // A less than B
+  assign p = ALTB ? '0 : ZeroDiff;
 
   assign pPlusr = (`DIVBLEN)'(`LOGR) + p;
   assign pPrTrunc = pPlusr[`LOGRK-1:0];