From 9b756d6a94a250f2034fc0be0a8133909ee0b52e Mon Sep 17 00:00:00 2001
From: Ross Thompson <stephen.thompson.37@us.af.mil>
Date: Tue, 13 Jul 2021 23:03:09 -0500
Subject: [PATCH] Implemented uncached reads.

---
 wally-pipelined/regression/wave.do  |  4 +--
 wally-pipelined/src/cache/dcache.sv | 42 +++++++++++++++++++++++++----
 2 files changed, 39 insertions(+), 7 deletions(-)

diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do
index f53880fd..f0bba807 100644
--- a/wally-pipelined/regression/wave.do
+++ b/wally-pipelined/regression/wave.do
@@ -401,7 +401,7 @@ add wave -noupdate /testbench/dut/uncore/dtim/risingHREADYTim
 add wave -noupdate /testbench/dut/uncore/dtim/memwrite
 add wave -noupdate /testbench/dut/uncore/dtim/HWDATA
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 12} {4707 ns} 0} {{Cursor 4} {1979605 ns} 0} {{Cursor 5} {6253401 ns} 0}
+WaveRestoreCursors {{Cursor 12} {5675 ns} 0} {{Cursor 4} {1979605 ns} 0} {{Cursor 5} {6253401 ns} 0}
 quietly wave cursor active 1
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 297
@@ -417,4 +417,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {4642 ns} {4816 ns}
+WaveRestoreZoom {5566 ns} {5750 ns}
diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv
index 9f2c0652..ba73f73a 100644
--- a/wally-pipelined/src/cache/dcache.sv
+++ b/wally-pipelined/src/cache/dcache.sv
@@ -90,7 +90,7 @@ module dcache
   logic [BLOCKLEN-1:0]	       ReadDataBlockM;
   logic [`XLEN-1:0]	       ReadDataBlockSetsM [(WORDSPERLINE)-1:0];
   logic [`XLEN-1:0]	       VictimReadDataBlockSetsM [(WORDSPERLINE)-1:0];  
-  logic [`XLEN-1:0]	       ReadDataWordM, FinalReadDataWordM;
+  logic [`XLEN-1:0]	       ReadDataWordM, FinalReadDataWordM, ReadDataWordMuxM;
   logic [`XLEN-1:0]	       FinalWriteDataM, FinalAMOWriteDataM;
   logic [BLOCKLEN-1:0]	       FinalWriteDataWordsM;
   logic [LOGWPL:0] 	       FetchCount, NextFetchCount;
@@ -111,6 +111,7 @@ module dcache
   logic [BLOCKLEN-1:0] 	       VictimReadDataBlockM;
   logic 		       VictimDirty;
   logic 		       SelAMOWrite;
+  logic 		       SelUncached;
   logic [6:0] 		       Funct7W;
   logic [2**LOGWPL-1:0]	       MemPAdrDecodedW;
 
@@ -229,12 +230,18 @@ module dcache
 
   assign HWDATA = CacheableM ? VictimReadDataBlockSetsM[FetchCount] : WriteDataM;
 
+  mux2 #(`XLEN) UnCachedDataMux(.d0(ReadDataWordM),
+				.d1(DCacheMemWriteData[`XLEN-1:0]),
+				.s(SelUncached),
+				.y(ReadDataWordMuxM));
+  
   // finally swr
   // *** BUG fix HSIZED? why was it this way?
-  subwordread subwordread(.HRDATA(ReadDataWordM),
+  subwordread subwordread(.HRDATA(ReadDataWordMuxM),
 			  .HADDRD(MemPAdrM[2:0]),
 			  .HSIZED({Funct3M[2], 1'b0, Funct3M[1:0]}),
 			  .HRDATAMasked(FinalReadDataWordM));
+  
 
   flopen #(`XLEN) ReadDataWReg(.clk(clk),
 			      .en(~StallW),
@@ -337,10 +344,10 @@ module dcache
 		STATE_PTW_MISS_WRITE_BACK_EVICTED_BLOCK,
 		STATE_PTW_MISS_WRITE_CACHE_BLOCK,
 		STATE_PTW_MISS_READ_SRAM,
-		STATE_UNCACHED_WDV,
-		STATE_UNCACHED_DONE,
 		STATE_UNCACHED_WRITE,
 		STATE_UNCACHED_WRITE_DONE,
+		STATE_UNCACHED_READ,
+		STATE_UNCACHED_READ_DONE,
 		STATE_CPU_BUSY} statetype;
 
   statetype CurrState, NextState;
@@ -393,6 +400,7 @@ module dcache
     AHBWrite = 1'b0;
     SelAMOWrite = 1'b0;
     CommittedM = 1'b0;        
+    SelUncached = 1'b0;
 
     case (CurrState)
       STATE_READY: begin
@@ -438,7 +446,13 @@ module dcache
 	  CntReset = 1'b1;
 	  DCacheStall = 1'b1;
 	  AHBWrite = 1'b1;
-	  
+	end
+	// uncached read
+	else if(MemRWM[1] & ~CacheableM & ~FaultM & ~DTLBMissM) begin
+	  NextState = STATE_UNCACHED_READ;
+	  CntReset = 1'b1;
+	  DCacheStall = 1'b1;
+	  AHBRead = 1'b1;	  
 	end
 	// fault
 	else if(AnyCPUReqM & FaultM & ~DTLBMissM) begin
@@ -560,10 +574,28 @@ module dcache
 	end
       end
 
+      STATE_UNCACHED_READ : begin
+	DCacheStall = 1'b1;	
+	AHBRead = 1'b1;
+	CommittedM = 1'b1;
+	if(AHBAck) begin
+	  NextState = STATE_UNCACHED_READ_DONE;
+	end else begin
+	  NextState = STATE_UNCACHED_READ;
+	end
+      end
+      
       STATE_UNCACHED_WRITE_DONE: begin
 	CommittedM = 1'b1;
 	NextState = STATE_READY;
       end
+
+      STATE_UNCACHED_READ_DONE: begin
+	CommittedM = 1'b1;
+	SelUncached = 1'b1;
+	NextState = STATE_READY;
+      end
+
       default: begin
       end
     endcase