From 9a7c7e8398840e7358a035eb437c37294fe44bf6 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 29 Aug 2022 09:48:00 -0500 Subject: [PATCH] Added comments about planned changes. --- pipelined/src/hazard/hazard.sv | 1 + pipelined/src/lsu/lsu.sv | 9 +++++++++ 2 files changed, 10 insertions(+) diff --git a/pipelined/src/hazard/hazard.sv b/pipelined/src/hazard/hazard.sv index ac3fc9d9..b9a6d957 100644 --- a/pipelined/src/hazard/hazard.sv +++ b/pipelined/src/hazard/hazard.sv @@ -61,6 +61,7 @@ module hazard( // *** can stalls be pushed into earlier stages (e.g. no stall after Decode?) + // *** consider replacing CSRWriteFencePendingDEM with a flush rather than a stall. assign StallFCause = CSRWriteFencePendingDEM & ~(TrapM | RetM | BPPredWrongE); // stall in decode if instruction is a load/mul/csr dependent on previous assign StallDCause = (LoadStallD | StoreStallD | MDUStallD | CSRRdStallD | FPUStallD | FStallD) & ~(TrapM | RetM | BPPredWrongE); diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 60768cec..6744fbcd 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -184,6 +184,15 @@ module lsu ( .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW); end else begin + // Determine which region of physical memory (if any) is being accessed + adrdecs adrdecs(.PhysicalAddress(LSUPAdrM), AccessRW, AccessRX, AccessRWX, Size, .SelRegions(LSUHSel)); + + // conditionally move adredecs to here and ifu. + // the lsu will output LSUHSel to EBU (need the same for ifu). + // The ebu will have a mux to select between LSUHSel, IFUHSel + // mux for HWSTRB + // adrdecs out of uncore. + assign {DTLBMissM, LoadAccessFaultM, StoreAmoAccessFaultM, LoadMisalignedFaultM, StoreAmoMisalignedFaultM} = '0; assign {LoadPageFaultM, StoreAmoPageFaultM} = '0; assign LSUPAdrM = PreLSUPAdrM;