From 9806babe9e541e924dd999262788f1096d4d30b4 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 5 Dec 2022 17:51:13 -0600
Subject: [PATCH] Renamed SelBusBuffer to SelFetchBuffer.

---
 pipelined/src/cache/cache.sv    | 6 +++---
 pipelined/src/cache/cachefsm.sv | 4 ++--
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv
index 5a2be23e..4c2942eb 100644
--- a/pipelined/src/cache/cache.sv
+++ b/pipelined/src/cache/cache.sv
@@ -100,7 +100,7 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
   logic                       ResetOrFlushAdr, ResetOrFlushWay;
   logic [LINELEN-1:0]         ReadDataLine, ReadDataLineCache;
   logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1:0]          WordOffsetAddr;
-  logic                       SelBusBuffer;
+  logic                       SelFetchBuffer;
   logic                       ce;
 
   localparam                  LOGLLENBYTES = $clog2(WORDLEN/8);
@@ -147,7 +147,7 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
       .y(WordOffsetAddr)); 
   else assign WordOffsetAddr = PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)];
   
-  mux2 #(LINELEN) EarlyReturnMux(ReadDataLineCache, FetchBuffer, SelBusBuffer, ReadDataLine);
+  mux2 #(LINELEN) EarlyReturnMux(ReadDataLineCache, FetchBuffer, SelFetchBuffer, ReadDataLine);
 
   subcachelineread #(LINELEN, WORDLEN, MUXINTERVAL) subcachelineread(
     .PAdr(WordOffsetAddr),
@@ -200,7 +200,7 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
 		.ClearValid, .ClearDirty, .SetDirty,
 		.SetValid, .SelEvict, .SelFlush,
 		.FlushAdrCntEn, .FlushWayCntEn, .FlushAdrCntRst,
-		.FlushWayCntRst, .FlushAdrFlag, .FlushWayFlag, .FlushCache, .SelBusBuffer,
+		.FlushWayCntRst, .FlushAdrFlag, .FlushWayFlag, .FlushCache, .SelFetchBuffer,
         .InvalidateCache,
         .ce,
         .LRUWriteEn);
diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv
index f35d9560..12fd3ade 100644
--- a/pipelined/src/cache/cachefsm.sv
+++ b/pipelined/src/cache/cachefsm.sv
@@ -71,7 +71,7 @@ module cachefsm
    output logic       FlushWayCntEn, 
    output logic       FlushAdrCntRst,
    output logic       FlushWayCntRst,
-   output logic       SelBusBuffer, 
+   output logic       SelFetchBuffer, 
    output logic       ce);
   
   logic               resetDelay;
@@ -200,7 +200,7 @@ module cachefsm
                   (CurrState == STATE_MISS_WRITE_CACHE_LINE) |
                   resetDelay;
 
-  assign SelBusBuffer = CurrState == STATE_MISS_WRITE_CACHE_LINE | CurrState == STATE_MISS_READ_DELAY;
+  assign SelFetchBuffer = CurrState == STATE_MISS_WRITE_CACHE_LINE | CurrState == STATE_MISS_READ_DELAY;
   assign ce = (CurrState == STATE_READY & ~CPUBusy | CacheStall) | (CurrState != STATE_READY) | reset;
                        
 endmodule // cachefsm