From 96cbd8e785cc6a29ecc8a089a6ee28976560cb6e Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 27 Aug 2021 11:03:36 -0500 Subject: [PATCH] Modified icache to no longer need StallF in the PCMux logic. Instead this is handled in the icachefsm. One downside is it increases the icache complexity. However it also fixes an untested bug. If a region was uncacheable it would have been possible for the request to be made multiple times. Now that is not possible. Additionally spills were oscillating between the spill hit states without this change. The impact was 'benign' as the final spilled instruction always had the correct upper 16 bits. --- wally-pipelined/regression/wave.do | 127 +++++++++++------- .../cache/dcache_ptw_interaction_README.txt | 2 +- wally-pipelined/src/cache/icache.sv | 3 +- wally-pipelined/src/cache/icachefsm.sv | 90 +++++++++++-- 4 files changed, 159 insertions(+), 63 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index 92519896..82fb8d3c 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -16,41 +16,41 @@ add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM add wave -noupdate /testbench/dut/hart/ieu/dp/ResultM add wave -noupdate /testbench/dut/hart/ieu/dp/ResultW -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM -add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM -add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM -add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM -add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE -add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM -add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/RetM -add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/TrapM -add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD -add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/StoreStallD -add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/ICacheStallF -add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/LSUStall -add wave -noupdate -group HDU -group hazards /testbench/dut/hart/MulDivStallD -add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF -add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD -add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE -add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM -add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM +add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM +add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM +add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/RetM +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/TrapM +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/StoreStallD +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/ICacheStallF +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LSUStall +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/MulDivStallD +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]} @@ -98,11 +98,12 @@ add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/if add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredClassNonCFIWrongE add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE -add wave -noupdate -group {instruction pipeline} /testbench/InstrFName -add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD -add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE -add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM -add wave -noupdate -group {instruction pipeline} /testbench/InstrW +add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrFName +add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/icache/FinalInstrRawF +add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD +add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE +add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM +add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrW add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCF add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F @@ -160,12 +161,12 @@ add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/Write add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE -add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCNextF -add wave -noupdate -group PCS /testbench/dut/hart/PCF -add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCD -add wave -noupdate -group PCS /testbench/dut/hart/PCE -add wave -noupdate -group PCS /testbench/dut/hart/PCM -add wave -noupdate -group PCS /testbench/PCW +add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCNextF +add wave -noupdate -expand -group PCS /testbench/dut/hart/PCF +add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCD +add wave -noupdate -expand -group PCS /testbench/dut/hart/PCE +add wave -noupdate -expand -group PCS /testbench/dut/hart/PCM +add wave -noupdate -expand -group PCS /testbench/PCW add wave -noupdate -group muldiv /testbench/dut/hart/mdu/InstrD add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcAE add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcBE @@ -185,7 +186,7 @@ add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/N add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/D add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/Q add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/rem0 -add wave -noupdate -expand -group icache -color Orange /testbench/dut/hart/ifu/icache/controller/CurrState +add wave -noupdate -expand -group icache -color Gold /testbench/dut/hart/ifu/icache/controller/CurrState add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/controller/NextState add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/ITLBMissF add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ITLBWriteF @@ -193,6 +194,8 @@ add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ReadLine add wave -noupdate -expand -group icache {/testbench/dut/hart/ifu/icache/icachemem/word[0]/CacheDataMem/Addr} add wave -noupdate -expand -group icache {/testbench/dut/hart/ifu/icache/icachemem/word[0]/CacheDataMem/WriteData} add wave -noupdate -expand -group icache {/testbench/dut/hart/ifu/icache/icachemem/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/PCNextIndexF +add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ReadLineF add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF @@ -456,16 +459,38 @@ add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HSELUART add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HADDR add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWRITE add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWDATA -add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/offset0 +add wave -noupdate -color Gold /testbench/dut/hart/lsu/dcache/subwordread/offset0 add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/offset1 add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/offset2 add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/offset3 add wave -noupdate /testbench/dut/hart/ExceptionM add wave -noupdate /testbench/dut/hart/PendingInterruptM add wave -noupdate /testbench/dut/hart/TrapM +add wave -noupdate /testbench/dut/hart/ifu/icache/CompressedF +add wave -noupdate /testbench/dut/hart/ifu/icache/PCPF +add wave -noupdate /testbench/dut/hart/ifu/PCPFmmu +add wave -noupdate /testbench/dut/hart/ifu/PCPF +add wave -noupdate /testbench/dut/hart/ifu/PCF +add wave -noupdate /testbench/dut/hart/ifu/immu/Translate +add wave -noupdate /testbench/dut/hart/ifu/icache/FinalInstrRawF +add wave -noupdate /testbench/dut/hart/ifu/icache/StallF +add wave -noupdate /testbench/dut/hart/ifu/icache/ICacheMemReadData +add wave -noupdate {/testbench/dut/hart/ifu/icache/icachemem/word[0]/CacheDataMem/Addr} +add wave -noupdate {/testbench/dut/hart/ifu/icache/icachemem/word[0]/CacheDataMem/ReadData} +add wave -noupdate {/testbench/dut/hart/ifu/icache/icachemem/word[1]/CacheDataMem/Addr} +add wave -noupdate {/testbench/dut/hart/ifu/icache/icachemem/word[1]/CacheDataMem/ReadData} +add wave -noupdate {/testbench/dut/hart/ifu/icache/icachemem/word[2]/CacheDataMem/Addr} +add wave -noupdate {/testbench/dut/hart/ifu/icache/icachemem/word[2]/CacheDataMem/ReadData} +add wave -noupdate {/testbench/dut/hart/ifu/icache/icachemem/word[3]/CacheDataMem/Addr} +add wave -noupdate {/testbench/dut/hart/ifu/icache/icachemem/word[3]/CacheDataMem/ReadData} +add wave -noupdate /testbench/dut/hart/ifu/icache/icachemem/WayHit +add wave -noupdate /testbench/dut/hart/ifu/icache/PCTagF +add wave -noupdate /testbench/dut/hart/ifu/icache/PCPSpillF +add wave -noupdate /testbench/dut/hart/ifu/icache/ICacheReadEn +add wave -noupdate /testbench/dut/hart/ifu/icache/PCMux_q TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 6} {32245 ns} 0} {{Cursor 2} {176 ns} 0} {{Cursor 3} {25666 ns} 0} {{Cursor 4} {2221 ns} 0} -quietly wave cursor active 2 +WaveRestoreCursors {{Cursor 6} {53451 ns} 0} +quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 297 configure wave -justifyvalue left @@ -480,4 +505,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {0 ns} {1124571 ns} +WaveRestoreZoom {53011 ns} {53891 ns} diff --git a/wally-pipelined/src/cache/dcache_ptw_interaction_README.txt b/wally-pipelined/src/cache/dcache_ptw_interaction_README.txt index b52987ed..59d768fc 100644 --- a/wally-pipelined/src/cache/dcache_ptw_interaction_README.txt +++ b/wally-pipelined/src/cache/dcache_ptw_interaction_README.txt @@ -9,7 +9,7 @@ should continue. It is important to note ITLB misses and faults DO NOT flush a memory operation in the memory stage. This is the core reason for the complexity. -| Type | ITLB miss | DTLB miss | mem op | | +| Type | ITLB miss | DTLB miss | mem op | | |-------+-----------+-----------+--------+--------------| | 0 | 0 | 0 | 0 | | | 1 | 0 | 0 | 1 | | diff --git a/wally-pipelined/src/cache/icache.sv b/wally-pipelined/src/cache/icache.sv index 7fc1e19b..7bbeccc6 100644 --- a/wally-pipelined/src/cache/icache.sv +++ b/wally-pipelined/src/cache/icache.sv @@ -109,7 +109,7 @@ module icache assign PCPSpillF = PCPF + {{{PA_WIDTH}{1'b0}}, 2'b10}; // *** modelsim does not allow the use of PA_BITS for literal width. // now we have to select between these three PCs - assign PCPreFinalF = PCMux[0] | StallF ? PCPF : PCNextF; // *** don't like the stallf, but it is necessary + assign PCPreFinalF = PCMux[0] ? PCPF : PCNextF; // *** don't like the stallf, but it is necessary // for the data cache i used a cpu busy state which is triggered by StallW. In the case of the icache I // modified the select on this address mux. Both are not ideal; however the cpu_busy state is required for the // dcache as a write would repeatedly update the sram or worse for an uncached write multiple times. @@ -243,6 +243,7 @@ module icache icachefsm #(.BLOCKLEN(BLOCKLEN)) controller(.clk, .reset, + .StallF, .ICacheReadEn, .ICacheMemWriteEnable, .ICacheStallF, diff --git a/wally-pipelined/src/cache/icachefsm.sv b/wally-pipelined/src/cache/icachefsm.sv index c0c2e003..ddf9b50c 100644 --- a/wally-pipelined/src/cache/icachefsm.sv +++ b/wally-pipelined/src/cache/icachefsm.sv @@ -30,6 +30,8 @@ module icachefsm #(parameter BLOCKLEN = 256) // Inputs from pipeline input logic clk, reset, + input logic StallF, + // inputs from mmu input logic ITLBMissF, input logic ITLBWriteF, @@ -88,7 +90,8 @@ module icachefsm #(parameter BLOCKLEN = 256) STATE_MISS_FETCH_WDV, // aligned miss, issue read to AHB and wait for data. STATE_MISS_FETCH_DONE, // write data into SRAM/LUT - STATE_MISS_READ, // read block 1 from SRAM/LUT + STATE_MISS_READ, // read block 1 from SRAM/LUT + STATE_MISS_READ_DELAY, // read block 1 from SRAM/LUT STATE_MISS_SPILL_FETCH_WDV, // spill, miss on block 0, issue read to AHB and wait STATE_MISS_SPILL_FETCH_DONE, // write data into SRAM/LUT @@ -104,7 +107,10 @@ module icachefsm #(parameter BLOCKLEN = 256) STATE_INVALIDATE, // *** not sure if invalidate or evict? invalidate by cache block or address? STATE_TLB_MISS, - STATE_TLB_MISS_DONE + STATE_TLB_MISS_DONE, + + STATE_CPU_BUSY, + STATE_CPU_BUSY_SPILL } statetype; statetype CurrState, NextState; @@ -138,7 +144,12 @@ module icachefsm #(parameter BLOCKLEN = 256) end else if (hit & ~spill) begin SavePC = 1'b1; ICacheStallF = 1'b0; - NextState = STATE_READY; + if(StallF) begin + NextState = STATE_CPU_BUSY; + PCMux = 2'b01; + end else begin + NextState = STATE_READY; + end end else if (hit & spill) begin spillSave = 1'b1; PCMux = 2'b10; @@ -151,7 +162,12 @@ module icachefsm #(parameter BLOCKLEN = 256) PCMux = 2'b01; NextState = STATE_MISS_SPILL_FETCH_WDV; end else begin - NextState = STATE_READY; + if(StallF) begin + NextState = STATE_CPU_BUSY; + PCMux = 2'b01; + end else begin + NextState = STATE_READY; + end end end // branch 1, hit spill and 2, miss spill hit @@ -192,8 +208,14 @@ module icachefsm #(parameter BLOCKLEN = 256) PCMux = 2'b00; UnalignedSelect = 1'b1; SavePC = 1'b1; - NextState = STATE_READY; - ICacheStallF = 1'b0; + ICacheStallF = 1'b0; + if(StallF) begin + NextState = STATE_CPU_BUSY_SPILL; + PCMux = 2'b10; + end else begin + NextState = STATE_READY; + end + end // branch 3 miss no spill STATE_MISS_FETCH_WDV: begin @@ -214,7 +236,19 @@ module icachefsm #(parameter BLOCKLEN = 256) STATE_MISS_READ: begin PCMux = 2'b01; ICacheReadEn = 1'b1; - NextState = STATE_READY; + NextState = STATE_MISS_READ_DELAY; + end + STATE_MISS_READ_DELAY: begin + //PCMux = 2'b01; + ICacheReadEn = 1'b1; + ICacheStallF = 1'b0; + if(StallF) begin + PCMux = 2'b01; + NextState = STATE_CPU_BUSY; + PCMux = 2'b01; + end else begin + NextState = STATE_READY; + end end // branch 4 miss spill hit, and 5 miss spill miss STATE_MISS_SPILL_FETCH_WDV: begin @@ -249,12 +283,17 @@ module icachefsm #(parameter BLOCKLEN = 256) CntReset = 1'b1; NextState = STATE_MISS_SPILL_MISS_FETCH_WDV; end else begin - NextState = STATE_READY; ICacheReadEn = 1'b1; PCMux = 2'b00; UnalignedSelect = 1'b1; SavePC = 1'b1; - ICacheStallF = 1'b0; + ICacheStallF = 1'b0; + if(StallF) begin + NextState = STATE_CPU_BUSY; + PCMux = 2'b01; + end else begin + NextState = STATE_READY; + end end end STATE_MISS_SPILL_MISS_FETCH_WDV: begin @@ -284,7 +323,12 @@ module icachefsm #(parameter BLOCKLEN = 256) UnalignedSelect = 1'b1; SavePC = 1'b1; ICacheStallF = 1'b0; - NextState = STATE_READY; + if(StallF) begin + NextState = STATE_CPU_BUSY; + PCMux = 2'b01; + end else begin + NextState = STATE_READY; + end end STATE_TLB_MISS: begin if (WalkerInstrPageFaultF) begin @@ -297,8 +341,34 @@ module icachefsm #(parameter BLOCKLEN = 256) end end STATE_TLB_MISS_DONE: begin + PCMux = 2'b01; NextState = STATE_READY; end + STATE_CPU_BUSY: begin + ICacheStallF = 1'b0; + if (ITLBMissF) begin + NextState = STATE_TLB_MISS; + end else if(StallF) begin + NextState = STATE_CPU_BUSY; + PCMux = 2'b01; + end + else begin + NextState = STATE_READY; + end + end + STATE_CPU_BUSY_SPILL: begin + ICacheStallF = 1'b0; + ICacheReadEn = 1'b1; + if (ITLBMissF) begin + NextState = STATE_TLB_MISS; + end else if(StallF) begin + NextState = STATE_CPU_BUSY_SPILL; + PCMux = 2'b10; + end + else begin + NextState = STATE_READY; + end + end default: begin PCMux = 2'b01; NextState = STATE_READY;