From 95df88ae70808a9e7943f652c25f1eeb9bd80b77 Mon Sep 17 00:00:00 2001
From: DTowersM <dtowersm@gmail.com>
Date: Tue, 31 May 2022 20:08:04 +0000
Subject: [PATCH] added embench tests to tests.vh

---
 pipelined/testbench/tests.vh | 32 +++++++++++++++++++++++++++++++-
 1 file changed, 31 insertions(+), 1 deletion(-)

diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh
index dba197f5..d907d9a2 100644
--- a/pipelined/testbench/tests.vh
+++ b/pipelined/testbench/tests.vh
@@ -28,6 +28,7 @@
 `define WALLYTEST "2"
 `define MYIMPERASTEST   "3"
 `define COREMARK "4"
+`define EMBENCH "5"
 // *** remove MYIMPERASTEST cases when ported 
 
 string tvpaths[] = '{
@@ -35,15 +36,44 @@ string tvpaths[] = '{
     "../../addins/riscv-arch-test/work/",
     "../../tests/wally-riscv-arch-test/work/",
     "../../tests/imperas-riscv-tests/work/",
-    "../../benchmarks/riscv-coremark/work/"
+    "../../benchmarks/riscv-coremark/work/",
+    "../../addins/embench-iot/bd_speed/src/"
 };
 
+
+
    // *** make sure these are somewhere
   string coremark[] = '{
     `COREMARK,
     "coremark.bare.riscv", "100000"
   };
 
+  string embench[] = '{
+    `EMBENCH,
+    "aha-mont64/aha-mont64", "1080",
+    "crc32/crc32", "1080",
+    "cubic/cubic", "9080",
+    "edn/edn", "1080",
+    "huffbench/huffbench", "5080",
+    "matmult-int/matmult-int", "1080",
+    "md5sum/md5sum", "4080",
+    "minver/minver", "2080",
+    "nbody/nbody", "2080",
+    "nettle-aes/nettle-aes", "1080",
+    "nettle-sha256/nettle-sha256", "2080",
+    "nsichneu/nsichneu", "4080",
+    "picojpeg/picojpeg", "3080",
+    "primecount/primecount", "1080",
+    "qrduino/qrduino", "6080",
+    "sglib-combined/sglib-combined", "5080",
+    "slre/slre", "1080",
+    "st/st", "2080",
+    "statemate/statemate", "2080",
+    "tarfind/tarfind", "4080",
+    "ud/ud", "1080",
+    "wikisort/wikisort", "3080"
+  };
+
   string wally64a[] = '{
     `WALLYTEST,
     "rv64i_m/privilege/WALLY-amo", "2210",