From f4fb546969b0762ed1a5c3db7be5253e994763d4 Mon Sep 17 00:00:00 2001
From: bbracker <bbracker@hmc.edu>
Date: Fri, 12 Mar 2021 20:23:55 -0500
Subject: [PATCH] clint HREADY signal update

---
 wally-pipelined/src/uncore/clint.sv | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/wally-pipelined/src/uncore/clint.sv b/wally-pipelined/src/uncore/clint.sv
index 71770323..e672a769 100644
--- a/wally-pipelined/src/uncore/clint.sv
+++ b/wally-pipelined/src/uncore/clint.sv
@@ -45,9 +45,7 @@ module clint (
   assign memread  = HSELCLINT & ~HWRITE;
   assign memwrite = HSELCLINT & HWRITE;
   assign HRESPCLINT = 0; // OK
-//  assign HREADYCLINT = 1; // Respond immediately
-  always_ff @(posedge HCLK) // delay response
-    HREADYCLINT <= memread | memwrite;
+  assign HREADYCLINT = 1'b1; // will need to be modified if CLINT ever needs more than 1 cycle to do something
   
   // word aligned reads
   generate