From 9395414df3904d67307ebe214538ea9ec2e4998e Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 2 Dec 2022 11:55:23 -0800 Subject: [PATCH] Renamed FPUStallD to FCvtIntStallD --- pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv | 1 - pipelined/src/hazard/hazard.sv | 5 +++-- pipelined/src/ieu/forward.sv | 4 ++-- pipelined/src/ieu/ieu.sv | 4 ++-- pipelined/src/wally/wallypipelinedcore.sv | 6 +++--- 5 files changed, 10 insertions(+), 10 deletions(-) diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv index a1e09d4d..dc9b1efc 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv @@ -58,7 +58,6 @@ module fdivsqrtfsm( logic [`DURLEN-1:0] cycles; logic SpecialCaseE; - // *** start logic is presently in fctl. Make it look more like integer division start logic // FDivStartE and IDivStartE come from fctrl, reflecitng the start of floating-point and possibly integer division assign IFDivStartE = (FDivStartE | IDivStartE) & (state == IDLE) & ~StallM; assign FDivDoneE = (state == DONE); diff --git a/pipelined/src/hazard/hazard.sv b/pipelined/src/hazard/hazard.sv index 7d381f7c..0bd5cbe4 100644 --- a/pipelined/src/hazard/hazard.sv +++ b/pipelined/src/hazard/hazard.sv @@ -35,7 +35,7 @@ module hazard( (* mark_debug = "true" *) input logic BPPredWrongE, CSRWriteFencePendingDEM, RetM, TrapM, (* mark_debug = "true" *) input logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD, (* mark_debug = "true" *) input logic LSUStallM, IFUStallF, -(* mark_debug = "true" *) input logic FPUStallD, FStallD, +(* mark_debug = "true" *) input logic FCvtIntStallD, FStallD, (* mark_debug = "true" *) input logic DivBusyE,FDivBusyE, (* mark_debug = "true" *) input logic EcallFaultM, BreakpointFaultM, (* mark_debug = "true" *) input logic wfiM, IntPendingM, @@ -64,11 +64,12 @@ module hazard( // *** consider replacing CSRWriteFencePendingDEM with a flush rather than a stall. assign StallFCause = CSRWriteFencePendingDEM & ~(TrapM | RetM | BPPredWrongE); // stall in decode if instruction is a load/mul/csr dependent on previous - assign StallDCause = (LoadStallD | StoreStallD | MDUStallD | CSRRdStallD | FPUStallD | FStallD) & ~(TrapM | RetM | BPPredWrongE); + assign StallDCause = (LoadStallD | StoreStallD | MDUStallD | CSRRdStallD | FCvtIntStallD | FStallD) & ~(TrapM | RetM | BPPredWrongE); assign StallECause = (DivBusyE | FDivBusyE) & ~(TrapM); // *** can we move to decode stage (KP?) // WFI terminates if any enabled interrupt is pending, even if global interrupts are disabled. It could also terminate with TW trap assign StallMCause = ((wfiM) & (~TrapM & ~IntPendingM)); assign StallWCause = ((IFUStallF | LSUStallM) & ~TrapM); // | (FDivBusyE & ~TrapM & ~IntPendingM); + // head version // assign StallWCause = LSUStallM | IFUStallF | (FDivBusyE & ~TrapM & ~IntPendingM); // *** FDivBusyE should look like DivBusyE // assign StallMCause = (wfiM & (~TrapM & ~IntPendingM)); // | FDivBusyE; diff --git a/pipelined/src/ieu/forward.sv b/pipelined/src/ieu/forward.sv index 856fbded..da68307c 100644 --- a/pipelined/src/ieu/forward.sv +++ b/pipelined/src/ieu/forward.sv @@ -39,7 +39,7 @@ module forward( input logic SCE, // Forwarding controls output logic [1:0] ForwardAE, ForwardBE, - output logic FPUStallD, LoadStallD, MDUStallD, CSRRdStallD + output logic FCvtIntStallD, LoadStallD, MDUStallD, CSRRdStallD ); logic MatchDE; @@ -58,7 +58,7 @@ module forward( // Stall on dependent operations that finish in Mem Stage and can't bypass in time assign MatchDE = (Rs1D == RdE) | (Rs2D == RdE); // Decode-stage instruction source depends on result from execute stage instruction - assign FPUStallD = FCvtIntE & MatchDE; // FPU to Integer transfers have single-cycle latency except fcvt + assign FCvtIntStallD = FCvtIntE & MatchDE; // FPU to Integer transfers have single-cycle latency except fcvt assign LoadStallD = (MemReadE|SCE) & MatchDE; assign MDUStallD = MDUE & MatchDE; assign CSRRdStallD = CSRReadE & MatchDE; diff --git a/pipelined/src/ieu/ieu.sv b/pipelined/src/ieu/ieu.sv index 6258566f..014d24f6 100644 --- a/pipelined/src/ieu/ieu.sv +++ b/pipelined/src/ieu/ieu.sv @@ -67,7 +67,7 @@ module ieu ( // hazards input logic StallD, StallE, StallM, StallW, input logic FlushD, FlushE, FlushM, FlushW, - output logic FPUStallD, LoadStallD, MDUStallD, CSRRdStallD, + output logic FCvtIntStallD, LoadStallD, MDUStallD, CSRRdStallD, output logic PCSrcE, output logic CSRReadM, CSRWriteM, PrivilegedM, output logic CSRWriteFencePendingDEM, @@ -113,6 +113,6 @@ module ieu ( .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW, .MemReadE, .MDUE, .CSRReadE, .RegWriteM, .RegWriteW, .FCvtIntE, .SCE, .ForwardAE, .ForwardBE, - .FPUStallD, .LoadStallD, .MDUStallD, .CSRRdStallD); + .FCvtIntStallD, .LoadStallD, .MDUStallD, .CSRRdStallD); endmodule diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index ba975395..d189a0b1 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -95,7 +95,7 @@ module wallypipelinedcore ( logic FDivBusyE; logic IllegalFPUInstrM; logic FRegWriteM; - logic FPUStallD; + logic FCvtIntStallD; logic FpLoadStoreM; logic [1:0] FResSelW; logic [4:0] SetFflagsM; @@ -237,7 +237,7 @@ module wallypipelinedcore ( // hazards .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, - .FPUStallD, .LoadStallD, .MDUStallD, .CSRRdStallD, + .FCvtIntStallD, .LoadStallD, .MDUStallD, .CSRRdStallD, .PCSrcE, .CSRReadM, .CSRWriteM, .PrivilegedM, .CSRWriteFencePendingDEM, .StoreStallD @@ -319,7 +319,7 @@ module wallypipelinedcore ( .BPPredWrongE, .CSRWriteFencePendingDEM, .RetM, .TrapM, .LoadStallD, .StoreStallD, .MDUStallD, .CSRRdStallD, .LSUStallM, .IFUStallF, - .FPUStallD, .FStallD, + .FCvtIntStallD, .FStallD, .DivBusyE, .FDivBusyE, .EcallFaultM, .BreakpointFaultM, .wfiM, .IntPendingM,