From 921a49921bbe28a1fb3a0a8a846812b4027d7df8 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 26 Aug 2022 21:05:20 -0700 Subject: [PATCH] Set correct size of IROM/DTIM and allow FLEN>XLEN with DTIM --- pipelined/config/rv64BP/wally-config.vh | 8 ++++---- pipelined/src/ifu/irom.sv | 7 ++----- pipelined/src/lsu/dtim.sv | 3 +-- pipelined/src/mmu/mmu.sv | 3 +-- pipelined/testbench/testbench.sv | 2 +- 5 files changed, 9 insertions(+), 14 deletions(-) diff --git a/pipelined/config/rv64BP/wally-config.vh b/pipelined/config/rv64BP/wally-config.vh index 4ab4e974..bb02b9fb 100644 --- a/pipelined/config/rv64BP/wally-config.vh +++ b/pipelined/config/rv64BP/wally-config.vh @@ -91,11 +91,11 @@ // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits `define DTIM_SUPPORTED 0 -`define DTIM_BASE 34'h80000000 -`define DTIM_RANGE 34'h00001FFF +`define DTIM_BASE 56'h80000000 +`define DTIM_RANGE 56'h00001FFF `define IROM_SUPPORTED 0 -`define IROM_BASE 34'h80000000 -`define IROM_RANGE 34'h00001FFF +`define IROM_BASE 56'h80000000 +`define IROM_RANGE 56'h00001FFF `define BOOTROM_SUPPORTED 1'b1 `define BOOTROM_BASE 56'h00001000 `define BOOTROM_RANGE 56'h00000FFF diff --git a/pipelined/src/ifu/irom.sv b/pipelined/src/ifu/irom.sv index 2670511e..c35d602d 100644 --- a/pipelined/src/ifu/irom.sv +++ b/pipelined/src/ifu/irom.sv @@ -35,12 +35,9 @@ module irom( output logic [31:0] ReadData ); - -// localparam ADDR_WDITH = $clog2(`IROM_RAM_RANGE/8); // *** replace with tihs when defined - localparam ADDR_WDITH = $clog2(`UNCORE_RAM_RANGE/8); // *** this is the wrong size + localparam ADDR_WDITH = $clog2(`IROM_RANGE/8); localparam OFFSET = $clog2(`LLEN/8); - brom1p1r #(ADDR_WDITH, 32) - rom(.clk, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadData)); + brom1p1r #(ADDR_WDITH, 32) rom(.clk, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadData)); endmodule diff --git a/pipelined/src/lsu/dtim.sv b/pipelined/src/lsu/dtim.sv index cbd48dba..6a4ee1f5 100644 --- a/pipelined/src/lsu/dtim.sv +++ b/pipelined/src/lsu/dtim.sv @@ -41,8 +41,7 @@ module dtim( logic we; -// localparam ADDR_WDITH = $clog2(`TIM_RAM_RANGE/8); // *** replace with tihs when defined - localparam ADDR_WDITH = $clog2(`UNCORE_RAM_RANGE/8); // *** this is the wrong size + localparam ADDR_WDITH = $clog2(`DTIM_RANGE/8); localparam OFFSET = $clog2(`LLEN/8); assign we = LSURWM[0] & ~TrapM; // have to ignore write if Trap. diff --git a/pipelined/src/mmu/mmu.sv b/pipelined/src/mmu/mmu.sv index ccf49ce4..dbf23e98 100644 --- a/pipelined/src/mmu/mmu.sv +++ b/pipelined/src/mmu/mmu.sv @@ -128,14 +128,13 @@ module mmu #(parameter TLB_ENTRIES = 8, // number of TLB Entries .AtomicAccessM, .ExecuteAccessF, .WriteAccessM, .ReadAccessM, .Cacheable, .Idempotent, .AtomicAllowed, .PMAInstrAccessFaultF, .PMALoadAccessFaultM, .PMAStoreAmoAccessFaultM); - + pmpchecker pmpchecker(.PhysicalAddress, .PrivilegeModeW, .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, .ExecuteAccessF, .WriteAccessM, .ReadAccessM, .PMPInstrAccessFaultF, .PMPLoadAccessFaultM, .PMPStoreAmoAccessFaultM); // If TLB miss and translating we want to not have faults from the PMA and PMP checkers. -// assign SquashBusAccess = PMASquashBusAccess | PMPSquashBusAccess; assign InstrAccessFaultF = (PMAInstrAccessFaultF | PMPInstrAccessFaultF) & ~(Translate & ~TLBHit); assign LoadAccessFaultM = (PMALoadAccessFaultM | PMPLoadAccessFaultM) & ~(Translate & ~TLBHit); assign StoreAmoAccessFaultM = (PMAStoreAmoAccessFaultM | PMPStoreAmoAccessFaultM) & ~(Translate & ~TLBHit); diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index adb92b5d..57d1ab22 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -439,7 +439,7 @@ module riscvassertions; assert (`F_SUPPORTED | ~`ZFH_SUPPORTED) else $error("Can't support half-precision fp (ZFH) without supporting float (F)"); assert (`DCACHE | ~`F_SUPPORTED | `FLEN <= `XLEN) else $error("Data cache required to support FLEN > XLEN because AHB bus width is XLEN"); assert (`I_SUPPORTED ^ `E_SUPPORTED) else $error("Exactly one of I and E must be supported"); - assert (`FLEN<=`XLEN | `DCACHE) else $error("Wally does not support FLEN > XLEN unleses data cache is supported"); + assert (`FLEN<=`XLEN | `DCACHE | `DTIM_SUPPORTED) else $error("Wally does not support FLEN > XLEN unleses data cache or DTIM is supported"); assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (!`DCACHE) | `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); assert (`DCACHE_LINELENINBITS >= 128 | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled"); assert (`DCACHE_LINELENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size");