From ade4a4cd5e29ff8eca8528657e2f0ae44f3006a1 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 31 Mar 2022 15:48:15 -0500 Subject: [PATCH 1/2] Notes on what to change in ram.sv. --- pipelined/src/uncore/ram.sv | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/pipelined/src/uncore/ram.sv b/pipelined/src/uncore/ram.sv index e9b0af32..2d151d50 100644 --- a/pipelined/src/uncore/ram.sv +++ b/pipelined/src/uncore/ram.sv @@ -43,6 +43,13 @@ module ram #(parameter BASE=0, RANGE = 65535) ( output logic HRESPRam, HREADYRam ); + + // Desired changes. + // 1. find a way to merge read and write address into 1 port. + // 2. remove all unnecessary latencies. (HREADY needs to be able to constant high.) + // 3. implement burst. + // 4. remove the configurable latency. + localparam MemStartAddr = BASE>>(1+`XLEN/32); localparam MemEndAddr = (RANGE+BASE)>>1+(`XLEN/32); From 48c49802b2e743b862c17732805c5750f01c62b0 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 1 Apr 2022 15:20:45 -0500 Subject: [PATCH 2/2] Fixed linting issues. --- pipelined/src/generic/flop/bram2p1r1w.sv | 4 ++-- pipelined/src/uncore/uartPC16550D.sv | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/pipelined/src/generic/flop/bram2p1r1w.sv b/pipelined/src/generic/flop/bram2p1r1w.sv index 58038b8c..485df2aa 100644 --- a/pipelined/src/generic/flop/bram2p1r1w.sv +++ b/pipelined/src/generic/flop/bram2p1r1w.sv @@ -78,8 +78,8 @@ module bram2p1r1w end -----/\----- EXCLUDED -----/\----- */ - initial begin - if(PRELOAD_ENABLED) begin + if(PRELOAD_ENABLED) begin + initial begin RAM[0] = 64'h94e1819300002197; RAM[1] = 64'h4281420141014081; RAM[2] = 64'h4481440143814301; diff --git a/pipelined/src/uncore/uartPC16550D.sv b/pipelined/src/uncore/uartPC16550D.sv index 267e38fd..e2fd7b1c 100644 --- a/pipelined/src/uncore/uartPC16550D.sv +++ b/pipelined/src/uncore/uartPC16550D.sv @@ -310,7 +310,7 @@ module uartPC16550D( if (rxfifohead == rxfifotail +1) rxdataready <= #1 0; end else begin rxdataready <= #1 0; - RXBR <= #1 {0, RXBR[9:0]}; // Ben 31 March 2022: I added this so that rxoverrunerr permanently goes away upon reading RBR (when not in FIFO mode) + RXBR <= #1 {1'b0, RXBR[9:0]}; // Ben 31 March 2022: I added this so that rxoverrunerr permanently goes away upon reading RBR (when not in FIFO mode) end end else if (~MEMWb & A == 3'b010) // writes to FIFO Control Register if (Din[1] | ~Din[0]) begin // rx FIFO reset or FIFO disable clears FIFO contents