From 90eb4fc1f137f70a63a84fd99ec191615c41c104 Mon Sep 17 00:00:00 2001 From: Katherine Parry Date: Thu, 29 Dec 2022 15:54:17 -0600 Subject: [PATCH] minor optimizations and renaming --- pipelined/src/fpu/fma/fma.sv | 8 ++++---- pipelined/src/fpu/fma/fmaadd.sv | 11 ++++++----- pipelined/src/fpu/fma/fmaalign.sv | 9 +++++---- pipelined/src/fpu/fpu.sv | 2 +- pipelined/testbench/testbench-fp.sv | 6 +++--- 5 files changed, 19 insertions(+), 17 deletions(-) diff --git a/pipelined/src/fpu/fma/fma.sv b/pipelined/src/fpu/fma/fma.sv index eb2213da..4d60f477 100644 --- a/pipelined/src/fpu/fma/fma.sv +++ b/pipelined/src/fpu/fma/fma.sv @@ -36,7 +36,7 @@ module fma( input logic [`NF:0] Xm, Ym, Zm, // input's significands in U(0.NF) format input logic XZero, YZero, ZZero, // is the input zero input logic [2:0] OpCtrl, // 000 = fmadd (X*Y)+Z, 001 = fmsub (X*Y)-Z, 010 = fnmsub -(X*Y)+Z, 011 = fnmadd -(X*Y)-Z, 100 = fmul (X*Y) - output logic ZmSticky, // sticky bit that is calculated during alignment + output logic ASticky, // sticky bit that is calculated during alignment output logic [3*`NF+4:0] Sm,//change // the positive sum's significand output logic InvA, // Was A inverted for effective subtraction (P-A or -P+A) output logic As, // the aligned addend's sign (modified Z sign for other opperations) @@ -75,7 +75,7 @@ module fma( fmasign sign(.OpCtrl, .Xs, .Ys, .Zs, .Ps, .As, .InvA); fmaalign align(.Ze, .Zm, .XZero, .YZero, .ZZero, .Xe, .Ye, - .Am, .ZmSticky, .KillProd); + .Am, .ASticky, .KillProd); @@ -83,10 +83,10 @@ module fma( // // Addition/LZA // /////////////////////////////////////////////////////////////////////////////// - fmaadd add(.Am, .Pm, .Ze, .Pe, .Ps, .KillProd, .ZmSticky, .AmInv, .PmKilled, .InvA, .Sm, .Se, .Ss); + fmaadd add(.Am, .Pm, .Ze, .Pe, .Ps, .KillProd, .ASticky, .AmInv, .PmKilled, .InvA, .Sm, .Se, .Ss); //change - fmalza #(3*`NF+5) lza(.A(AmInv), .Pm({PmKilled, 1'b0, InvA&Ps&ZmSticky&KillProd}), .Cin(InvA & ~(ZmSticky & ~KillProd)), .sub(InvA), .SCnt); + fmalza #(3*`NF+5) lza(.A(AmInv), .Pm({PmKilled, 1'b0, InvA&Ps&ASticky&KillProd}), .Cin(InvA & ~(ASticky & ~KillProd)), .sub(InvA), .SCnt); endmodule diff --git a/pipelined/src/fpu/fma/fmaadd.sv b/pipelined/src/fpu/fma/fmaadd.sv index 0991e44b..509adb67 100644 --- a/pipelined/src/fpu/fma/fmaadd.sv +++ b/pipelined/src/fpu/fma/fmaadd.sv @@ -36,7 +36,7 @@ module fmaadd( input logic Ps, // the product sign and the alligend addeded's sign (Modified Z sign for other opperations) input logic InvA, // invert the aligned addend input logic KillProd, // should the product be set to 0 - input logic ZmSticky, + input logic ASticky, input logic [`NE-1:0] Ze, input logic [`NE+1:0] Pe, output logic [3*`NF+4:0] AmInv,//change // aligned addend possibly inverted @@ -62,11 +62,12 @@ module fmaadd( // - calculate a positive and negitive sum in parallel // if there was a small negitive number killed in the alignment stage one needs to be subtracted from the sum // prod - addend where some of the addend is put into the sticky bit then don't add +1 from negation - // ie ~(InvA&ZmSticky&~KillProd)&InvA = (~ZmSticky|KillProd)&InvA + // ie ~(InvA&ASticky&~KillProd)&InvA = (~ASticky|KillProd)&InvA // addend - prod where product is killed (and not exactly zero) then don't add +1 from negation - // ie ~(InvA&ZmSticky&KillProd)&InvA = (~ZmSticky|~KillProd)&InvA - assign {NegSum, PreSum} = {{`NF+2{1'b0}}, PmKilled, 2'b0} + {InvA, AmInv} + {{3*`NF+5{1'b0}}, (~ZmSticky|KillProd)&InvA};//change - assign NegPreSum = Am + {{`NF+1{1'b1}}, ~PmKilled, 2'b0} + {(3*`NF+2)'(0), (~ZmSticky|~KillProd)&InvA, 2'b0};//change + // ie ~(InvA&ASticky&KillProd)&InvA = (~ASticky|~KillProd)&InvA + // in this case this result is only ever selected when InvA=1 so we can remove &InvA + assign {NegSum, PreSum} = {{`NF+2{1'b0}}, PmKilled, 2'b0} + {InvA, AmInv} + {{3*`NF+5{1'b0}}, (~ASticky|KillProd)&InvA};//change + assign NegPreSum = Am + {{`NF+1{1'b1}}, ~PmKilled, 2'b0} + {(3*`NF+2)'(0), ~ASticky|~KillProd, 2'b0};//change // Choose the positive sum and accompanying LZA result. assign Sm = NegSum ? NegPreSum : PreSum; diff --git a/pipelined/src/fpu/fma/fmaalign.sv b/pipelined/src/fpu/fma/fmaalign.sv index 85b28c7b..67dc0b82 100644 --- a/pipelined/src/fpu/fma/fmaalign.sv +++ b/pipelined/src/fpu/fma/fmaalign.sv @@ -36,7 +36,7 @@ module fmaalign( input logic [`NF:0] Zm, // significand in U(0.NF) format] input logic XZero, YZero, ZZero, // is the input zero output logic [3*`NF+4:0] Am,//change // addend aligned for addition in U(NF+5.2NF+1) - output logic ZmSticky, // Sticky bit calculated from the aliged addend + output logic ASticky, // Sticky bit calculated from the aliged addend output logic KillProd // should the product be set to zero ); @@ -44,6 +44,7 @@ module fmaalign( logic [4*`NF+4:0] ZmShifted;//change // output of the alignment shifter including sticky bits U(NF+5.3NF+1) logic [4*`NF+4:0] ZmPreshifted;//change // input to the alignment shifter U(NF+5.3NF+1) logic KillZ; + logic PmSticky, tmpZmSticky; /////////////////////////////////////////////////////////////////////////////// // Alignment shifter @@ -73,7 +74,7 @@ module fmaalign( // | addnend | if (KillProd) begin ZmShifted = {(`NF+2)'(0), Zm, (2*`NF+2)'(0)};//change - ZmSticky = ~(XZero|YZero); + ASticky = ~(XZero|YZero); // If the addend is too small to effect the addition // - The addend has to shift two past the end of the product to be considered too small @@ -83,14 +84,14 @@ module fmaalign( // | addnend | end else if (KillZ) begin ZmShifted = 0; - ZmSticky = ~ZZero; + ASticky = ~ZZero; // If the Addend is shifted right // | 54'b0 | 106'b(product) | 2'b0 | // | addnend | end else begin ZmShifted = ZmPreshifted >> ACnt; - ZmSticky = |(ZmShifted[`NF-1:0]); + ASticky = |(ZmShifted[`NF-1:0]); end end diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index 1ebd391c..507cd908 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -258,7 +258,7 @@ module fpu ( .As(AsE), .Ps(PsE), .Ss(SsE), .Se(SeE), .Sm(SmE), .InvA(InvAE), .SCnt(SCntE), - .ZmSticky(ZmStickyE)); + .ASticky(ZmStickyE)); // divide and squareroot // - fdiv diff --git a/pipelined/testbench/testbench-fp.sv b/pipelined/testbench/testbench-fp.sv index d0953482..f5986c83 100644 --- a/pipelined/testbench/testbench-fp.sv +++ b/pipelined/testbench/testbench-fp.sv @@ -92,7 +92,7 @@ module testbenchfp; logic Ss; logic [`NE+1:0] Pe; logic [`NE+1:0] Se; - logic ZmSticky; + logic ASticky; logic KillProd; logic [$clog2(3*`NF+6)-1:0] SCnt; logic [3*`NF+4:0] Sm; @@ -690,7 +690,7 @@ module testbenchfp; .Xm(Xm), .Ym(Ym), .Zm(Zm), .XZero, .YZero, .ZZero, .Ss, .Se, .OpCtrl(OpCtrlVal), .Sm, .InvA, .SCnt, .As, .Ps, - .ZmSticky); + .ASticky); end postprocess postprocess(.Xs(Xs), .Ys(Ys), .PostProcSel(UnitVal[1:0]), @@ -700,7 +700,7 @@ module testbenchfp; .XZero(XZero), .YZero(YZero), .ZZero(ZZero), .CvtShiftAmt(CvtShiftAmtE), .XInf(XInf), .YInf(YInf), .ZInf(ZInf), .CvtCs(CvtResSgnE), .ToInt(WriteIntVal), .XSNaN(XSNaN), .YSNaN(YSNaN), .ZSNaN(ZSNaN), .CvtLzcIn(CvtLzcInE), .IntZero, - .FmaZmS(ZmSticky), .FmaSe(Se), + .FmaZmS(ASticky), .FmaSe(Se), .FmaSm(Sm), .FmaSCnt(SCnt), .FmaAs(As), .FmaPs(Ps), .Fmt(ModFmt), .Frm(FrmVal), .PostProcFlg(Flg), .PostProcRes(FpRes), .FCvtIntRes(IntRes));