From 8fa0fc422990a49bb39ccae13eaf669cbff4d37c Mon Sep 17 00:00:00 2001 From: Katherine Parry Date: Mon, 6 Jun 2022 16:06:04 +0000 Subject: [PATCH] fma synth warnings and errors removed --- pipelined/config/rv64fp/wally-config.vh | 3 +- pipelined/config/shared/wally-shared.vh | 58 +++--- pipelined/regression/lint-wally | 2 +- pipelined/regression/sim-wally | 2 +- pipelined/src/fpu/fctrl.sv | 2 +- pipelined/src/fpu/fcvt.sv | 39 ++-- pipelined/src/fpu/fma.sv | 20 +- pipelined/src/fpu/fpu.sv | 46 +++-- pipelined/src/fpu/unpack.sv | 10 +- pipelined/testbench/testbench-fp.sv | 232 ++++++++++++------------ 10 files changed, 217 insertions(+), 197 deletions(-) diff --git a/pipelined/config/rv64fp/wally-config.vh b/pipelined/config/rv64fp/wally-config.vh index d7ad9d3c..dd5a6b49 100644 --- a/pipelined/config/rv64fp/wally-config.vh +++ b/pipelined/config/rv64fp/wally-config.vh @@ -38,7 +38,8 @@ `define IEEE754 0 // MISA RISC-V configuration per specification -`define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 ) +// ZYXWVUTSRQPONMLKJIHGFEDCBA +`define MISA 32'b0000000000101000001000100101101 `define ZICSR_SUPPORTED 1 `define ZIFENCEI_SUPPORTED 1 `define COUNTERS 32 diff --git a/pipelined/config/shared/wally-shared.vh b/pipelined/config/shared/wally-shared.vh index 7d1ad112..e2d5cf75 100644 --- a/pipelined/config/shared/wally-shared.vh +++ b/pipelined/config/shared/wally-shared.vh @@ -51,43 +51,45 @@ `define PMPCFG_ENTRIES (`PMP_ENTRIES/8) // Floating point constants for Quad, Double, Single, and Half precisions -`define Q_LEN 128 -`define Q_NE 15 -`define Q_NF 112 -`define Q_BIAS 16383 -`define D_LEN 64 -`define D_NE 11 -`define D_NF 52 -`define D_BIAS 1023 -`define S_LEN 32 -`define S_NE 8 -`define S_NF 23 -`define S_BIAS 127 -`define H_LEN 16 -`define H_NE 5 -`define H_NF 10 -`define H_BIAS 15 +`define Q_LEN 32'd128 +`define Q_NE 32'd15 +`define Q_NF 32'd112 +`define Q_BIAS 32'd16383 +`define D_LEN 32'd64 +`define D_NE 32'd11 +`define D_NF 32'd52 +`define D_BIAS 32'd1023 +`define D_FMT 32'd1 +`define S_LEN 32'd32 +`define S_NE 32'd8 +`define S_NF 32'd23 +`define S_BIAS 32'd127 +`define S_FMT 32'd1 +`define H_LEN 32'd16 +`define H_NE 32'd5 +`define H_NF 32'd10 +`define H_BIAS 32'd15 // Floating point length FLEN and number of exponent (NE) and fraction (NF) bits `define FLEN (`Q_SUPPORTED ? `Q_LEN : `D_SUPPORTED ? `D_LEN : `F_SUPPORTED ? `S_LEN : `H_LEN) `define NE (`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `F_SUPPORTED ? `S_NE : `H_NE) `define NF (`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `F_SUPPORTED ? `S_NF : `H_NF) -`define FMT (`Q_SUPPORTED ? 3 : `D_SUPPORTED ? 1 : `F_SUPPORTED ? 0 : 2) +`define FMT (`Q_SUPPORTED ? 2'd3 : `D_SUPPORTED ? 2'd1 : `F_SUPPORTED ? 2'd0 : 2'd2) `define BIAS (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `F_SUPPORTED ? `S_BIAS : `H_BIAS) // Floating point constants needed for FPU paramerterization -`define FPSIZES ((3)'(`Q_SUPPORTED)+(3)'(`D_SUPPORTED)+(3)'(`F_SUPPORTED)+(3)'(`ZFH_SUPPORTED)) -`define FMTBITS (((`FPSIZES==3'b011)|(`FPSIZES==3'b100)) ? 2 : 1) -`define LEN1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_LEN : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_LEN : `H_LEN) -`define NE1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NE : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NE : `H_NE) -`define NF1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NF : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NF : `H_NF) -`define FMT1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? 1 : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? 0 : 2) -`define BIAS1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_BIAS : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_BIAS : `H_BIAS) -`define LEN2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_LEN : `H_LEN) +`define FPSIZES ((32)'(`Q_SUPPORTED)+(32)'(`D_SUPPORTED)+(32)'(`F_SUPPORTED)+(32)'(`ZFH_SUPPORTED)) +`define FMTBITS ((`FPSIZES>=3)+1) +`define LEN1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_LEN : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_LEN : `H_LEN) +`define NE1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NE : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NE : `H_NE) +`define NF1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NF : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NF : `H_NF) +`define FMT1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? 2'd1 : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? 2'd0 : 2'd2) +`define BIAS1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_BIAS : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_BIAS : `H_BIAS) +`define LEN2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_LEN : `H_LEN) `define NE2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NE : `H_NE) -`define NF2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NF : `H_NF) -`define FMT2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? 0 : 2) -`define BIAS2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_BIAS : `H_BIAS) +`define NF2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NF : `H_NF) +`define FMT2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? 2'd0 : 2'd2) +`define BIAS2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_BIAS : `H_BIAS) // Disable spurious Verilator warnings diff --git a/pipelined/regression/lint-wally b/pipelined/regression/lint-wally index 1bf23bd8..2b5288d5 100755 --- a/pipelined/regression/lint-wally +++ b/pipelined/regression/lint-wally @@ -5,7 +5,7 @@ export PATH=$PATH:/usr/local/bin/ verilator=`which verilator` basepath=$(dirname $0)/.. -for config in rv64fp rv32e rv64gc rv32gc rv32ic; do +for config in rv64fp rv64fpquad rv32e rv64gc rv32gc rv32ic; do echo "$config linting..." if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes); then echo "Exiting after $config lint due to errors or warnings" diff --git a/pipelined/regression/sim-wally b/pipelined/regression/sim-wally index 22d539ea..a7dffc9e 100755 --- a/pipelined/regression/sim-wally +++ b/pipelined/regression/sim-wally @@ -1,2 +1,2 @@ -vsim -do "do wally-pipelined.do rv32e imperas64d" +vsim -do "do wally-pipelined.do rv32gc arch32f" diff --git a/pipelined/src/fpu/fctrl.sv b/pipelined/src/fpu/fctrl.sv index 108d923c..406c0ec3 100755 --- a/pipelined/src/fpu/fctrl.sv +++ b/pipelined/src/fpu/fctrl.sv @@ -122,7 +122,7 @@ module fctrl ( else if (`FPSIZES == 2)begin logic [1:0] FmtTmp; assign FmtTmp = (FResultSelD == 2'b00) ? {~Funct3D[1], ~(Funct3D[1]^Funct3D[0])} : ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : Funct7D[1:0]; - assign FmtD = `FMT == FmtTmp; + assign FmtD = (`FMT == FmtTmp); end else if (`FPSIZES == 3|`FPSIZES == 4) assign FmtD = (FResultSelD == 2'b00) ? {~Funct3D[1], ~(Funct3D[1]^Funct3D[0])} : ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : Funct7D[1:0]; diff --git a/pipelined/src/fpu/fcvt.sv b/pipelined/src/fpu/fcvt.sv index b8b5a107..d9fbe77c 100644 --- a/pipelined/src/fpu/fcvt.sv +++ b/pipelined/src/fpu/fcvt.sv @@ -2,6 +2,7 @@ `include "wally-config.vh" // largest length in IEU/FPU `define LGLEN ((`NF<`XLEN) ? `XLEN : `NF) +`define LOGLGLEN $unsigned($clog2(`LGLEN+1)) module fcvt ( input logic XSgnE, // input's sign @@ -42,7 +43,7 @@ module fcvt ( logic [`XLEN-1:0] TrimInt; // integer trimmed to the correct size logic [`LGLEN-1:0] LzcIn; // input to the Leading Zero Counter (priority encoder) logic [`NE:0] CalcExp; // the calculated expoent - logic [$clog2(`LGLEN+1)-1:0] ShiftAmt; // how much to shift by + logic [`LOGLGLEN-1:0] ShiftAmt; // how much to shift by logic [`LGLEN+`NF:0] ShiftIn; // number to be shifted logic ResDenormUf;// does the result underflow or is denormalized logic ResUf; // does the result underflow @@ -72,7 +73,7 @@ module fcvt ( logic Int64; // is the integer 64 bits? logic IntToFp; // is the opperation an int->fp conversion? logic ToInt; // is the opperation an fp->int conversion? - logic [$clog2(`LGLEN+1)-1:0] ZeroCnt; // output from the LZC + logic [`LOGLGLEN-1:0] ZeroCnt; // output from the LZC // seperate OpCtrl for code readability @@ -143,9 +144,9 @@ module fcvt ( // - only shift fp -> fp if the intital value is denormalized // - this is a problem because the input to the lzc was the fraction rather than the mantissa // - rather have a few and-gates than an extra bit in the priority encoder??? *** is this true? - assign ShiftAmt = ToInt ? CalcExp[$clog2(`LGLEN+1)-1:0]&{$clog2(`LGLEN+1){~CalcExp[`NE]}} : - ResDenormUf&~IntToFp ? ($clog2(`LGLEN+1))'(`NF-1)+CalcExp[$clog2(`LGLEN+1)-1:0] : - (ZeroCnt+1)&{$clog2(`LGLEN+1){XDenormE|IntToFp}}; + assign ShiftAmt = ToInt ? CalcExp[`LOGLGLEN-1:0]&{`LOGLGLEN{~CalcExp[`NE]}} : + ResDenormUf&~IntToFp ? (`LOGLGLEN)'(`NF-1)+CalcExp[`LOGLGLEN-1:0] : + (ZeroCnt+1)&{`LOGLGLEN{XDenormE|IntToFp}}; // shift // fp -> int: | `XLEN zeros | Mantissa | 0's if nessisary | << CalcExp @@ -261,34 +262,34 @@ module fcvt ( // - shift left to normilize (-1-ZeroCnt) // - newBias to make the biased exponent // - assign CalcExp = {1'b0, OldExp} - (`NE+1)'(`BIAS) + {2'b0, NewBias} - {{`NE{1'b0}}, XDenormE|IntToFp} - {{`NE-$clog2(`LGLEN+1)+1{1'b0}}, (ZeroCnt&{$clog2(`LGLEN+1){XDenormE|IntToFp}})}; + assign CalcExp = {1'b0, OldExp} - (`NE+1)'(`BIAS) + {2'b0, NewBias} - {{`NE{1'b0}}, XDenormE|IntToFp} - {{`NE-`LOGLGLEN+1{1'b0}}, (ZeroCnt&{`LOGLGLEN{XDenormE|IntToFp}})}; // find if the result is dnormal or underflows // - if Calculated expoenent is 0 or negitive (and the input/result is not exactaly 0) // - can't underflow an integer to Fp conversion assign ResDenormUf = (~|CalcExp | CalcExp[`NE])&~XZeroE&~IntToFp; // choose the negative of the fraction size if (`FPSIZES == 1) begin - assign ResNegNF = -`NF; + assign ResNegNF = -($clog2(`NF)+1)'(`NF); end else if (`FPSIZES == 2) begin - assign ResNegNF = OutFmt ? -`NF : -`NF1; + assign ResNegNF = OutFmt ? -($clog2(`NF)+1)'(`NF) : -($clog2(`NF)+1)'(`NF1); end else if (`FPSIZES == 3) begin always_comb case (OutFmt) - `FMT: ResNegNF = -`NF; - `FMT1: ResNegNF = -`NF1; - `FMT2: ResNegNF = -`NF2; + `FMT: ResNegNF = -($clog2(`NF)+1)'(`NF); + `FMT1: ResNegNF = -($clog2(`NF)+1)'(`NF1); + `FMT2: ResNegNF = -($clog2(`NF)+1)'(`NF2); default: ResNegNF = 1'bx; endcase end else if (`FPSIZES == 4) begin always_comb case (OutFmt) - 2'h3: ResNegNF = -`Q_NF; - 2'h1: ResNegNF = -`D_NF; - 2'h0: ResNegNF = -`S_NF; - 2'h2: ResNegNF = -`H_NF; + 2'h3: ResNegNF = -($clog2(`NF)+1)'(`Q_NF); + 2'h1: ResNegNF = -($clog2(`NF)+1)'(`D_NF); + 2'h0: ResNegNF = -($clog2(`NF)+1)'(`S_NF); + 2'h2: ResNegNF = -($clog2(`NF)+1)'(`H_NF); endcase end // determine if the result underflows ??? -> fp @@ -453,10 +454,10 @@ module fcvt ( // find the maximum exponent (the exponent and larger overflows) if (`FPSIZES == 1) begin - assign MaxExp = ToInt ? Int64 ? 65 : 33 : {`NE{1'b1}}; + assign MaxExp = ToInt ? Int64 ? (`NE)'(65) : (`NE)'(33) : {`NE{1'b1}}; end else if (`FPSIZES == 2) begin - assign MaxExp = ToInt ? Int64 ? 65 : 33 : + assign MaxExp = ToInt ? Int64 ? (`NE)'($unsigned(65)) : (`NE)'($unsigned(33)) : OutFmt ? {`NE{1'b1}} : {{`NE-`NE1{1'b0}}, {`NE1{1'b1}}}; end else if (`FPSIZES == 3) begin @@ -476,7 +477,7 @@ module fcvt ( MaxExpFp = 1'bx; end endcase - assign MaxExp = ToInt ? Int64 ? 65 : 33 : MaxExpFp; + assign MaxExp = ToInt ? Int64 ? (`NE)'(65) : (`NE)'(33) : MaxExpFp; end else if (`FPSIZES == 4) begin logic [`NE-1:0] MaxExpFp; @@ -495,7 +496,7 @@ module fcvt ( MaxExpFp = {{`Q_NE-`H_NE{1'b0}}, {`H_NE{1'b1}}}; end endcase - assign MaxExp = ToInt ? Int64 ? 65 : 33 : MaxExpFp; + assign MaxExp = ToInt ? Int64 ? (`NE)'(65) : (`NE)'(33) : MaxExpFp; end // if the result exponent is larger then the maximum possible exponent diff --git a/pipelined/src/fpu/fma.sv b/pipelined/src/fpu/fma.sv index 1658a064..0cb2c064 100644 --- a/pipelined/src/fpu/fma.sv +++ b/pipelined/src/fpu/fma.sv @@ -81,7 +81,7 @@ module fma( // E/M pipeline registers flopenrc #(3*`NF+6) EMRegFma2(clk, reset, FlushM, ~StallM, SumE, SumM); - flopenrc #(13) EMRegFma3(clk, reset, FlushM, ~StallM, ProdExpE, ProdExpM); + flopenrc #(`NE+2) EMRegFma3(clk, reset, FlushM, ~StallM, ProdExpE, ProdExpM); flopenrc #($clog2(3*`NF+7)+8) EMRegFma4(clk, reset, FlushM, ~StallM, {AddendStickyE, KillProdE, InvZE, NormCntE, NegSumE, ZSgnEffE, PSgnE, FOpCtrlE[2]&~FOpCtrlE[1]&~FOpCtrlE[0], ZDenormE}, {AddendStickyM, KillProdM, InvZM, NormCntM, NegSumM, ZSgnEffM, PSgnM, Mult, ZDenormM}); @@ -237,7 +237,7 @@ module align( // - positive means the product is larger, so shift Z right // *** can we use ProdExpE instead of XExp/YExp to save an adder? DH 5/12/22 // KP- yes we used ProdExpE originally but we did this for timing - assign AlignCnt = XZeroE|YZeroE ? -1 : {2'b0, XExpE} + {2'b0, YExpE} - {2'b0, (`NE)'(`BIAS)} + `NF+3 - {2'b0, ZExpE}; + assign AlignCnt = XZeroE|YZeroE ? -(`NE+2)'($unsigned(1)) : {2'b0, XExpE} + {2'b0, YExpE} - {2'b0, (`NE)'(`BIAS)} + (`NE+2)'(`NF)+3 - {2'b0, ZExpE}; // Defualt Addition without shifting // | 54'b0 | 106'b(product) | 2'b0 | @@ -320,7 +320,7 @@ module add( // Do the addition // - calculate a positive and negitive sum in parallel - assign PreSum = AlignedAddendInv + {55'b0, ProdManKilled, 2'b0} + {{3*`NF+6{1'b0}}, InvZE}; + assign PreSum = AlignedAddendInv + {{`NF+3{1'b0}}, ProdManKilled, 2'b0} + {{3*`NF+6{1'b0}}, InvZE}; assign NegPreSum = XZeroE|YZeroE|KillProdE ? {1'b0, AlignedAddendE} : {1'b0, AlignedAddendE} + {{`NF+3{1'b1}}, ~ProdManKilled, 2'b0} + {(3*`NF+7)'(4)}; // Is the sum negitive @@ -543,7 +543,7 @@ module normalize( assign SumZero = ~(|SumM); // calculate the sum's exponent - assign SumExpTmpTmp = KillProdM ? {2'b0, ZExpM[`NE-1:1], ZExpM[0]&~ZDenormM} : ProdExpM + -({4'b0, NormCntM} + 1 - (`NF+4)); + assign SumExpTmpTmp = KillProdM ? {2'b0, ZExpM[`NE-1:1], ZExpM[0]&~ZDenormM} : ProdExpM + -({{`NE+2-$unsigned($clog2(3*`NF+7)){1'b0}}, NormCntM} + 1 - (`NE+2)'(`NF+4)); //convert the sum's exponent into the propper percision if (`FPSIZES == 1) begin @@ -556,8 +556,8 @@ module normalize( always_comb begin case (FmtM) `FMT: SumExpTmp = SumExpTmpTmp; - `FMT1: SumExpTmp = (SumExpTmpTmp-`BIAS+`BIAS1)&{`NE+2{|SumExpTmpTmp}}; - `FMT2: SumExpTmp = (SumExpTmpTmp-`BIAS+`BIAS2)&{`NE+2{|SumExpTmpTmp}}; + `FMT1: SumExpTmp = (SumExpTmpTmp-(`NE+2)'(`BIAS)+(`NE+2)'(`BIAS1))&{`NE+2{|SumExpTmpTmp}}; + `FMT2: SumExpTmp = (SumExpTmpTmp-(`NE+2)'(`BIAS)+(`NE+2)'(`BIAS2))&{`NE+2{|SumExpTmpTmp}}; default: SumExpTmp = `NE+2'bx; endcase end @@ -566,9 +566,9 @@ module normalize( always_comb begin case (FmtM) 2'h3: SumExpTmp = SumExpTmpTmp; - 2'h1: SumExpTmp = (SumExpTmpTmp-`BIAS+`D_BIAS)&{`NE+2{|SumExpTmpTmp}}; - 2'h0: SumExpTmp = (SumExpTmpTmp-`BIAS+`S_BIAS)&{`NE+2{|SumExpTmpTmp}}; - 2'h2: SumExpTmp = (SumExpTmpTmp-`BIAS+`H_BIAS)&{`NE+2{|SumExpTmpTmp}}; + 2'h1: SumExpTmp = (SumExpTmpTmp-(`NE+2)'(`BIAS)+(`NE+2)'(`D_BIAS))&{`NE+2{|SumExpTmpTmp}}; + 2'h0: SumExpTmp = (SumExpTmpTmp-(`NE+2)'(`BIAS)+(`NE+2)'(`S_BIAS))&{`NE+2{|SumExpTmpTmp}}; + 2'h2: SumExpTmp = (SumExpTmpTmp-(`NE+2)'(`BIAS)+(`NE+2)'(`H_BIAS))&{`NE+2{|SumExpTmpTmp}}; endcase end @@ -674,7 +674,7 @@ module normalize( // Determine sum's exponent // if plus1 If plus2 if said denorm but norm plus 1 if said denorm but norm plus 2 - assign SumExp = (SumExpTmp+{12'b0, LZAPlus1&~KillProdM}+{11'b0, LZAPlus2&~KillProdM, 1'b0}+{12'b0, ~ResultDenorm&PreResultDenorm&~KillProdM}+{12'b0, &SumExpTmp&SumShifted[3*`NF+6]&~KillProdM}) & {`NE+2{~(SumZero|ResultDenorm)}}; + assign SumExp = (SumExpTmp+{{`NE+1{1'b0}}, LZAPlus1&~KillProdM}+{{`NE{1'b0}}, LZAPlus2&~KillProdM, 1'b0}+{{`NE+1{1'b0}}, ~ResultDenorm&PreResultDenorm&~KillProdM}+{{`NE+1{1'b0}}, &SumExpTmp&SumShifted[3*`NF+6]&~KillProdM}) & {`NE+2{~(SumZero|ResultDenorm)}}; // recalculate if the result is denormalized assign ResultDenorm = PreResultDenorm&~SumShifted[3*`NF+6]&~SumShifted[3*`NF+7]; diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index a45e2bbe..c8d1e3c6 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -107,7 +107,7 @@ module fpu ( logic FOpCtrlQ; // result and flag signals - logic [`FLEN-1:0] FDivResM, FDivResW; // divide/squareroot result + logic [63:0] FDivResM, FDivResW; // divide/squareroot result logic [4:0] FDivFlgM; // divide/squareroot flags logic [`FLEN-1:0] FMAResM, FMAResW; // FMA/multiply result logic [4:0] FMAFlgM; // FMA/multiply result @@ -125,7 +125,7 @@ module fpu ( logic [`FLEN-1:0] FPUResultW; // final FP result being written to the FP register // other signals logic FDivSqrtDoneE; // is divide done - logic [`FLEN-1:0] DivInput1E, DivInput2E; // inputs to divide/squareroot unit + logic [63:0] DivInput1E, DivInput2E; // inputs to divide/squareroot unit logic load_preload; // enable for FF on fpdivsqrt logic [`FLEN-1:0] AlignedSrcAE; // align SrcA to the floating point format logic [`FLEN-1:0] BoxedZeroE; // Zero value for Z for multiplication, with NaN boxing if needed @@ -184,11 +184,11 @@ module fpu ( generate if(`FPSIZES == 1) assign BoxedZeroE = 0; else if(`FPSIZES == 2) - mux2 #(`FLEN) fmulzeromux ({{`FLEN-`LEN1{1'b1}}, {`FLEN-`LEN1{1'b0}}}, (`FLEN)'(0), FmtE, BoxedZeroE); // NaN boxing zeroes + mux2 #(`FLEN) fmulzeromux ({{`FLEN-`LEN1{1'b1}}, {`LEN1{1'b0}}}, (`FLEN)'(0), FmtE, BoxedZeroE); // NaN boxing zeroes else if(`FPSIZES == 3 | `FPSIZES == 4) - mux4 #(`FLEN) fmulzeromux ({{`FLEN-`S_LEN{1'b1}}, (`FLEN-`S_LEN)'(0)}, - {{`FLEN-`D_LEN{1'b1}}, (`FLEN-`D_LEN)'(0)}, - {{`FLEN-`H_LEN{1'b1}}, (`FLEN-`H_LEN)'(0)}, + mux4 #(`FLEN) fmulzeromux ({{`FLEN-`S_LEN{1'b1}}, {`S_LEN{1'b0}}}, + {{`FLEN-`D_LEN{1'b1}}, {`D_LEN{1'b0}}}, + {{`FLEN-`H_LEN{1'b1}}, {`H_LEN{1'b0}}}, (`FLEN)'(0), FmtE, BoxedZeroE); // NaN boxing zeroes endgenerate @@ -218,17 +218,27 @@ module fpu ( .FMAFlgM, .FMAResM); // fpdivsqrt using Goldschmidt's iteration - flopenrc #(`FLEN) reg_input1 (.d({XSgnE, XExpE, XManE[51:0]}), .q(DivInput1E), + if(`FLEN == 64) begin + flopenrc #(64) reg_input1 (.d({FSrcXE[63:0]}), .q(DivInput1E), .clear(FDivSqrtDoneE), .en(load_preload), .reset(reset), .clk(clk)); - flopenrc #(`FLEN) reg_input2 (.d({YSgnE, YExpE, YManE[51:0]}), .q(DivInput2E), + flopenrc #(64) reg_input2 (.d({FSrcYE[63:0]}), .q(DivInput2E), .clear(FDivSqrtDoneE), .en(load_preload), .reset(reset), .clk(clk)); - flopenrc #(8+int'(`FMTBITS-1)) reg_input3 (.d({XNaNE, YNaNE, XInfE, YInfE, XZeroE, YZeroE, FmtE, FOpCtrlE[0]}), + end + else if (`FLEN == 32) begin + flopenrc #(64) reg_input1 (.d({32'b0, FSrcXE[31:0]}), .q(DivInput1E), + .clear(FDivSqrtDoneE), .en(load_preload), + .reset(reset), .clk(clk)); + flopenrc #(64) reg_input2 (.d({32'b0, FSrcYE[31:0]}), .q(DivInput2E), + .clear(FDivSqrtDoneE), .en(load_preload), + .reset(reset), .clk(clk)); + end + flopenrc #(8) reg_input3 (.d({XNaNE, YNaNE, XInfE, YInfE, XZeroE, YZeroE, FmtE[0], FOpCtrlE[0]}), .q({XNaNQ, YNaNQ, XInfQ, YInfQ, XZeroQ, YZeroQ, FmtQ, FOpCtrlQ}), .clear(FDivSqrtDoneE), .en(load_preload), .reset(reset), .clk(clk)); - fpdiv_pipe fdivsqrt (.op1(DivInput1E), .op2(DivInput2E), .rm(FrmE[1:0]), .op_type(FOpCtrlQ), + fpdiv_pipe fdivsqrt (.op1(DivInput1E[63:0]), .op2(DivInput2E[63:0]), .rm(FrmE[1:0]), .op_type(FOpCtrlQ), .reset, .clk(clk), .start(FDivStartE), .P(~FmtQ), .OvEn(1'b1), .UnEn(1'b1), .XNaNQ, .YNaNQ, .XInfQ, .YInfQ, .XZeroQ, .YZeroQ, .load_preload, .FDivBusyE, .done(FDivSqrtDoneE), .AS_Result(FDivResM), .Flags(FDivFlgM)); @@ -244,7 +254,8 @@ module fpu ( // data to be stored in memory - to IEU // - FP uses NaN-blocking format // - if there are any unsused bits the most significant bits are filled with 1s - assign FWriteDataE = FSrcYE[`XLEN-1:0]; + if (`FLEN>`XLEN) assign FWriteDataE = FSrcYE[`XLEN-1:0]; + else assign FWriteDataE = {{`XLEN-`FLEN{FSrcYE[`FLEN-1]}}, FSrcYE}; // NaN Block SrcA generate @@ -262,8 +273,12 @@ module fpu ( mux4 #(5) FFlgMux(5'b0, 5'b0, {CmpNVE, 4'b0}, CvtFlgE, FResSelE, FFlgE); // select the result that may be written to the integer register - to IEU - mux4 #(`XLEN) IntResMux(CmpResE[`XLEN-1:0], FSrcXE[`XLEN-1:0], ClassResE, - CvtIntResE, FIntResSelE, FIntResE); + if (`FLEN>`XLEN) + mux4 #(`XLEN) IntResMux(CmpResE[`XLEN-1:0], FSrcXE[`XLEN-1:0], ClassResE, + CvtIntResE, FIntResSelE, FIntResE); + else + mux4 #(`XLEN) IntResMux({{`XLEN-`FLEN{CmpResE[`FLEN-1:0]}}, CmpResE}, {{`XLEN-`FLEN{FSrcXE[`FLEN-1:0]}}, FSrcXE}, ClassResE, + CvtIntResE, FIntResSelE, FIntResE); // *** DH 5/25/22: CvtRes will move to mem stage. Premux in execute to save area, then make sure stalls are ok // *** make sure the fpu matches the chapter diagram @@ -290,7 +305,7 @@ module fpu ( // M/W pipe registers flopenrc #(`FLEN) MWRegFma(clk, reset, FlushW, ~StallW, FMAResM, FMAResW); - flopenrc #(`FLEN) MWRegDiv(clk, reset, FlushW, ~StallW, FDivResM, FDivResW); + flopenrc #(64) MWRegDiv(clk, reset, FlushW, ~StallW, FDivResM, FDivResW); flopenrc #(`FLEN) MWRegClass(clk, reset, FlushW, ~StallW, FResM, FResW); flopenrc #(4+int'(`FMTBITS-1)) MWCtrlReg(clk, reset, FlushW, ~StallW, {FRegWriteM, FResultSelM, FmtM}, @@ -313,5 +328,6 @@ module fpu ( endgenerate // select the result to be written to the FP register - mux4 #(`FLEN) FPUResultMux (ReadResW, FMAResW, FDivResW, FResW, FResultSelW, FPUResultW); + if(`FLEN>=64) + mux4 #(`FLEN) FPUResultMux (ReadResW, FMAResW, {{`FLEN-64{1'b0}},FDivResW}, FResW, FResultSelW, FPUResultW); endmodule // fpu diff --git a/pipelined/src/fpu/unpack.sv b/pipelined/src/fpu/unpack.sv index 73b867aa..506109da 100644 --- a/pipelined/src/fpu/unpack.sv +++ b/pipelined/src/fpu/unpack.sv @@ -1,11 +1,11 @@ `include "wally-config.vh" module unpack ( - input logic [$signed(`FLEN)-$signed(1):0] X, Y, Z, // inputs from register file - input logic [$signed(`FMTBITS)-$signed(1):0] FmtE, // format signal 00 - single 01 - double 11 - quad 10 - half + input logic [`FLEN-1:0] X, Y, Z, // inputs from register file + input logic [`FMTBITS-1:0] FmtE, // format signal 00 - single 01 - double 11 - quad 10 - half output logic XSgnE, YSgnE, ZSgnE, // sign bits of XYZ - output logic [$signed(`NE)-$signed(1):0] XExpE, YExpE, ZExpE, // exponents of XYZ (converted to largest supported precision) - output logic [$signed(`NF):0] XManE, YManE, ZManE, // mantissas of XYZ (converted to largest supported precision) + output logic [`NE-1:0] XExpE, YExpE, ZExpE, // exponents of XYZ (converted to largest supported precision) + output logic [`NF:0] XManE, YManE, ZManE, // mantissas of XYZ (converted to largest supported precision) output logic XNaNE, YNaNE, ZNaNE, // is XYZ a NaN output logic XSNaNE, YSNaNE, ZSNaNE, // is XYZ a signaling NaN output logic XDenormE, ZDenormE, // is XYZ denormalized @@ -14,7 +14,7 @@ module unpack ( output logic XExpMaxE // does X have the maximum exponent (NaN or Inf) ); - logic [$signed(`NF)-$signed(1):0] XFracE, YFracE, ZFracE; //Fraction of XYZ + logic [`NF-1:0] XFracE, YFracE, ZFracE; //Fraction of XYZ logic XExpNonZero, YExpNonZero, ZExpNonZero; // is the exponent of XYZ non-zero logic XFracZero, YFracZero, ZFracZero; // is the fraction zero logic YExpMaxE, ZExpMaxE; // is the exponent all 1s diff --git a/pipelined/testbench/testbench-fp.sv b/pipelined/testbench/testbench-fp.sv index e74dd45b..1a27c833 100644 --- a/pipelined/testbench/testbench-fp.sv +++ b/pipelined/testbench/testbench-fp.sv @@ -261,26 +261,26 @@ module testbenchfp; Fmt = {Fmt, 2'b11}; end end - if (TEST === "div" | TEST === "all") begin // if division is being tested - // add the divide tests/op-ctrls/unit/fmt - Tests = {Tests, f128div}; - OpCtrl = {OpCtrl, `DIV_OPCTRL}; - WriteInt = {WriteInt, 1'b0}; - for(int i = 0; i<5; i++) begin - Unit = {Unit, `DIVUNIT}; - Fmt = {Fmt, 2'b11}; - end - end - if (TEST === "sqrt" | TEST === "all") begin // if square-root is being tested - // add the square-root tests/op-ctrls/unit/fmt - Tests = {Tests, f128sqrt}; - OpCtrl = {OpCtrl, `SQRT_OPCTRL}; - WriteInt = {WriteInt, 1'b0}; - for(int i = 0; i<5; i++) begin - Unit = {Unit, `DIVUNIT}; - Fmt = {Fmt, 2'b11}; - end - end + // if (TEST === "div" | TEST === "all") begin // if division is being tested + // // add the divide tests/op-ctrls/unit/fmt + // Tests = {Tests, f128div}; + // OpCtrl = {OpCtrl, `DIV_OPCTRL}; + // WriteInt = {WriteInt, 1'b0}; + // for(int i = 0; i<5; i++) begin + // Unit = {Unit, `DIVUNIT}; + // Fmt = {Fmt, 2'b11}; + // end + // end + // if (TEST === "sqrt" | TEST === "all") begin // if square-root is being tested + // // add the square-root tests/op-ctrls/unit/fmt + // Tests = {Tests, f128sqrt}; + // OpCtrl = {OpCtrl, `SQRT_OPCTRL}; + // WriteInt = {WriteInt, 1'b0}; + // for(int i = 0; i<5; i++) begin + // Unit = {Unit, `DIVUNIT}; + // Fmt = {Fmt, 2'b11}; + // end + // end if (TEST === "fma" | TEST === "all") begin // if fused-mutliply-add is being tested // add each rounding mode to it's own list of tests // - fma tests are very long, so run all rounding modes in parallel @@ -390,26 +390,26 @@ module testbenchfp; Fmt = {Fmt, 2'b01}; end end - if (TEST === "div" | TEST === "all") begin // if division is being tested - // add the correct tests/op-ctrls/unit/fmt to their lists - Tests = {Tests, f64div}; - OpCtrl = {OpCtrl, `DIV_OPCTRL}; - WriteInt = {WriteInt, 1'b0}; - for(int i = 0; i<5; i++) begin - Unit = {Unit, `DIVUNIT}; - Fmt = {Fmt, 2'b01}; - end - end - if (TEST === "sqrt" | TEST === "all") begin // if square-root is being tessted - // add the correct tests/op-ctrls/unit/fmt to their lists - Tests = {Tests, f64sqrt}; - OpCtrl = {OpCtrl, `SQRT_OPCTRL}; - WriteInt = {WriteInt, 1'b0}; - for(int i = 0; i<5; i++) begin - Unit = {Unit, `DIVUNIT}; - Fmt = {Fmt, 2'b01}; - end - end + // if (TEST === "div" | TEST === "all") begin // if division is being tested + // // add the correct tests/op-ctrls/unit/fmt to their lists + // Tests = {Tests, f64div}; + // OpCtrl = {OpCtrl, `DIV_OPCTRL}; + // WriteInt = {WriteInt, 1'b0}; + // for(int i = 0; i<5; i++) begin + // Unit = {Unit, `DIVUNIT}; + // Fmt = {Fmt, 2'b01}; + // end + // end + // if (TEST === "sqrt" | TEST === "all") begin // if square-root is being tessted + // // add the correct tests/op-ctrls/unit/fmt to their lists + // Tests = {Tests, f64sqrt}; + // OpCtrl = {OpCtrl, `SQRT_OPCTRL}; + // WriteInt = {WriteInt, 1'b0}; + // for(int i = 0; i<5; i++) begin + // Unit = {Unit, `DIVUNIT}; + // Fmt = {Fmt, 2'b01}; + // end + // end if (TEST === "fma" | TEST === "all") begin // if the fused multiply add is being tested // add each rounding mode to it's own list of tests // - fma tests are very long, so run all rounding modes in parallel @@ -502,26 +502,26 @@ module testbenchfp; Fmt = {Fmt, 2'b00}; end end - if (TEST === "div" | TEST === "all") begin // if division is being tested - // add the correct tests/op-ctrls/unit/fmt to their lists - Tests = {Tests, f32div}; - OpCtrl = {OpCtrl, `DIV_OPCTRL}; - WriteInt = {WriteInt, 1'b0}; - for(int i = 0; i<5; i++) begin - Unit = {Unit, `DIVUNIT}; - Fmt = {Fmt, 2'b00}; - end - end - if (TEST === "sqrt" | TEST === "all") begin // if sqrt is being tested - // add the correct tests/op-ctrls/unit/fmt to their lists - Tests = {Tests, f32sqrt}; - OpCtrl = {OpCtrl, `SQRT_OPCTRL}; - WriteInt = {WriteInt, 1'b0}; - for(int i = 0; i<5; i++) begin - Unit = {Unit, `DIVUNIT}; - Fmt = {Fmt, 2'b00}; - end - end + // if (TEST === "div" | TEST === "all") begin // if division is being tested + // // add the correct tests/op-ctrls/unit/fmt to their lists + // Tests = {Tests, f32div}; + // OpCtrl = {OpCtrl, `DIV_OPCTRL}; + // WriteInt = {WriteInt, 1'b0}; + // for(int i = 0; i<5; i++) begin + // Unit = {Unit, `DIVUNIT}; + // Fmt = {Fmt, 2'b00}; + // end + // end + // if (TEST === "sqrt" | TEST === "all") begin // if sqrt is being tested + // // add the correct tests/op-ctrls/unit/fmt to their lists + // Tests = {Tests, f32sqrt}; + // OpCtrl = {OpCtrl, `SQRT_OPCTRL}; + // WriteInt = {WriteInt, 1'b0}; + // for(int i = 0; i<5; i++) begin + // Unit = {Unit, `DIVUNIT}; + // Fmt = {Fmt, 2'b00}; + // end + // end if (TEST === "fma" | TEST === "all") begin // if fma is being tested // add each rounding mode to it's own list of tests // - fma tests are very long, so run all rounding modes in parallel @@ -596,26 +596,26 @@ module testbenchfp; Fmt = {Fmt, 2'b10}; end end - if (TEST === "div" | TEST === "all") begin // if division is being tested - // add the correct tests/op-ctrls/unit/fmt to their lists - Tests = {Tests, f16div}; - OpCtrl = {OpCtrl, `DIV_OPCTRL}; - WriteInt = {WriteInt, 1'b0}; - for(int i = 0; i<5; i++) begin - Unit = {Unit, `DIVUNIT}; - Fmt = {Fmt, 2'b10}; - end - end - if (TEST === "sqrt" | TEST === "all") begin // if sqrt is being tested - // add the correct tests/op-ctrls/unit/fmt to their lists - Tests = {Tests, f16sqrt}; - OpCtrl = {OpCtrl, `SQRT_OPCTRL}; - WriteInt = {WriteInt, 1'b0}; - for(int i = 0; i<5; i++) begin - Unit = {Unit, `DIVUNIT}; - Fmt = {Fmt, 2'b10}; - end - end + // if (TEST === "div" | TEST === "all") begin // if division is being tested + // // add the correct tests/op-ctrls/unit/fmt to their lists + // Tests = {Tests, f16div}; + // OpCtrl = {OpCtrl, `DIV_OPCTRL}; + // WriteInt = {WriteInt, 1'b0}; + // for(int i = 0; i<5; i++) begin + // Unit = {Unit, `DIVUNIT}; + // Fmt = {Fmt, 2'b10}; + // end + // end + // if (TEST === "sqrt" | TEST === "all") begin // if sqrt is being tested + // // add the correct tests/op-ctrls/unit/fmt to their lists + // Tests = {Tests, f16sqrt}; + // OpCtrl = {OpCtrl, `SQRT_OPCTRL}; + // WriteInt = {WriteInt, 1'b0}; + // for(int i = 0; i<5; i++) begin + // Unit = {Unit, `DIVUNIT}; + // Fmt = {Fmt, 2'b10}; + // end + // end if (TEST === "fma" | TEST === "all") begin // if fma is being tested // add each rounding mode to it's own list of tests // - fma tests are very long, so run all rounding modes in parallel @@ -673,10 +673,10 @@ module testbenchfp; // - 1 for the larger precision // - 0 for the smaller precision always_comb begin - if(`FMTBITS == 2) ModFmt = FmtVal; - else ModFmt = FmtVal === `FMT; - if(`FMTBITS == 2) FmaModFmt = FmaFmtVal; - else FmaModFmt = FmaFmtVal === `FMT; + if(`FMTBITS == 1) ModFmt = FmtVal == `FMT; + else ModFmt = FmtVal; + if(`FMTBITS == 1) FmaModFmt = FmaFmtVal == `FMT; + else FmaModFmt = FmaFmtVal; end // extract the inputs (X, Y, Z, SrcA) and the output (Ans, AnsFlg) from the current test vector @@ -1028,111 +1028,111 @@ end // - the sign of the NaN does not matter for the opperations being tested // - when 2 or more NaNs are inputed the NaN that is propigated doesn't matter case (FmaFmtVal) - 4'b11: FmaRneNaNGood =(((`IEEE754==0)&(FmaRneRes === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + 4'b11: FmaRneNaNGood =(((`IEEE754==0)&FmaRneAnsNaN&(FmaRneRes === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | (FmaRneAnsFlg[4]&(FmaRneRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | (FmaRneXNaN&(FmaRneRes[`Q_LEN-2:0] === {FmaRneX[`Q_LEN-2:`Q_NF],1'b1,FmaRneX[`Q_NF-2:0]})) | (FmaRneYNaN&(FmaRneRes[`Q_LEN-2:0] === {FmaRneY[`Q_LEN-2:`Q_NF],1'b1,FmaRneY[`Q_NF-2:0]})) | (FmaRneZNaN&(FmaRneRes[`Q_LEN-2:0] === {FmaRneZ[`Q_LEN-2:`Q_NF],1'b1,FmaRneZ[`Q_NF-2:0]}))); - 4'b01: FmaRneNaNGood =(((`IEEE754==0)&(FmaRneRes === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + 4'b01: FmaRneNaNGood =(((`IEEE754==0)&FmaRneAnsNaN&(FmaRneRes[`D_LEN-1:0] === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | (FmaRneAnsFlg[4]&(FmaRneRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | (FmaRneXNaN&(FmaRneRes[`D_LEN-2:0] === {FmaRneX[`D_LEN-2:`D_NF],1'b1,FmaRneX[`D_NF-2:0]})) | (FmaRneYNaN&(FmaRneRes[`D_LEN-2:0] === {FmaRneY[`D_LEN-2:`D_NF],1'b1,FmaRneY[`D_NF-2:0]})) | (FmaRneZNaN&(FmaRneRes[`D_LEN-2:0] === {FmaRneZ[`D_LEN-2:`D_NF],1'b1,FmaRneZ[`D_NF-2:0]}))); - 4'b00: FmaRneNaNGood =(((`IEEE754==0)&(FmaRneRes === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + 4'b00: FmaRneNaNGood =(((`IEEE754==0)&FmaRneAnsNaN&(FmaRneRes[`S_LEN-1:0] === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | (FmaRneAnsFlg[4]&(FmaRneRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | (FmaRneXNaN&(FmaRneRes[`S_LEN-2:0] === {FmaRneX[`S_LEN-2:`S_NF],1'b1,FmaRneX[`S_NF-2:0]})) | (FmaRneYNaN&(FmaRneRes[`S_LEN-2:0] === {FmaRneY[`S_LEN-2:`S_NF],1'b1,FmaRneY[`S_NF-2:0]})) | (FmaRneZNaN&(FmaRneRes[`S_LEN-2:0] === {FmaRneZ[`S_LEN-2:`S_NF],1'b1,FmaRneZ[`S_NF-2:0]}))); - 4'b10: FmaRneNaNGood =(((`IEEE754==0)&(FmaRneRes === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + 4'b10: FmaRneNaNGood =(((`IEEE754==0)&FmaRneAnsNaN&(FmaRneRes[`H_LEN-1:0] === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | (FmaRneAnsFlg[4]&(FmaRneRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | (FmaRneXNaN&(FmaRneRes[`H_LEN-2:0] === {FmaRneX[`H_LEN-2:`H_NF],1'b1,FmaRneX[`H_NF-2:0]})) | (FmaRneYNaN&(FmaRneRes[`H_LEN-2:0] === {FmaRneY[`H_LEN-2:`H_NF],1'b1,FmaRneY[`H_NF-2:0]})) | (FmaRneZNaN&(FmaRneRes[`H_LEN-2:0] === {FmaRneZ[`H_LEN-2:`H_NF],1'b1,FmaRneZ[`H_NF-2:0]}))); endcase case (FmaFmtVal) - 4'b11: FmaRzNaNGood = (((`IEEE754==0)&(FmaRneRes === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + 4'b11: FmaRzNaNGood = (((`IEEE754==0)&FmaRzAnsNaN&(FmaRzRes === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | (FmaRzAnsFlg[4]&(FmaRzRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | (FmaRzXNaN&(FmaRzRes[`Q_LEN-2:0] === {FmaRzX[`Q_LEN-2:`Q_NF],1'b1,FmaRzX[`Q_NF-2:0]})) | (FmaRzYNaN&(FmaRzRes[`Q_LEN-2:0] === {FmaRzY[`Q_LEN-2:`Q_NF],1'b1,FmaRzY[`Q_NF-2:0]})) | (FmaRzZNaN&(FmaRzRes[`Q_LEN-2:0] === {FmaRzZ[`Q_LEN-2:`Q_NF],1'b1,FmaRzZ[`Q_NF-2:0]}))); - 4'b01: FmaRzNaNGood = (((`IEEE754==0)&(FmaRneRes === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + 4'b01: FmaRzNaNGood = (((`IEEE754==0)&FmaRzAnsNaN&(FmaRzRes[`D_LEN-1:0] === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | (FmaRzAnsFlg[4]&(FmaRzRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | (FmaRzXNaN&(FmaRzRes[`D_LEN-2:0] === {FmaRzX[`D_LEN-2:`D_NF],1'b1,FmaRzX[`D_NF-2:0]})) | (FmaRzYNaN&(FmaRzRes[`D_LEN-2:0] === {FmaRzY[`D_LEN-2:`D_NF],1'b1,FmaRzY[`D_NF-2:0]})) | (FmaRzZNaN&(FmaRzRes[`D_LEN-2:0] === {FmaRzZ[`D_LEN-2:`D_NF],1'b1,FmaRzZ[`D_NF-2:0]}))); - 4'b00: FmaRzNaNGood = (((`IEEE754==0)&(FmaRneRes === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + 4'b00: FmaRzNaNGood = (((`IEEE754==0)&FmaRzAnsNaN&(FmaRzRes[`S_LEN-1:0] === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | (FmaRzAnsFlg[4]&(FmaRzRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | (FmaRzXNaN&(FmaRzRes[`S_LEN-2:0] === {FmaRzX[`S_LEN-2:`S_NF],1'b1,FmaRzX[`S_NF-2:0]})) | (FmaRzYNaN&(FmaRzRes[`S_LEN-2:0] === {FmaRzY[`S_LEN-2:`S_NF],1'b1,FmaRzY[`S_NF-2:0]})) | (FmaRzZNaN&(FmaRzRes[`S_LEN-2:0] === {FmaRzZ[`S_LEN-2:`S_NF],1'b1,FmaRzZ[`S_NF-2:0]}))); - 4'b10: FmaRzNaNGood = (((`IEEE754==0)&(FmaRneRes === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + 4'b10: FmaRzNaNGood = (((`IEEE754==0)&FmaRzAnsNaN&(FmaRzRes[`H_LEN-1:0] === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | (FmaRzAnsFlg[4]&(FmaRzRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | (FmaRzXNaN&(FmaRzRes[`H_LEN-2:0] === {FmaRzX[`H_LEN-2:`H_NF],1'b1,FmaRzX[`H_NF-2:0]})) | (FmaRzYNaN&(FmaRzRes[`H_LEN-2:0] === {FmaRzY[`H_LEN-2:`H_NF],1'b1,FmaRzY[`H_NF-2:0]})) | (FmaRzZNaN&(FmaRzRes[`H_LEN-2:0] === {FmaRzZ[`H_LEN-2:`H_NF],1'b1,FmaRzZ[`H_NF-2:0]}))); endcase case (FmaFmtVal) - 4'b11: FmaRuNaNGood = (((`IEEE754==0)&(FmaRneRes === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + 4'b11: FmaRuNaNGood = (((`IEEE754==0)&FmaRuAnsNaN&(FmaRuRes === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | (FmaRuAnsFlg[4]&(FmaRuRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | (FmaRuXNaN&(FmaRuRes[`Q_LEN-2:0] === {FmaRuX[`Q_LEN-2:`Q_NF],1'b1,FmaRuX[`Q_NF-2:0]})) | (FmaRuYNaN&(FmaRuRes[`Q_LEN-2:0] === {FmaRuY[`Q_LEN-2:`Q_NF],1'b1,FmaRuY[`Q_NF-2:0]})) | (FmaRuZNaN&(FmaRuRes[`Q_LEN-2:0] === {FmaRuZ[`Q_LEN-2:`Q_NF],1'b1,FmaRuZ[`Q_NF-2:0]}))); - 4'b01: FmaRuNaNGood = (((`IEEE754==0)&(FmaRneRes === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + 4'b01: FmaRuNaNGood = (((`IEEE754==0)&FmaRuAnsNaN&(FmaRuRes[`D_LEN-1:0] === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | (FmaRuAnsFlg[4]&(FmaRuRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | (FmaRuAnsFlg[4]&(FmaRuRes[`Q_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF{1'b0}}})) | (FmaRuXNaN&(FmaRuRes[`D_LEN-2:0] === {FmaRuX[`D_LEN-2:`D_NF],1'b1,FmaRuX[`D_NF-2:0]})) | (FmaRuYNaN&(FmaRuRes[`D_LEN-2:0] === {FmaRuY[`D_LEN-2:`D_NF],1'b1,FmaRuY[`D_NF-2:0]})) | (FmaRuZNaN&(FmaRuRes[`D_LEN-2:0] === {FmaRuZ[`D_LEN-2:`D_NF],1'b1,FmaRuZ[`D_NF-2:0]}))); - 4'b00: FmaRuNaNGood = (((`IEEE754==0)&(FmaRneRes === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + 4'b00: FmaRuNaNGood = (((`IEEE754==0)&FmaRuAnsNaN&(FmaRuRes[`S_LEN-1:0] === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | (FmaRuAnsFlg[4]&(FmaRuRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | (FmaRuXNaN&(FmaRuRes[`S_LEN-2:0] === {FmaRuX[`S_LEN-2:`S_NF],1'b1,FmaRuX[`S_NF-2:0]})) | (FmaRuYNaN&(FmaRuRes[`S_LEN-2:0] === {FmaRuY[`S_LEN-2:`S_NF],1'b1,FmaRuY[`S_NF-2:0]})) | (FmaRuZNaN&(FmaRuRes[`S_LEN-2:0] === {FmaRuZ[`S_LEN-2:`S_NF],1'b1,FmaRuZ[`S_NF-2:0]}))); - 4'b10: FmaRuNaNGood = (((`IEEE754==0)&(FmaRneRes === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + 4'b10: FmaRuNaNGood = (((`IEEE754==0)&FmaRuAnsNaN&(FmaRuRes[`H_LEN-1:0] === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | (FmaRuAnsFlg[4]&(FmaRuRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | (FmaRuXNaN&(FmaRuRes[`H_LEN-2:0] === {FmaRuX[`H_LEN-2:`H_NF],1'b1,FmaRuX[`H_NF-2:0]})) | (FmaRuYNaN&(FmaRuRes[`H_LEN-2:0] === {FmaRuY[`H_LEN-2:`H_NF],1'b1,FmaRuY[`H_NF-2:0]})) | (FmaRuZNaN&(FmaRuRes[`H_LEN-2:0] === {FmaRuZ[`H_LEN-2:`H_NF],1'b1,FmaRuZ[`H_NF-2:0]}))); endcase case (FmaFmtVal) - 4'b11: FmaRdNaNGood = (((`IEEE754==0)&(FmaRneRes === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + 4'b11: FmaRdNaNGood = (((`IEEE754==0)&FmaRdAnsNaN&(FmaRdRes === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | (FmaRdAnsFlg[4]&(FmaRdRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | (FmaRdXNaN&(FmaRdRes[`Q_LEN-2:0] === {FmaRdX[`Q_LEN-2:`Q_NF],1'b1,FmaRdX[`Q_NF-2:0]})) | (FmaRdYNaN&(FmaRdRes[`Q_LEN-2:0] === {FmaRdY[`Q_LEN-2:`Q_NF],1'b1,FmaRdY[`Q_NF-2:0]})) | (FmaRdZNaN&(FmaRdRes[`Q_LEN-2:0] === {FmaRdZ[`Q_LEN-2:`Q_NF],1'b1,FmaRdZ[`Q_NF-2:0]}))); - 4'b01: FmaRdNaNGood = (((`IEEE754==0)&(FmaRneRes === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + 4'b01: FmaRdNaNGood = (((`IEEE754==0)&FmaRdAnsNaN&(FmaRdRes[`D_LEN-1:0] === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | (FmaRdAnsFlg[4]&(FmaRdRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | (FmaRdXNaN&(FmaRdRes[`D_LEN-2:0] === {FmaRdX[`D_LEN-2:`D_NF],1'b1,FmaRdX[`D_NF-2:0]})) | (FmaRdYNaN&(FmaRdRes[`D_LEN-2:0] === {FmaRdY[`D_LEN-2:`D_NF],1'b1,FmaRdY[`D_NF-2:0]})) | (FmaRdZNaN&(FmaRdRes[`D_LEN-2:0] === {FmaRdZ[`D_LEN-2:`D_NF],1'b1,FmaRdZ[`D_NF-2:0]}))); - 4'b00: FmaRdNaNGood = (((`IEEE754==0)&(FmaRneRes === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + 4'b00: FmaRdNaNGood = (((`IEEE754==0)&FmaRdAnsNaN&(FmaRdRes[`S_LEN-1:0] === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | (FmaRdAnsFlg[4]&(FmaRdRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | (FmaRdXNaN&(FmaRdRes[`S_LEN-2:0] === {FmaRdX[`S_LEN-2:`S_NF],1'b1,FmaRdX[`S_NF-2:0]})) | (FmaRdYNaN&(FmaRdRes[`S_LEN-2:0] === {FmaRdY[`S_LEN-2:`S_NF],1'b1,FmaRdY[`S_NF-2:0]})) | (FmaRdZNaN&(FmaRdRes[`S_LEN-2:0] === {FmaRdZ[`S_LEN-2:`S_NF],1'b1,FmaRdZ[`S_NF-2:0]}))); - 4'b10: FmaRdNaNGood = (((`IEEE754==0)&(FmaRneRes === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + 4'b10: FmaRdNaNGood = (((`IEEE754==0)&FmaRdAnsNaN&(FmaRdRes[`H_LEN-1:0] === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | (FmaRdAnsFlg[4]&(FmaRdRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | (FmaRdXNaN&(FmaRdRes[`H_LEN-2:0] === {FmaRdX[`H_LEN-2:`H_NF],1'b1,FmaRdX[`H_NF-2:0]})) | (FmaRdYNaN&(FmaRdRes[`H_LEN-2:0] === {FmaRdY[`H_LEN-2:`H_NF],1'b1,FmaRdY[`H_NF-2:0]})) | (FmaRdZNaN&(FmaRdRes[`H_LEN-2:0] === {FmaRdZ[`H_LEN-2:`H_NF],1'b1,FmaRdZ[`H_NF-2:0]}))); endcase case (FmaFmtVal) - 4'b11: FmaRnmNaNGood =(((`IEEE754==0)&(FmaRneRes === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + 4'b11: FmaRnmNaNGood =(((`IEEE754==0)&FmaRnmAnsNaN&(FmaRnmRes === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | (FmaRnmAnsFlg[4]&(FmaRnmRes[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | (FmaRnmXNaN&(FmaRnmRes[`Q_LEN-2:0] === {FmaRnmX[`Q_LEN-2:`Q_NF],1'b1,FmaRnmX[`Q_NF-2:0]})) | (FmaRnmYNaN&(FmaRnmRes[`Q_LEN-2:0] === {FmaRnmY[`Q_LEN-2:`Q_NF],1'b1,FmaRnmY[`Q_NF-2:0]})) | (FmaRnmZNaN&(FmaRnmRes[`Q_LEN-2:0] === {FmaRnmZ[`Q_LEN-2:`Q_NF],1'b1,FmaRnmZ[`Q_NF-2:0]}))); - 4'b01: FmaRnmNaNGood =(((`IEEE754==0)&(FmaRneRes === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + 4'b01: FmaRnmNaNGood =(((`IEEE754==0)&FmaRnmAnsNaN&(FmaRnmRes[`D_LEN-1:0] === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | (FmaRnmAnsFlg[4]&(FmaRnmRes[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | (FmaRnmXNaN&(FmaRnmRes[`D_LEN-2:0] === {FmaRnmX[`D_LEN-2:`D_NF],1'b1,FmaRnmX[`D_NF-2:0]})) | (FmaRnmYNaN&(FmaRnmRes[`D_LEN-2:0] === {FmaRnmY[`D_LEN-2:`D_NF],1'b1,FmaRnmY[`D_NF-2:0]})) | (FmaRnmZNaN&(FmaRnmRes[`D_LEN-2:0] === {FmaRnmZ[`D_LEN-2:`D_NF],1'b1,FmaRnmZ[`D_NF-2:0]}))); - 4'b00: FmaRnmNaNGood =(((`IEEE754==0)&(FmaRneRes === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + 4'b00: FmaRnmNaNGood =(((`IEEE754==0)&FmaRnmAnsNaN&(FmaRnmRes[`S_LEN-1:0] === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | (FmaRnmAnsFlg[4]&(FmaRnmRes[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | (FmaRnmXNaN&(FmaRnmRes[`S_LEN-2:0] === {FmaRnmX[`S_LEN-2:`S_NF],1'b1,FmaRnmX[`S_NF-2:0]})) | (FmaRnmYNaN&(FmaRnmRes[`S_LEN-2:0] === {FmaRnmY[`S_LEN-2:`S_NF],1'b1,FmaRnmY[`S_NF-2:0]})) | (FmaRnmZNaN&(FmaRnmRes[`S_LEN-2:0] === {FmaRnmZ[`S_LEN-2:`S_NF],1'b1,FmaRnmZ[`S_NF-2:0]}))); - 4'b10: FmaRnmNaNGood =(((`IEEE754==0)&(FmaRneRes === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + 4'b10: FmaRnmNaNGood =(((`IEEE754==0)&FmaRnmAnsNaN&(FmaRnmRes[`H_LEN-1:0] === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | (FmaRnmAnsFlg[4]&(FmaRnmRes[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | (FmaRnmXNaN&(FmaRnmRes[`H_LEN-2:0] === {FmaRnmX[`H_LEN-2:`H_NF],1'b1,FmaRnmX[`H_NF-2:0]})) | (FmaRnmYNaN&(FmaRnmRes[`H_LEN-2:0] === {FmaRnmY[`H_LEN-2:`H_NF],1'b1,FmaRnmY[`H_NF-2:0]})) | @@ -1140,22 +1140,22 @@ end endcase if (UnitVal !== `CVTFPUNIT & UnitVal !== `CVTINTUNIT) case (FmtVal) - 4'b11: NaNGood = (((`IEEE754==0)&(Res === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + 4'b11: NaNGood = (((`IEEE754==0)&AnsNaN&(Res === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | (AnsFlg[4]&(Res[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | (XNaN&(Res[`Q_LEN-2:0] === {X[`Q_LEN-2:`Q_NF],1'b1,X[`Q_NF-2:0]})) | (YNaN&(Res[`Q_LEN-2:0] === {Y[`Q_LEN-2:`Q_NF],1'b1,Y[`Q_NF-2:0]})) | (ZNaN&(Res[`Q_LEN-2:0] === {Z[`Q_LEN-2:`Q_NF],1'b1,Z[`Q_NF-2:0]}))); - 4'b01: NaNGood = (((`IEEE754==0)&(Res === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + 4'b01: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`D_LEN-1:0] === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | (AnsFlg[4]&(Res[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | (XNaN&(Res[`D_LEN-2:0] === {X[`D_LEN-2:`D_NF],1'b1,X[`D_NF-2:0]})) | (YNaN&(Res[`D_LEN-2:0] === {Y[`D_LEN-2:`D_NF],1'b1,Y[`D_NF-2:0]})) | (ZNaN&(Res[`D_LEN-2:0] === {Z[`D_LEN-2:`D_NF],1'b1,Z[`D_NF-2:0]}))); - 4'b00: NaNGood = (((`IEEE754==0)&(Res === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + 4'b00: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`S_LEN-1:0] === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | (AnsFlg[4]&(Res[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | (XNaN&(Res[`S_LEN-2:0] === {X[`S_LEN-2:`S_NF],1'b1,X[`S_NF-2:0]})) | (YNaN&(Res[`S_LEN-2:0] === {Y[`S_LEN-2:`S_NF],1'b1,Y[`S_NF-2:0]})) | (ZNaN&(Res[`S_LEN-2:0] === {Z[`S_LEN-2:`S_NF],1'b1,Z[`S_NF-2:0]}))); - 4'b10: NaNGood = (((`IEEE754==0)&(Res === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + 4'b10: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`H_LEN-1:0] === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | (AnsFlg[4]&(Res[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | (XNaN&(Res[`H_LEN-2:0] === {X[`H_LEN-2:`H_NF],1'b1,X[`H_NF-2:0]})) | (YNaN&(Res[`H_LEN-2:0] === {Y[`H_LEN-2:`H_NF],1'b1,Y[`H_NF-2:0]})) | @@ -1163,22 +1163,22 @@ end endcase else if (UnitVal === `CVTFPUNIT) // if converting from floating point to floating point OpCtrl contains the final FP format case (OpCtrlVal[1:0]) - 2'b11: NaNGood = (((`IEEE754==0)&(Res === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + 2'b11: NaNGood = (((`IEEE754==0)&AnsNaN&(Res === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | (AnsFlg[4]&(Res[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | (AnsNaN&(Res[`Q_LEN-2:0] === Ans[`Q_LEN-2:0])) | (XNaN&(Res[`Q_LEN-2:0] === {X[`Q_LEN-2:`Q_NF],1'b1,X[`Q_NF-2:0]})) | (YNaN&(Res[`Q_LEN-2:0] === {Y[`Q_LEN-2:`Q_NF],1'b1,Y[`Q_NF-2:0]}))); - 2'b01: NaNGood = (((`IEEE754==0)&(Res === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + 2'b01: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`D_LEN-1:0] === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | (AnsFlg[4]&(Res[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | (AnsNaN&(Res[`D_LEN-2:0] === Ans[`D_LEN-2:0])) | (XNaN&(Res[`D_LEN-2:0] === {X[`D_LEN-2:`D_NF],1'b1,X[`D_NF-2:0]})) | (YNaN&(Res[`D_LEN-2:0] === {Y[`D_LEN-2:`D_NF],1'b1,Y[`D_NF-2:0]}))); - 2'b00: NaNGood = (((`IEEE754==0)&(Res === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + 2'b00: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`S_LEN-1:0] === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | (AnsFlg[4]&(Res[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | (AnsNaN&(Res[`S_LEN-2:0] === Ans[`S_LEN-2:0])) | (XNaN&(Res[`S_LEN-2:0] === {X[`S_LEN-2:`S_NF],1'b1,X[`S_NF-2:0]})) | (YNaN&(Res[`S_LEN-2:0] === {Y[`S_LEN-2:`S_NF],1'b1,Y[`S_NF-2:0]}))); - 2'b10: NaNGood = (((`IEEE754==0)&(Res === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + 2'b10: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`H_LEN-1:0] === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | (AnsFlg[4]&(Res[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | (AnsNaN&(Res[`H_LEN-2:0] === Ans[`H_LEN-2:0])) | (XNaN&(Res[`H_LEN-2:0] === {X[`H_LEN-2:`H_NF],1'b1,X[`H_NF-2:0]})) | @@ -1452,14 +1452,14 @@ module readvectors ( case (Fmt) 2'b11: begin // quad X = TestVector[8+3*(`Q_LEN)-1:8+2*(`Q_LEN)]; - if(OpCtrl === `MUL_OPCTRL) Y = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)]; else Y = {2'b0, {`Q_NE-1{1'b1}}, `Q_NF'h0}; + if(OpCtrl === `MUL_OPCTRL) Y = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)]; else Y = {2'b0, {`Q_NE-1{1'b1}}, (`Q_NF)'(0)}; if(OpCtrl === `MUL_OPCTRL) Z = 0; else Z = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)]; Ans = TestVector[8+(`Q_LEN-1):8]; end 2'b01: begin // double X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+3*(`D_LEN)-1:8+2*(`D_LEN)]}; if(OpCtrl === `MUL_OPCTRL) Y = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]}; - else Y = {{`FLEN-`D_LEN{1'b1}}, 2'b0, {`D_NE-1{1'b1}}, `D_NF'h0}; + else Y = {{`FLEN-`D_LEN{1'b1}}, 2'b0, {`D_NE-1{1'b1}}, (`D_NF)'(0)}; if(OpCtrl === `MUL_OPCTRL) Z = {{`FLEN-`D_LEN{1'b1}}, {`D_LEN{1'b0}}}; else Z = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]}; Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; @@ -1467,7 +1467,7 @@ module readvectors ( 2'b00: begin // single X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+3*(`S_LEN)-1:8+2*(`S_LEN)]}; if(OpCtrl === `MUL_OPCTRL) Y = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+(`S_LEN)]}; - else Y = {{`FLEN-`S_LEN{1'b1}}, 2'b0, {`S_NE-1{1'b1}}, `S_NF'h0}; + else Y = {{`FLEN-`S_LEN{1'b1}}, 2'b0, {`S_NE-1{1'b1}}, (`S_NF)'(0)}; if(OpCtrl === `MUL_OPCTRL) Z = {{`FLEN-`S_LEN{1'b1}}, {`S_LEN{1'b0}}}; else Z = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+(`S_LEN)]}; Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; @@ -1475,7 +1475,7 @@ module readvectors ( 2'b10: begin // half X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+3*(`H_LEN)-1:8+2*(`H_LEN)]}; if(OpCtrl === `MUL_OPCTRL) Y = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+(`H_LEN)]}; - else Y = {{`FLEN-`H_LEN{1'b1}}, 2'b0, {`H_NE-1{1'b1}}, `H_NF'h0}; + else Y = {{`FLEN-`H_LEN{1'b1}}, 2'b0, {`H_NE-1{1'b1}}, (`H_NF)'(0)}; if(OpCtrl === `MUL_OPCTRL) Z = {{`FLEN-`H_LEN{1'b1}}, {`H_LEN{1'b0}}}; else Z = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+(`H_LEN)]}; Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]};