diff --git a/wally-pipelined/config/busybear/wally-config.vh b/wally-pipelined/config/busybear/wally-config.vh
index 794f6bbe..92e11aac 100644
--- a/wally-pipelined/config/busybear/wally-config.vh
+++ b/wally-pipelined/config/busybear/wally-config.vh
@@ -57,6 +57,9 @@
 // Address space
 `define RESET_VECTOR 64'h0000000000001000
 
+// Bus Interface
+`define AHBW 64
+
 // Test modes
 
 // Tie GPIO outputs back to inputs
diff --git a/wally-pipelined/regression/wally-busybear.do b/wally-pipelined/regression/wally-busybear.do
index 80d660af..f1ccea6a 100644
--- a/wally-pipelined/regression/wally-busybear.do
+++ b/wally-pipelined/regression/wally-busybear.do
@@ -131,6 +131,6 @@ add wave /testbench_busybear/InstrWName
 #set DefaultRadix hexadecimal
 #
 #-- Run the Simulation 
-run 621070
+run 621530
 #run -all
 ##quit
diff --git a/wally-pipelined/testbench/testbench-busybear.sv b/wally-pipelined/testbench/testbench-busybear.sv
index ebb4f1d7..d47a32bf 100644
--- a/wally-pipelined/testbench/testbench-busybear.sv
+++ b/wally-pipelined/testbench/testbench-busybear.sv
@@ -16,6 +16,23 @@ module testbench_busybear();
   logic        TimerIntM = 0, SwIntM = 0; // from CLINT
   logic        ExtIntM = 0; // not yet connected
 
+  logic [`AHBW-1:0] HRDATA;
+  logic             HREADY, HRESP;
+  logic [31:0]      HADDR;
+  logic [`AHBW-1:0] HWDATA;
+  logic             HWRITE;
+  logic [2:0]       HSIZE;
+  logic [2:0]       HBURST;
+  logic [3:0]       HPROT;
+  logic [1:0]       HTRANS;
+  logic             HMASTLOCK;
+
+  assign GPIOPinsIn = 0;
+  assign UARTSin = 1;
+  assign HREADY = 1;
+  assign HRESP = 0;
+  assign HRDATA = 0;
+
   // for now, seem to need these to be zero until we get a better idea
   assign InstrAccessFaultF = 0;
   assign DataAccessFaultM = 0;