From 8c6ddcc15bd8b2b3856408491276cacedb62113d Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 11 Jan 2023 15:15:08 -0800 Subject: [PATCH] changed name to CORE-V-WALLY --- pipelined/src/cache/cache.sv | 2 +- pipelined/src/cache/cacheLRU.sv | 2 +- pipelined/src/cache/cachefsm.sv | 2 +- pipelined/src/cache/cacheway.sv | 2 +- pipelined/src/cache/subcachelineread.sv | 2 +- pipelined/src/ebu/ahbcacheinterface.sv | 2 +- pipelined/src/ebu/ahbinterface.sv | 2 +- pipelined/src/ebu/amoalu.sv | 2 +- pipelined/src/ebu/buscachefsm.sv | 2 +- pipelined/src/ebu/busfsm.sv | 2 +- pipelined/src/ebu/controllerinputstage.sv | 2 +- pipelined/src/ebu/ebu.sv | 2 +- pipelined/src/fpu/fclassify.sv | 2 +- pipelined/src/fpu/fcmp.sv | 2 +- pipelined/src/fpu/fctrl.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrt.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv | 2 +- pipelined/src/fpu/fhazard.sv | 2 +- pipelined/src/fpu/fma/fma.sv | 2 +- pipelined/src/fpu/fma/fmaadd.sv | 2 +- pipelined/src/fpu/fma/fmaalign.sv | 2 +- pipelined/src/fpu/fma/fmaexpadd.sv | 2 +- pipelined/src/fpu/fma/fmalza.sv | 2 +- pipelined/src/fpu/fma/fmamult.sv | 2 +- pipelined/src/fpu/fma/fmasign.sv | 2 +- pipelined/src/fpu/fpu.sv | 2 +- pipelined/src/fpu/fregfile.sv | 2 +- pipelined/src/fpu/fsgninj.sv | 2 +- pipelined/src/fpu/postproc/cvtshiftcalc.sv | 2 +- pipelined/src/fpu/postproc/divshiftcalc.sv | 2 +- pipelined/src/fpu/postproc/flags.sv | 2 +- pipelined/src/fpu/postproc/fmashiftcalc.sv | 2 +- pipelined/src/fpu/postproc/negateintres.sv | 2 +- pipelined/src/fpu/postproc/normshift.sv | 2 +- pipelined/src/fpu/postproc/postprocess.sv | 2 +- pipelined/src/fpu/postproc/resultsign.sv | 2 +- pipelined/src/fpu/postproc/round.sv | 2 +- pipelined/src/fpu/postproc/roundsign.sv | 2 +- pipelined/src/fpu/postproc/shiftcorrection.sv | 2 +- pipelined/src/fpu/postproc/specialcase.sv | 2 +- pipelined/src/fpu/unpack.sv | 2 +- pipelined/src/fpu/unpackinput.sv | 2 +- pipelined/src/generic/adder.sv | 2 +- pipelined/src/generic/aplusbeq0.sv | 2 +- pipelined/src/generic/arrs.sv | 2 +- pipelined/src/generic/binencoder.sv | 2 +- pipelined/src/generic/clockgater.sv | 2 +- pipelined/src/generic/counter.sv | 2 +- pipelined/src/generic/csa.sv | 2 +- pipelined/src/generic/decoder.sv | 2 +- pipelined/src/generic/flop/flop.sv | 2 +- pipelined/src/generic/flop/flopen.sv | 2 +- pipelined/src/generic/flop/flopenl.sv | 2 +- pipelined/src/generic/flop/flopenr.sv | 2 +- pipelined/src/generic/flop/flopenrc.sv | 2 +- pipelined/src/generic/flop/flopens.sv | 2 +- pipelined/src/generic/flop/flopr.sv | 2 +- pipelined/src/generic/flop/floprc.sv | 2 +- pipelined/src/generic/flop/synchronizer.sv | 2 +- pipelined/src/generic/lzc.sv | 2 +- pipelined/src/generic/mem/ram1p1rwbe.sv | 2 +- pipelined/src/generic/mem/ram2p1r1wb.sv | 2 +- pipelined/src/generic/mem/ram2p1rwbefix.sv | 2 +- pipelined/src/generic/mem/rom1p1r.sv | 2 +- pipelined/src/generic/mux.sv | 2 +- pipelined/src/generic/neg.sv | 2 +- pipelined/src/generic/onehotdecoder.sv | 2 +- pipelined/src/generic/or_rows.sv | 2 +- pipelined/src/generic/priorityonehot.sv | 2 +- pipelined/src/generic/prioritythermometer.sv | 2 +- pipelined/src/hazard/hazard.sv | 2 +- pipelined/src/ieu/alu.sv | 2 +- pipelined/src/ieu/comparator.sv | 2 +- pipelined/src/ieu/controller.sv | 2 +- pipelined/src/ieu/datapath.sv | 2 +- pipelined/src/ieu/extend.sv | 2 +- pipelined/src/ieu/forward.sv | 2 +- pipelined/src/ieu/ieu.sv | 2 +- pipelined/src/ieu/regfile.sv | 2 +- pipelined/src/ieu/shifter.sv | 2 +- pipelined/src/ifu/BTBPredictor.sv | 2 +- pipelined/src/ifu/RAsPredictor.sv | 2 +- pipelined/src/ifu/bpred.sv | 2 +- pipelined/src/ifu/decompress.sv | 2 +- pipelined/src/ifu/foldedgshare.sv | 2 +- pipelined/src/ifu/globalHistoryPredictor.sv | 2 +- pipelined/src/ifu/globalhistory.sv | 2 +- pipelined/src/ifu/gshare.sv | 2 +- pipelined/src/ifu/ifu.sv | 2 +- pipelined/src/ifu/irom.sv | 2 +- pipelined/src/ifu/localHistoryPredictor.sv | 2 +- pipelined/src/ifu/oldgsharepredictor.sv | 2 +- pipelined/src/ifu/oldgsharepredictor2.sv | 2 +- pipelined/src/ifu/satCounter2.sv | 2 +- pipelined/src/ifu/speculativeglobalhistory.sv | 2 +- pipelined/src/ifu/speculativegshare.sv | 2 +- pipelined/src/ifu/spillsupport.sv | 2 +- pipelined/src/ifu/twoBitPredictor.sv | 2 +- pipelined/src/lsu/atomic.sv | 2 +- pipelined/src/lsu/dtim.sv | 2 +- pipelined/src/lsu/endianswap.sv | 2 +- pipelined/src/lsu/lrsc.sv | 2 +- pipelined/src/lsu/lsu.sv | 2 +- pipelined/src/lsu/subwordread.sv | 2 +- pipelined/src/lsu/subwordwrite.sv | 2 +- pipelined/src/lsu/swbytemask.sv | 2 +- pipelined/src/mdu/intdivrestoring.sv | 2 +- pipelined/src/mdu/intdivrestoringstep.sv | 2 +- pipelined/src/mdu/mdu.sv | 2 +- pipelined/src/mdu/mul.sv | 2 +- pipelined/src/mmu/adrdec.sv | 2 +- pipelined/src/mmu/adrdecs.sv | 2 +- pipelined/src/mmu/hptw.sv | 2 +- pipelined/src/mmu/mmu.sv | 2 +- pipelined/src/mmu/pmachecker.sv | 2 +- pipelined/src/mmu/pmpadrdec.sv | 2 +- pipelined/src/mmu/pmpchecker.sv | 2 +- pipelined/src/mmu/tlb.sv | 2 +- pipelined/src/mmu/tlbcam.sv | 2 +- pipelined/src/mmu/tlbcamline.sv | 2 +- pipelined/src/mmu/tlbcontrol.sv | 2 +- pipelined/src/mmu/tlblru.sv | 2 +- pipelined/src/mmu/tlbmixer.sv | 2 +- pipelined/src/mmu/tlbram.sv | 2 +- pipelined/src/mmu/tlbramline.sv | 2 +- pipelined/src/mmu/vm64check.sv | 2 +- pipelined/src/privileged/csr.sv | 2 +- pipelined/src/privileged/csrc.sv | 2 +- pipelined/src/privileged/csri.sv | 2 +- pipelined/src/privileged/csrm.sv | 2 +- pipelined/src/privileged/csrs.sv | 2 +- pipelined/src/privileged/csrsr.sv | 2 +- pipelined/src/privileged/csru.sv | 2 +- pipelined/src/privileged/privdec.sv | 2 +- pipelined/src/privileged/privileged.sv | 2 +- pipelined/src/privileged/privmode.sv | 2 +- pipelined/src/privileged/privpiperegs.sv | 2 +- pipelined/src/privileged/trap.sv | 2 +- pipelined/src/uncore/ahbapbbridge.sv | 2 +- pipelined/src/uncore/clint_apb.sv | 2 +- pipelined/src/uncore/gpio_apb.sv | 2 +- pipelined/src/uncore/plic_apb.sv | 2 +- pipelined/src/uncore/ram_ahb.sv | 2 +- pipelined/src/uncore/rom_ahb.sv | 2 +- pipelined/src/uncore/sdc/SDC.sv | 2 +- pipelined/src/uncore/sdc/SDCcounter.sv | 2 +- pipelined/src/uncore/sdc/clkdivider.sv | 2 +- pipelined/src/uncore/sdc/crc16_sipo_np_ce.sv | 2 +- pipelined/src/uncore/sdc/crc7_pipo.sv | 2 +- pipelined/src/uncore/sdc/crc7_sipo_np_ce.sv | 2 +- pipelined/src/uncore/sdc/piso_generic_ce.sv | 2 +- pipelined/src/uncore/sdc/regfile_p2r1w1_nibo.sv | 2 +- pipelined/src/uncore/sdc/regfile_p2r1w1bwen.sv | 2 +- pipelined/src/uncore/sdc/sd_clk_fsm.sv | 2 +- pipelined/src/uncore/sdc/sd_cmd_fsm.sv | 2 +- pipelined/src/uncore/sdc/sd_dat_fsm.sv | 2 +- pipelined/src/uncore/sdc/sd_top.sv | 2 +- pipelined/src/uncore/sdc/simple_timer.sv | 2 +- pipelined/src/uncore/sdc/sipo_generic_ce.sv | 2 +- pipelined/src/uncore/sdc/up_down_counter.sv | 2 +- pipelined/src/uncore/uartPC16550D.sv | 2 +- pipelined/src/uncore/uart_apb.sv | 2 +- pipelined/src/uncore/uncore.sv | 2 +- pipelined/src/wally/wallypipelinedcore.sv | 2 +- pipelined/src/wally/wallypipelinedsoc.sv | 2 +- pipelined/src/wally/wallypipelinedsocwrapper.v | 2 +- 179 files changed, 179 insertions(+), 179 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index 23a90db2..62fc3a1d 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -6,7 +6,7 @@ // // Purpose: Storage for data and meta data. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/cache/cacheLRU.sv b/pipelined/src/cache/cacheLRU.sv index 36005e4e..3cabf059 100644 --- a/pipelined/src/cache/cacheLRU.sv +++ b/pipelined/src/cache/cacheLRU.sv @@ -6,7 +6,7 @@ // Tested for Powers of 2. // // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index 657f1f97..4abbe59a 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -6,7 +6,7 @@ // // Purpose: Controller for the dcache fsm // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv index 4d25b8d3..10bb4cfa 100644 --- a/pipelined/src/cache/cacheway.sv +++ b/pipelined/src/cache/cacheway.sv @@ -6,7 +6,7 @@ // // Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/cache/subcachelineread.sv b/pipelined/src/cache/subcachelineread.sv index 6a317e13..0219e259 100644 --- a/pipelined/src/cache/subcachelineread.sv +++ b/pipelined/src/cache/subcachelineread.sv @@ -6,7 +6,7 @@ // // Purpose: Controller for the dcache fsm // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ebu/ahbcacheinterface.sv b/pipelined/src/ebu/ahbcacheinterface.sv index 6263f497..e3d84547 100644 --- a/pipelined/src/ebu/ahbcacheinterface.sv +++ b/pipelined/src/ebu/ahbcacheinterface.sv @@ -10,7 +10,7 @@ // This register should be necessary for timing. There is no register in the uncore or // ahblite controller between the memories and this cache. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ebu/ahbinterface.sv b/pipelined/src/ebu/ahbinterface.sv index 98134afe..0ebcd3b3 100644 --- a/pipelined/src/ebu/ahbinterface.sv +++ b/pipelined/src/ebu/ahbinterface.sv @@ -10,7 +10,7 @@ // This register should be necessary for timing. There is no register in the uncore or // ahblite controller between the memories and this cache. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ebu/amoalu.sv b/pipelined/src/ebu/amoalu.sv index 5e1dd850..7bdbbc86 100644 --- a/pipelined/src/ebu/amoalu.sv +++ b/pipelined/src/ebu/amoalu.sv @@ -6,7 +6,7 @@ // // Purpose: Performs AMO operations // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ebu/buscachefsm.sv b/pipelined/src/ebu/buscachefsm.sv index 38b0b8ff..ed7d3459 100644 --- a/pipelined/src/ebu/buscachefsm.sv +++ b/pipelined/src/ebu/buscachefsm.sv @@ -6,7 +6,7 @@ // // Purpose: Load/Store Unit's interface to BUS for cacheless system // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ebu/busfsm.sv b/pipelined/src/ebu/busfsm.sv index 41be2d2d..f01678c7 100644 --- a/pipelined/src/ebu/busfsm.sv +++ b/pipelined/src/ebu/busfsm.sv @@ -6,7 +6,7 @@ // // Purpose: Load/Store Unit's interface to BUS for cacheless system // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ebu/controllerinputstage.sv b/pipelined/src/ebu/controllerinputstage.sv index d84add27..3bbda0ea 100644 --- a/pipelined/src/ebu/controllerinputstage.sv +++ b/pipelined/src/ebu/controllerinputstage.sv @@ -12,7 +12,7 @@ // Bus width presently matches XLEN // Anticipate replacing this with an AXI bus interface to communicate with FPGA DRAM/Flash controllers // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ebu/ebu.sv b/pipelined/src/ebu/ebu.sv index 333da0dd..3e44ff93 100644 --- a/pipelined/src/ebu/ebu.sv +++ b/pipelined/src/ebu/ebu.sv @@ -12,7 +12,7 @@ // Bus width presently matches XLEN // Anticipate replacing this with an AXI bus interface to communicate with FPGA DRAM/Flash controllers // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fclassify.sv b/pipelined/src/fpu/fclassify.sv index c2dfa988..e91f34d1 100644 --- a/pipelined/src/fpu/fclassify.sv +++ b/pipelined/src/fpu/fclassify.sv @@ -6,7 +6,7 @@ // // Purpose: Floating-point classify unit // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fcmp.sv b/pipelined/src/fpu/fcmp.sv index 09881ff0..5cea973d 100755 --- a/pipelined/src/fpu/fcmp.sv +++ b/pipelined/src/fpu/fcmp.sv @@ -7,7 +7,7 @@ // // Purpose: Floating-point comparison unit // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fctrl.sv b/pipelined/src/fpu/fctrl.sv index 1363d18e..4d156666 100755 --- a/pipelined/src/fpu/fctrl.sv +++ b/pipelined/src/fpu/fctrl.sv @@ -6,7 +6,7 @@ // // Purpose: floating-point control unit // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv index a47031a7..2fecf769 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv @@ -6,7 +6,7 @@ // // Purpose: Combined Divide and Square Root Floating Point and Integer Unit // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv index e5f58b6b..8d881d20 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv @@ -6,7 +6,7 @@ // // Purpose: Combined Divide and Square Root Floating Point and Integer Unit // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv index c4cd3918..ae642890 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv @@ -6,7 +6,7 @@ // // Purpose: Radix 2 F Addend Generator // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv index 863a7603..4572ba94 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv @@ -6,7 +6,7 @@ // // Purpose: Radix 4 F Addend Generator // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv index 4649e9a5..476a7c90 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv @@ -6,7 +6,7 @@ // // Purpose: Combined Divide and Square Root Floating Point and Integer Unit // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv index a2175451..9a50679a 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv @@ -6,7 +6,7 @@ // // Purpose: Combined Divide and Square Root Floating Point and Integer Unit // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv index 4a1d7d13..94b7c043 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv @@ -6,7 +6,7 @@ // // Purpose: Combined Divide and Square Root Floating Point and Integer Unit // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv index 2fa3fb98..83d3c09d 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv @@ -6,7 +6,7 @@ // // Purpose: Combined Divide and Square Root Floating Point and Integer Unit // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv index fce04715..316e885b 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv @@ -6,7 +6,7 @@ // // Purpose: Radix 2 Quotient Digit Selection // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv index ef725d97..ee5e63a2 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv @@ -6,7 +6,7 @@ // // Purpose: Radix 4 Quotient Digit Selection // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv index 4751db29..104884fc 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv @@ -6,7 +6,7 @@ // // Purpose: Comparator-based Radix 4 Quotient Digit Selection // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv index c4e341d0..48d34972 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv @@ -6,7 +6,7 @@ // // Purpose: Combined Divide and Square Root Floating Point and Integer Unit stage // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv index a7f3f214..93e809ae 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv @@ -6,7 +6,7 @@ // // Purpose: Combined Divide and Square Root Floating Point and Integer Unit stage // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv index 04b36c44..46289cd2 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv @@ -6,7 +6,7 @@ // // Purpose: Radix 2 unified on-the-fly converter // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv index 01b30eb0..5c2168c2 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv @@ -6,7 +6,7 @@ // // Purpose: Radix 4 unified on-the-fly converter // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fhazard.sv b/pipelined/src/fpu/fhazard.sv index 281f7460..03678ace 100644 --- a/pipelined/src/fpu/fhazard.sv +++ b/pipelined/src/fpu/fhazard.sv @@ -6,7 +6,7 @@ // // Purpose: Determine forwarding, stalls and flushes for the FPU // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fma/fma.sv b/pipelined/src/fpu/fma/fma.sv index 71150255..23e6710f 100644 --- a/pipelined/src/fpu/fma/fma.sv +++ b/pipelined/src/fpu/fma/fma.sv @@ -6,7 +6,7 @@ // // Purpose: Floating point multiply-accumulate of configurable size // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fma/fmaadd.sv b/pipelined/src/fpu/fma/fmaadd.sv index cd899ebd..7f1487f2 100644 --- a/pipelined/src/fpu/fma/fmaadd.sv +++ b/pipelined/src/fpu/fma/fmaadd.sv @@ -6,7 +6,7 @@ // // Purpose: FMA significand adder // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fma/fmaalign.sv b/pipelined/src/fpu/fma/fmaalign.sv index a043df7d..df5080a7 100644 --- a/pipelined/src/fpu/fma/fmaalign.sv +++ b/pipelined/src/fpu/fma/fmaalign.sv @@ -7,7 +7,7 @@ // // Purpose: FMA alginment shift // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fma/fmaexpadd.sv b/pipelined/src/fpu/fma/fmaexpadd.sv index dfb31dc4..4521d475 100644 --- a/pipelined/src/fpu/fma/fmaexpadd.sv +++ b/pipelined/src/fpu/fma/fmaexpadd.sv @@ -6,7 +6,7 @@ // // Purpose: FMA exponent addition // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fma/fmalza.sv b/pipelined/src/fpu/fma/fmalza.sv index b9065f05..5571b2ab 100644 --- a/pipelined/src/fpu/fma/fmalza.sv +++ b/pipelined/src/fpu/fma/fmalza.sv @@ -6,7 +6,7 @@ // // Purpose: Leading Zero Anticipator // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fma/fmamult.sv b/pipelined/src/fpu/fma/fmamult.sv index 5f30c166..911f6645 100644 --- a/pipelined/src/fpu/fma/fmamult.sv +++ b/pipelined/src/fpu/fma/fmamult.sv @@ -6,7 +6,7 @@ // // Purpose: FMA Significand Multiplier // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fma/fmasign.sv b/pipelined/src/fpu/fma/fmasign.sv index 2664d6c5..b9c61ae2 100644 --- a/pipelined/src/fpu/fma/fmasign.sv +++ b/pipelined/src/fpu/fma/fmasign.sv @@ -6,7 +6,7 @@ // // Purpose: FMA Sign Logic // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index d9c82e9b..567b2e0b 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -6,7 +6,7 @@ // // Purpose: Floating Point Unit Top-Level Interface // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fregfile.sv b/pipelined/src/fpu/fregfile.sv index 393d25b1..4d774bcc 100644 --- a/pipelined/src/fpu/fregfile.sv +++ b/pipelined/src/fpu/fregfile.sv @@ -6,7 +6,7 @@ // // Purpose: 3R1W 4-port register file for FPU // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/fsgninj.sv b/pipelined/src/fpu/fsgninj.sv index 4c2f1446..4dc07a97 100755 --- a/pipelined/src/fpu/fsgninj.sv +++ b/pipelined/src/fpu/fsgninj.sv @@ -6,7 +6,7 @@ // // Purpose: FPU Sign Injection instructions // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/cvtshiftcalc.sv b/pipelined/src/fpu/postproc/cvtshiftcalc.sv index 8b6dc026..7069cb53 100644 --- a/pipelined/src/fpu/postproc/cvtshiftcalc.sv +++ b/pipelined/src/fpu/postproc/cvtshiftcalc.sv @@ -6,7 +6,7 @@ // // Purpose: Conversion shift calculation // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/divshiftcalc.sv b/pipelined/src/fpu/postproc/divshiftcalc.sv index e2601211..b98f749f 100644 --- a/pipelined/src/fpu/postproc/divshiftcalc.sv +++ b/pipelined/src/fpu/postproc/divshiftcalc.sv @@ -6,7 +6,7 @@ // // Purpose: Division shift calculation // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/flags.sv b/pipelined/src/fpu/postproc/flags.sv index d8cd47b7..587c1ce5 100644 --- a/pipelined/src/fpu/postproc/flags.sv +++ b/pipelined/src/fpu/postproc/flags.sv @@ -6,7 +6,7 @@ // // Purpose: Post-Processing flag calculation // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/fmashiftcalc.sv b/pipelined/src/fpu/postproc/fmashiftcalc.sv index 3335b40f..dd1fb11b 100644 --- a/pipelined/src/fpu/postproc/fmashiftcalc.sv +++ b/pipelined/src/fpu/postproc/fmashiftcalc.sv @@ -6,7 +6,7 @@ // // Purpose: FMA shift calculation // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/negateintres.sv b/pipelined/src/fpu/postproc/negateintres.sv index 133ed977..cbca322a 100644 --- a/pipelined/src/fpu/postproc/negateintres.sv +++ b/pipelined/src/fpu/postproc/negateintres.sv @@ -6,7 +6,7 @@ // // Purpose: Negate integer result // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/normshift.sv b/pipelined/src/fpu/postproc/normshift.sv index 95024c77..541c703b 100644 --- a/pipelined/src/fpu/postproc/normshift.sv +++ b/pipelined/src/fpu/postproc/normshift.sv @@ -6,7 +6,7 @@ // // Purpose: normalization shifter // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/postprocess.sv b/pipelined/src/fpu/postproc/postprocess.sv index c4dcf9f3..1e8b9aec 100644 --- a/pipelined/src/fpu/postproc/postprocess.sv +++ b/pipelined/src/fpu/postproc/postprocess.sv @@ -6,7 +6,7 @@ // // Purpose: Post-Processing // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/resultsign.sv b/pipelined/src/fpu/postproc/resultsign.sv index 484d2132..d260e549 100644 --- a/pipelined/src/fpu/postproc/resultsign.sv +++ b/pipelined/src/fpu/postproc/resultsign.sv @@ -6,7 +6,7 @@ // // Purpose: calculating the result's sign // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/round.sv b/pipelined/src/fpu/postproc/round.sv index b14d39be..04cd1767 100644 --- a/pipelined/src/fpu/postproc/round.sv +++ b/pipelined/src/fpu/postproc/round.sv @@ -6,7 +6,7 @@ // // Purpose: Rounder // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/roundsign.sv b/pipelined/src/fpu/postproc/roundsign.sv index 0d376e7d..9bc7c108 100644 --- a/pipelined/src/fpu/postproc/roundsign.sv +++ b/pipelined/src/fpu/postproc/roundsign.sv @@ -6,7 +6,7 @@ // // Purpose: Sign calculation ofr rounding // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/shiftcorrection.sv b/pipelined/src/fpu/postproc/shiftcorrection.sv index 0f1e6bd1..673f7cd9 100644 --- a/pipelined/src/fpu/postproc/shiftcorrection.sv +++ b/pipelined/src/fpu/postproc/shiftcorrection.sv @@ -6,7 +6,7 @@ // // Purpose: shift correction // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/postproc/specialcase.sv b/pipelined/src/fpu/postproc/specialcase.sv index 6e9e2156..32f8692c 100644 --- a/pipelined/src/fpu/postproc/specialcase.sv +++ b/pipelined/src/fpu/postproc/specialcase.sv @@ -6,7 +6,7 @@ // // Purpose: special case selection // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/unpack.sv b/pipelined/src/fpu/unpack.sv index 20fb8ed2..be914fcf 100644 --- a/pipelined/src/fpu/unpack.sv +++ b/pipelined/src/fpu/unpack.sv @@ -6,7 +6,7 @@ // // Purpose: unpack X, Y, Z floating-point inputs // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/fpu/unpackinput.sv b/pipelined/src/fpu/unpackinput.sv index 14a41475..f92c2be4 100644 --- a/pipelined/src/fpu/unpackinput.sv +++ b/pipelined/src/fpu/unpackinput.sv @@ -6,7 +6,7 @@ // // Purpose: unpack input: extract sign, exponent, significand, characteristics // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/adder.sv b/pipelined/src/generic/adder.sv index b5439a42..b9b2b2af 100644 --- a/pipelined/src/generic/adder.sv +++ b/pipelined/src/generic/adder.sv @@ -6,7 +6,7 @@ // // Purpose: Adder // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/aplusbeq0.sv b/pipelined/src/generic/aplusbeq0.sv index 8dea1143..4b3c4439 100644 --- a/pipelined/src/generic/aplusbeq0.sv +++ b/pipelined/src/generic/aplusbeq0.sv @@ -6,7 +6,7 @@ // // Purpose: Determine if A+B = 0. Used in FP divider. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/arrs.sv b/pipelined/src/generic/arrs.sv index 3930314b..8256d9d3 100644 --- a/pipelined/src/generic/arrs.sv +++ b/pipelined/src/generic/arrs.sv @@ -9,7 +9,7 @@ // arrs takes in the asynchronous reset and outputs an asynchronous // rising edge, but then syncs the falling edge to the posedge clk. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/binencoder.sv b/pipelined/src/generic/binencoder.sv index f62d2aee..a7e8061f 100644 --- a/pipelined/src/generic/binencoder.sv +++ b/pipelined/src/generic/binencoder.sv @@ -5,7 +5,7 @@ // // Purpose: one-hot to binary encoding. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/clockgater.sv b/pipelined/src/generic/clockgater.sv index b3c2c689..486ea456 100644 --- a/pipelined/src/generic/clockgater.sv +++ b/pipelined/src/generic/clockgater.sv @@ -6,7 +6,7 @@ // // Purpose: Clock gater model. Must use standard cell for synthesis. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/counter.sv b/pipelined/src/generic/counter.sv index 18e27884..06df8be6 100644 --- a/pipelined/src/generic/counter.sv +++ b/pipelined/src/generic/counter.sv @@ -6,7 +6,7 @@ // // Purpose: Counter with reset and enable // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/csa.sv b/pipelined/src/generic/csa.sv index cffef432..ecb0f376 100644 --- a/pipelined/src/generic/csa.sv +++ b/pipelined/src/generic/csa.sv @@ -6,7 +6,7 @@ // // Purpose: 3:2 carry-save adder // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/decoder.sv b/pipelined/src/generic/decoder.sv index de1df16d..bfc9d3b5 100644 --- a/pipelined/src/generic/decoder.sv +++ b/pipelined/src/generic/decoder.sv @@ -6,7 +6,7 @@ // // Purpose: Binary encoding to one-hot decoder // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/flop/flop.sv b/pipelined/src/generic/flop/flop.sv index 979c81b1..14b09899 100644 --- a/pipelined/src/generic/flop/flop.sv +++ b/pipelined/src/generic/flop/flop.sv @@ -6,7 +6,7 @@ // // Purpose: various flavors of flip-flops // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/flop/flopen.sv b/pipelined/src/generic/flop/flopen.sv index 8f447b91..5987222d 100644 --- a/pipelined/src/generic/flop/flopen.sv +++ b/pipelined/src/generic/flop/flopen.sv @@ -6,7 +6,7 @@ // // Purpose: various flavors of flip-flops // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/flop/flopenl.sv b/pipelined/src/generic/flop/flopenl.sv index db79567a..b01c5b5b 100644 --- a/pipelined/src/generic/flop/flopenl.sv +++ b/pipelined/src/generic/flop/flopenl.sv @@ -6,7 +6,7 @@ // // Purpose: various flavors of flip-flops // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/flop/flopenr.sv b/pipelined/src/generic/flop/flopenr.sv index bd733aec..74cea0cd 100644 --- a/pipelined/src/generic/flop/flopenr.sv +++ b/pipelined/src/generic/flop/flopenr.sv @@ -6,7 +6,7 @@ // // Purpose: various flavors of flip-flops // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/flop/flopenrc.sv b/pipelined/src/generic/flop/flopenrc.sv index 197c5591..85fb09bd 100644 --- a/pipelined/src/generic/flop/flopenrc.sv +++ b/pipelined/src/generic/flop/flopenrc.sv @@ -6,7 +6,7 @@ // // Purpose: various flavors of flip-flops // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/flop/flopens.sv b/pipelined/src/generic/flop/flopens.sv index 872d3490..257d2808 100644 --- a/pipelined/src/generic/flop/flopens.sv +++ b/pipelined/src/generic/flop/flopens.sv @@ -6,7 +6,7 @@ // // Purpose: various flavors of flip-flops // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/flop/flopr.sv b/pipelined/src/generic/flop/flopr.sv index 1fe42277..d3296d92 100644 --- a/pipelined/src/generic/flop/flopr.sv +++ b/pipelined/src/generic/flop/flopr.sv @@ -6,7 +6,7 @@ // // Purpose: various flavors of flip-flops // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/flop/floprc.sv b/pipelined/src/generic/flop/floprc.sv index 6d084d6c..995cff60 100644 --- a/pipelined/src/generic/flop/floprc.sv +++ b/pipelined/src/generic/flop/floprc.sv @@ -6,7 +6,7 @@ // // Purpose: various flavors of flip-flops // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/flop/synchronizer.sv b/pipelined/src/generic/flop/synchronizer.sv index 6e208e95..d5594c99 100644 --- a/pipelined/src/generic/flop/synchronizer.sv +++ b/pipelined/src/generic/flop/synchronizer.sv @@ -6,7 +6,7 @@ // // Purpose: Two-stage flip-flop synchronizer // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/lzc.sv b/pipelined/src/generic/lzc.sv index 5a58cf42..54372f8d 100644 --- a/pipelined/src/generic/lzc.sv +++ b/pipelined/src/generic/lzc.sv @@ -5,7 +5,7 @@ // // Purpose: Leading Zero Counter // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/mem/ram1p1rwbe.sv b/pipelined/src/generic/mem/ram1p1rwbe.sv index 374a9a0b..6e24c417 100644 --- a/pipelined/src/generic/mem/ram1p1rwbe.sv +++ b/pipelined/src/generic/mem/ram1p1rwbe.sv @@ -9,7 +9,7 @@ // // Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/mem/ram2p1r1wb.sv b/pipelined/src/generic/mem/ram2p1r1wb.sv index ee66e333..db5718a8 100644 --- a/pipelined/src/generic/mem/ram2p1r1wb.sv +++ b/pipelined/src/generic/mem/ram2p1r1wb.sv @@ -16,7 +16,7 @@ // example // mem load -infile twoBitPredictor.txt -format bin testbench/dut/core/ifu/bpred/DirPredictor/memory/memory // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/mem/ram2p1rwbefix.sv b/pipelined/src/generic/mem/ram2p1rwbefix.sv index cc23b252..9dc3ed47 100644 --- a/pipelined/src/generic/mem/ram2p1rwbefix.sv +++ b/pipelined/src/generic/mem/ram2p1rwbefix.sv @@ -9,7 +9,7 @@ // // Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/mem/rom1p1r.sv b/pipelined/src/generic/mem/rom1p1r.sv index 6f6533a6..90bb87f9 100644 --- a/pipelined/src/generic/mem/rom1p1r.sv +++ b/pipelined/src/generic/mem/rom1p1r.sv @@ -5,7 +5,7 @@ // // Purpose: Single-ported ROM // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/mux.sv b/pipelined/src/generic/mux.sv index d4f92667..c3f0e5f9 100644 --- a/pipelined/src/generic/mux.sv +++ b/pipelined/src/generic/mux.sv @@ -6,7 +6,7 @@ // // Purpose: Various flavors of multiplexers // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/neg.sv b/pipelined/src/generic/neg.sv index f7947ce6..66be9e07 100644 --- a/pipelined/src/generic/neg.sv +++ b/pipelined/src/generic/neg.sv @@ -6,7 +6,7 @@ // // Purpose: 2's complement negator // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/onehotdecoder.sv b/pipelined/src/generic/onehotdecoder.sv index f1051969..3c45a762 100644 --- a/pipelined/src/generic/onehotdecoder.sv +++ b/pipelined/src/generic/onehotdecoder.sv @@ -6,7 +6,7 @@ // // Purpose: Bin to one hot decoder. Power of 2 only. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/or_rows.sv b/pipelined/src/generic/or_rows.sv index 7f892f76..f281cde5 100644 --- a/pipelined/src/generic/or_rows.sv +++ b/pipelined/src/generic/or_rows.sv @@ -6,7 +6,7 @@ // // Purpose: Various flavors of multiplexers // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/priorityonehot.sv b/pipelined/src/generic/priorityonehot.sv index 1aa28c88..51c155c1 100644 --- a/pipelined/src/generic/priorityonehot.sv +++ b/pipelined/src/generic/priorityonehot.sv @@ -16,7 +16,7 @@ // in 01011101010100000 // out 00000000000100000 // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/generic/prioritythermometer.sv b/pipelined/src/generic/prioritythermometer.sv index 0e2ba7dc..3054298a 100644 --- a/pipelined/src/generic/prioritythermometer.sv +++ b/pipelined/src/generic/prioritythermometer.sv @@ -12,7 +12,7 @@ // in 01011101010100000 // out 00000000000011111 // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/hazard/hazard.sv b/pipelined/src/hazard/hazard.sv index d99cf394..7d4aa9d2 100644 --- a/pipelined/src/hazard/hazard.sv +++ b/pipelined/src/hazard/hazard.sv @@ -6,7 +6,7 @@ // // Purpose: Determine forwarding, stalls and flushes // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ieu/alu.sv b/pipelined/src/ieu/alu.sv index 041712a7..430af3d8 100644 --- a/pipelined/src/ieu/alu.sv +++ b/pipelined/src/ieu/alu.sv @@ -6,7 +6,7 @@ // // Purpose: RISC-V Arithmetic/Logic Unit // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ieu/comparator.sv b/pipelined/src/ieu/comparator.sv index 579f2c9c..27226a6a 100644 --- a/pipelined/src/ieu/comparator.sv +++ b/pipelined/src/ieu/comparator.sv @@ -6,7 +6,7 @@ // // Purpose: Branch comparison // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ieu/controller.sv b/pipelined/src/ieu/controller.sv index d6a204b0..abc86da6 100644 --- a/pipelined/src/ieu/controller.sv +++ b/pipelined/src/ieu/controller.sv @@ -6,7 +6,7 @@ // // Purpose: Top level controller module // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ieu/datapath.sv b/pipelined/src/ieu/datapath.sv index 159d07f6..0e3e2e81 100644 --- a/pipelined/src/ieu/datapath.sv +++ b/pipelined/src/ieu/datapath.sv @@ -6,7 +6,7 @@ // // Purpose: Wally Integer Datapath // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ieu/extend.sv b/pipelined/src/ieu/extend.sv index feb7f9fb..74b6acdf 100644 --- a/pipelined/src/ieu/extend.sv +++ b/pipelined/src/ieu/extend.sv @@ -6,7 +6,7 @@ // // Purpose: // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ieu/forward.sv b/pipelined/src/ieu/forward.sv index 11fb4418..c76b2355 100644 --- a/pipelined/src/ieu/forward.sv +++ b/pipelined/src/ieu/forward.sv @@ -6,7 +6,7 @@ // // Purpose: Determine datapath forwarding // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ieu/ieu.sv b/pipelined/src/ieu/ieu.sv index 9f4a773d..9d6d81d4 100644 --- a/pipelined/src/ieu/ieu.sv +++ b/pipelined/src/ieu/ieu.sv @@ -6,7 +6,7 @@ // // Purpose: Integer Execution Unit: datapath and controller // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ieu/regfile.sv b/pipelined/src/ieu/regfile.sv index 8ac09a91..1680d5bc 100644 --- a/pipelined/src/ieu/regfile.sv +++ b/pipelined/src/ieu/regfile.sv @@ -6,7 +6,7 @@ // // Purpose: 3-port register file // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ieu/shifter.sv b/pipelined/src/ieu/shifter.sv index 21573c6c..015cc780 100644 --- a/pipelined/src/ieu/shifter.sv +++ b/pipelined/src/ieu/shifter.sv @@ -6,7 +6,7 @@ // // Purpose: RISC-V 32/64 bit shifter // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/BTBPredictor.sv b/pipelined/src/ifu/BTBPredictor.sv index 592d0f6f..d15dae6c 100644 --- a/pipelined/src/ifu/BTBPredictor.sv +++ b/pipelined/src/ifu/BTBPredictor.sv @@ -9,7 +9,7 @@ // Purpose: BTB model. Outputs type of instruction (currently 1 hot encoded. Probably want // to encode to reduce storage), valid, target PC. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/RAsPredictor.sv b/pipelined/src/ifu/RAsPredictor.sv index b7fbbc5a..2fb98417 100644 --- a/pipelined/src/ifu/RAsPredictor.sv +++ b/pipelined/src/ifu/RAsPredictor.sv @@ -8,7 +8,7 @@ // // Purpose: 2 bit saturating counter predictor with parameterized table depth. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/bpred.sv b/pipelined/src/ifu/bpred.sv index deae5cec..246a5242 100644 --- a/pipelined/src/ifu/bpred.sv +++ b/pipelined/src/ifu/bpred.sv @@ -9,7 +9,7 @@ // Purpose: Branch prediction unit // Produces a branch prediction based on branch history. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/decompress.sv b/pipelined/src/ifu/decompress.sv index 044095f8..aec215f6 100644 --- a/pipelined/src/ifu/decompress.sv +++ b/pipelined/src/ifu/decompress.sv @@ -6,7 +6,7 @@ // // Purpose: Expand 16-bit compressed instructions to 32 bits // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/foldedgshare.sv b/pipelined/src/ifu/foldedgshare.sv index 2665f318..38e0fe61 100644 --- a/pipelined/src/ifu/foldedgshare.sv +++ b/pipelined/src/ifu/foldedgshare.sv @@ -8,7 +8,7 @@ // // Purpose: Global History Branch predictor with parameterized global history register // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/globalHistoryPredictor.sv b/pipelined/src/ifu/globalHistoryPredictor.sv index cf97039c..92a3f9a1 100644 --- a/pipelined/src/ifu/globalHistoryPredictor.sv +++ b/pipelined/src/ifu/globalHistoryPredictor.sv @@ -8,7 +8,7 @@ // // Purpose: Global History Branch predictor with parameterized global history register // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/globalhistory.sv b/pipelined/src/ifu/globalhistory.sv index d4f234ac..86c48f6b 100644 --- a/pipelined/src/ifu/globalhistory.sv +++ b/pipelined/src/ifu/globalhistory.sv @@ -8,7 +8,7 @@ // // Purpose: Global History Branch predictor with parameterized global history register // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/gshare.sv b/pipelined/src/ifu/gshare.sv index 2fbac5c5..ca801a27 100644 --- a/pipelined/src/ifu/gshare.sv +++ b/pipelined/src/ifu/gshare.sv @@ -8,7 +8,7 @@ // // Purpose: Global History Branch predictor with parameterized global history register // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index d88ccdf5..464e0f1c 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -7,7 +7,7 @@ // Purpose: Instrunction Fetch Unit // PC, branch prediction, instruction cache // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/irom.sv b/pipelined/src/ifu/irom.sv index ef928431..3e7e4633 100644 --- a/pipelined/src/ifu/irom.sv +++ b/pipelined/src/ifu/irom.sv @@ -5,7 +5,7 @@ // Modified: // // Purpose: simple instruction ROM -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/localHistoryPredictor.sv b/pipelined/src/ifu/localHistoryPredictor.sv index 7e61d8c3..1709772d 100644 --- a/pipelined/src/ifu/localHistoryPredictor.sv +++ b/pipelined/src/ifu/localHistoryPredictor.sv @@ -8,7 +8,7 @@ // // Purpose: Global History Branch predictor with parameterized global history register // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/oldgsharepredictor.sv b/pipelined/src/ifu/oldgsharepredictor.sv index 627d2c33..29a62251 100644 --- a/pipelined/src/ifu/oldgsharepredictor.sv +++ b/pipelined/src/ifu/oldgsharepredictor.sv @@ -8,7 +8,7 @@ // // Purpose: Gshare predictor with parameterized global history register // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/oldgsharepredictor2.sv b/pipelined/src/ifu/oldgsharepredictor2.sv index 047e9e6b..679358e3 100644 --- a/pipelined/src/ifu/oldgsharepredictor2.sv +++ b/pipelined/src/ifu/oldgsharepredictor2.sv @@ -8,7 +8,7 @@ // // Purpose: Gshare predictor with parameterized global history register // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/satCounter2.sv b/pipelined/src/ifu/satCounter2.sv index 1a0d5a27..514a2956 100644 --- a/pipelined/src/ifu/satCounter2.sv +++ b/pipelined/src/ifu/satCounter2.sv @@ -8,7 +8,7 @@ // // Purpose: 2 bit starting counter // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/speculativeglobalhistory.sv b/pipelined/src/ifu/speculativeglobalhistory.sv index 7a099e74..6a4e3da0 100644 --- a/pipelined/src/ifu/speculativeglobalhistory.sv +++ b/pipelined/src/ifu/speculativeglobalhistory.sv @@ -8,7 +8,7 @@ // // Purpose: Global History Branch predictor with parameterized global history register // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/speculativegshare.sv b/pipelined/src/ifu/speculativegshare.sv index 0febd925..943a1b78 100644 --- a/pipelined/src/ifu/speculativegshare.sv +++ b/pipelined/src/ifu/speculativegshare.sv @@ -8,7 +8,7 @@ // // Purpose: Global History Branch predictor with parameterized global history register // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/spillsupport.sv b/pipelined/src/ifu/spillsupport.sv index 7835fc00..3cf6ea94 100644 --- a/pipelined/src/ifu/spillsupport.sv +++ b/pipelined/src/ifu/spillsupport.sv @@ -8,7 +8,7 @@ // cache line boundaries or if instruction address without a cache crosses // XLEN/8 boundary. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/ifu/twoBitPredictor.sv b/pipelined/src/ifu/twoBitPredictor.sv index a7d2669a..3e41dfc4 100644 --- a/pipelined/src/ifu/twoBitPredictor.sv +++ b/pipelined/src/ifu/twoBitPredictor.sv @@ -8,7 +8,7 @@ // // Purpose: 2 bit saturating counter predictor with parameterized table depth. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/lsu/atomic.sv b/pipelined/src/lsu/atomic.sv index c61acd99..62a4e945 100644 --- a/pipelined/src/lsu/atomic.sv +++ b/pipelined/src/lsu/atomic.sv @@ -6,7 +6,7 @@ // // Purpose: atomic data path. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/lsu/dtim.sv b/pipelined/src/lsu/dtim.sv index 6e4689ef..3ad107ae 100644 --- a/pipelined/src/lsu/dtim.sv +++ b/pipelined/src/lsu/dtim.sv @@ -5,7 +5,7 @@ // Modified: // // Purpose: simple memory with bus or cache. -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/lsu/endianswap.sv b/pipelined/src/lsu/endianswap.sv index 1b3497fa..46a47871 100644 --- a/pipelined/src/lsu/endianswap.sv +++ b/pipelined/src/lsu/endianswap.sv @@ -6,7 +6,7 @@ // // Purpose: Swap byte order for Big-Endian accesses // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/lsu/lrsc.sv b/pipelined/src/lsu/lrsc.sv index f4a4b9ff..b1426116 100644 --- a/pipelined/src/lsu/lrsc.sv +++ b/pipelined/src/lsu/lrsc.sv @@ -7,7 +7,7 @@ // Purpose: Load Reserved / Store Conditional unit // Track the reservation and squash the store if it fails // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index daf203f8..2c7fd8d9 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -8,7 +8,7 @@ // Top level of the memory-stage core logic // Contains data cache, DTLB, subword read/write datapath, interface to external bus // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/lsu/subwordread.sv b/pipelined/src/lsu/subwordread.sv index 2b8854e5..0a31408a 100644 --- a/pipelined/src/lsu/subwordread.sv +++ b/pipelined/src/lsu/subwordread.sv @@ -6,7 +6,7 @@ // // Purpose: Extract subwords and sign extend for reads // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/lsu/subwordwrite.sv b/pipelined/src/lsu/subwordwrite.sv index 57607955..85b6bc50 100644 --- a/pipelined/src/lsu/subwordwrite.sv +++ b/pipelined/src/lsu/subwordwrite.sv @@ -6,7 +6,7 @@ // // Purpose: Masking and muxing for subword writes // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/lsu/swbytemask.sv b/pipelined/src/lsu/swbytemask.sv index 433a5c91..3cbde954 100644 --- a/pipelined/src/lsu/swbytemask.sv +++ b/pipelined/src/lsu/swbytemask.sv @@ -6,7 +6,7 @@ // // Purpose: On-chip RAM, external to core // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mdu/intdivrestoring.sv b/pipelined/src/mdu/intdivrestoring.sv index 59ecbe7d..dab3c2d9 100644 --- a/pipelined/src/mdu/intdivrestoring.sv +++ b/pipelined/src/mdu/intdivrestoring.sv @@ -6,7 +6,7 @@ // // Purpose: Restoring integer division using a shift register and subtractor // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mdu/intdivrestoringstep.sv b/pipelined/src/mdu/intdivrestoringstep.sv index b37afd54..95a26e82 100644 --- a/pipelined/src/mdu/intdivrestoringstep.sv +++ b/pipelined/src/mdu/intdivrestoringstep.sv @@ -6,7 +6,7 @@ // // Purpose: Restoring integer division using a shift register and subtractor // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mdu/mdu.sv b/pipelined/src/mdu/mdu.sv index 0490642c..bb242b75 100644 --- a/pipelined/src/mdu/mdu.sv +++ b/pipelined/src/mdu/mdu.sv @@ -6,7 +6,7 @@ // // Purpose: M extension multiply and divide // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mdu/mul.sv b/pipelined/src/mdu/mul.sv index a8c4e296..b94ce799 100644 --- a/pipelined/src/mdu/mul.sv +++ b/pipelined/src/mdu/mul.sv @@ -6,7 +6,7 @@ // // Purpose: Multiply instructions // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/adrdec.sv b/pipelined/src/mmu/adrdec.sv index 6c0303cc..0d8248f2 100644 --- a/pipelined/src/mmu/adrdec.sv +++ b/pipelined/src/mmu/adrdec.sv @@ -6,7 +6,7 @@ // // Purpose: Address decoder // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/adrdecs.sv b/pipelined/src/mmu/adrdecs.sv index 8dc9c45c..4df5187d 100644 --- a/pipelined/src/mmu/adrdecs.sv +++ b/pipelined/src/mmu/adrdecs.sv @@ -6,7 +6,7 @@ // // Purpose: All the address decoders for peripherals // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/hptw.sv b/pipelined/src/mmu/hptw.sv index 67e4a83b..d155e6c7 100644 --- a/pipelined/src/mmu/hptw.sv +++ b/pipelined/src/mmu/hptw.sv @@ -11,7 +11,7 @@ // Purpose: Page Table Walker // Part of the Memory Management Unit (MMU) // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/mmu.sv b/pipelined/src/mmu/mmu.sv index 1949bf13..f36ae7de 100644 --- a/pipelined/src/mmu/mmu.sv +++ b/pipelined/src/mmu/mmu.sv @@ -6,7 +6,7 @@ // // Purpose: Memory management unit, including TLB, PMA, PMP // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/pmachecker.sv b/pipelined/src/mmu/pmachecker.sv index f74cff2a..367fef39 100644 --- a/pipelined/src/mmu/pmachecker.sv +++ b/pipelined/src/mmu/pmachecker.sv @@ -8,7 +8,7 @@ // the memory region accessed. // Can report illegal accesses to the trap unit and cause a fault. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/pmpadrdec.sv b/pipelined/src/mmu/pmpadrdec.sv index fb3e2c61..0eaf623d 100644 --- a/pipelined/src/mmu/pmpadrdec.sv +++ b/pipelined/src/mmu/pmpadrdec.sv @@ -10,7 +10,7 @@ // naturally aligned power-of-two region/NAPOT), then selects the // output based on which mode is input. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/pmpchecker.sv b/pipelined/src/mmu/pmpchecker.sv index c6f357a6..ae3f03e6 100644 --- a/pipelined/src/mmu/pmpchecker.sv +++ b/pipelined/src/mmu/pmpchecker.sv @@ -9,7 +9,7 @@ // Can raise an access fault on illegal reads, writes, and instruction // fetches. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/tlb.sv b/pipelined/src/mmu/tlb.sv index 7d5e51bb..d80fe2bb 100644 --- a/pipelined/src/mmu/tlb.sv +++ b/pipelined/src/mmu/tlb.sv @@ -9,7 +9,7 @@ // Purpose: Translation lookaside buffer // Cache of virtural-to-physical address translations // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/tlbcam.sv b/pipelined/src/mmu/tlbcam.sv index 79a1f21e..8f21e13a 100644 --- a/pipelined/src/mmu/tlbcam.sv +++ b/pipelined/src/mmu/tlbcam.sv @@ -9,7 +9,7 @@ // Purpose: Stores virtual page numbers with cached translations. // Determines whether a given virtual page number is in the TLB. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/tlbcamline.sv b/pipelined/src/mmu/tlbcamline.sv index 627f496d..44db71fa 100644 --- a/pipelined/src/mmu/tlbcamline.sv +++ b/pipelined/src/mmu/tlbcamline.sv @@ -9,7 +9,7 @@ // Purpose: CAM line for the translation lookaside buffer (TLB) // Determines whether a virtual page number matches the stored key. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/tlbcontrol.sv b/pipelined/src/mmu/tlbcontrol.sv index eb073513..8821ccf2 100644 --- a/pipelined/src/mmu/tlbcontrol.sv +++ b/pipelined/src/mmu/tlbcontrol.sv @@ -6,7 +6,7 @@ // // Purpose: Control signals for TLB // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/tlblru.sv b/pipelined/src/mmu/tlblru.sv index ee5ac7fe..92c4a97b 100644 --- a/pipelined/src/mmu/tlblru.sv +++ b/pipelined/src/mmu/tlblru.sv @@ -7,7 +7,7 @@ // Purpose: Implementation of bit pseudo least-recently-used algorithm for // cache evictions. Outputs the index of the next entry to be written. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/tlbmixer.sv b/pipelined/src/mmu/tlbmixer.sv index 71e5ca91..2e6f5860 100644 --- a/pipelined/src/mmu/tlbmixer.sv +++ b/pipelined/src/mmu/tlbmixer.sv @@ -9,7 +9,7 @@ // number with segments from the second, based on the page type. // NOTE: this DOES NOT include the 12 bit offset, which is the same no matter the translation mode or page type. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/tlbram.sv b/pipelined/src/mmu/tlbram.sv index 8b2c59d6..fd891940 100644 --- a/pipelined/src/mmu/tlbram.sv +++ b/pipelined/src/mmu/tlbram.sv @@ -8,7 +8,7 @@ // Outputs the physical page number and access bits of the current // virtual address on a TLB hit. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/tlbramline.sv b/pipelined/src/mmu/tlbramline.sv index 6c3a3079..bfad0d7b 100644 --- a/pipelined/src/mmu/tlbramline.sv +++ b/pipelined/src/mmu/tlbramline.sv @@ -6,7 +6,7 @@ // // Purpose: One line of the RAM, with enabled flip-flop and logic for reading into distributed OR // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/mmu/vm64check.sv b/pipelined/src/mmu/vm64check.sv index ad4ff4ce..39ff328e 100644 --- a/pipelined/src/mmu/vm64check.sv +++ b/pipelined/src/mmu/vm64check.sv @@ -6,7 +6,7 @@ // // Purpose: Check for good upper address bits in RV64 mode // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index 003e5bf4..52f277f3 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -8,7 +8,7 @@ // Purpose: Counter Control and Status Registers // See RISC-V Privileged Mode Specification 20190608 // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/csrc.sv b/pipelined/src/privileged/csrc.sv index 427c8152..6b2497d4 100644 --- a/pipelined/src/privileged/csrc.sv +++ b/pipelined/src/privileged/csrc.sv @@ -9,7 +9,7 @@ // Purpose: Counter CSRs // See RISC-V Privileged Mode Specification 20190608 3.1.10-11 // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/csri.sv b/pipelined/src/privileged/csri.sv index 9d0c6aff..73a7fa02 100644 --- a/pipelined/src/privileged/csri.sv +++ b/pipelined/src/privileged/csri.sv @@ -7,7 +7,7 @@ // Purpose: Interrupt Control & Status Registers (IP, EI) // See RISC-V Privileged Mode Specification 20190608 & 20210108 draft // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/csrm.sv b/pipelined/src/privileged/csrm.sv index 1d621da9..d100285c 100644 --- a/pipelined/src/privileged/csrm.sv +++ b/pipelined/src/privileged/csrm.sv @@ -8,7 +8,7 @@ // Purpose: Machine-Mode Control and Status Registers // See RISC-V Privileged Mode Specification 20190608 // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/csrs.sv b/pipelined/src/privileged/csrs.sv index d9590d0f..2f9d8e49 100644 --- a/pipelined/src/privileged/csrs.sv +++ b/pipelined/src/privileged/csrs.sv @@ -8,7 +8,7 @@ // Purpose: Supervisor-Mode Control and Status Registers // See RISC-V Privileged Mode Specification 20190608 // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/csrsr.sv b/pipelined/src/privileged/csrsr.sv index 70505297..82e8b5d5 100644 --- a/pipelined/src/privileged/csrsr.sv +++ b/pipelined/src/privileged/csrsr.sv @@ -7,7 +7,7 @@ // Purpose: Status register // See RISC-V Privileged Mode Specification 20190608 // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/csru.sv b/pipelined/src/privileged/csru.sv index 0bf35694..3bc02de3 100644 --- a/pipelined/src/privileged/csru.sv +++ b/pipelined/src/privileged/csru.sv @@ -8,7 +8,7 @@ // See RISC-V Privileged Mode Specification 20190608 Table 2.2 // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/privdec.sv b/pipelined/src/privileged/privdec.sv index d2729e9f..30838638 100644 --- a/pipelined/src/privileged/privdec.sv +++ b/pipelined/src/privileged/privdec.sv @@ -7,7 +7,7 @@ // Purpose: Decode Privileged & related instructions // See RISC-V Privileged Mode Specification 20190608 3.1.10-11 // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index edaca1da..73ecfada 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -7,7 +7,7 @@ // Purpose: Implements the CSRs, Exceptions, and Privileged operations // See RISC-V Privileged Mode Specification 20190608 // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/privmode.sv b/pipelined/src/privileged/privmode.sv index 1eb6b4db..6ce4e910 100644 --- a/pipelined/src/privileged/privmode.sv +++ b/pipelined/src/privileged/privmode.sv @@ -7,7 +7,7 @@ // Purpose: Track privilege mode // See RISC-V Privileged Mode Specification 20190608 3.1.10-11 // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/privpiperegs.sv b/pipelined/src/privileged/privpiperegs.sv index 52761855..6ba6b3ba 100644 --- a/pipelined/src/privileged/privpiperegs.sv +++ b/pipelined/src/privileged/privpiperegs.sv @@ -6,7 +6,7 @@ // // Purpose: Pipeline registers for early exceptions // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv index 05f1f6e9..95ceddb6 100644 --- a/pipelined/src/privileged/trap.sv +++ b/pipelined/src/privileged/trap.sv @@ -7,7 +7,7 @@ // Purpose: Handle Traps: Exceptions and Interrupts // See RISC-V Privileged Mode Specification 20190608 3.1.10-11 // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/ahbapbbridge.sv b/pipelined/src/uncore/ahbapbbridge.sv index 2a365695..9c72d1f5 100644 --- a/pipelined/src/uncore/ahbapbbridge.sv +++ b/pipelined/src/uncore/ahbapbbridge.sv @@ -5,7 +5,7 @@ // // Purpose: AHB to APB bridge // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/clint_apb.sv b/pipelined/src/uncore/clint_apb.sv index e80be7d7..679d2c8e 100644 --- a/pipelined/src/uncore/clint_apb.sv +++ b/pipelined/src/uncore/clint_apb.sv @@ -7,7 +7,7 @@ // Purpose: Core-Local Interruptor // See FE310-G002-Manual-v19p05 for specifications // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/gpio_apb.sv b/pipelined/src/uncore/gpio_apb.sv index f84707a8..1cc33f07 100644 --- a/pipelined/src/uncore/gpio_apb.sv +++ b/pipelined/src/uncore/gpio_apb.sv @@ -8,7 +8,7 @@ // See FE310-G002-Manual-v19p05 for specifications // No interrupts, drive strength, or pull-ups supported // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/plic_apb.sv b/pipelined/src/uncore/plic_apb.sv index bf580334..c39c0329 100644 --- a/pipelined/src/uncore/plic_apb.sv +++ b/pipelined/src/uncore/plic_apb.sv @@ -13,7 +13,7 @@ // Do we detect requests as level-triggered or edge-trigged? // If edge-triggered, do we want to allow 1 source to be able to make a number of repeated requests? // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/ram_ahb.sv b/pipelined/src/uncore/ram_ahb.sv index 2a0a1b3f..1834f21b 100644 --- a/pipelined/src/uncore/ram_ahb.sv +++ b/pipelined/src/uncore/ram_ahb.sv @@ -6,7 +6,7 @@ // // Purpose: On-chip RAM, external to core, with AHB interface // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/rom_ahb.sv b/pipelined/src/uncore/rom_ahb.sv index 9aba4d68..72bfbe71 100644 --- a/pipelined/src/uncore/rom_ahb.sv +++ b/pipelined/src/uncore/rom_ahb.sv @@ -6,7 +6,7 @@ // // Purpose: On-chip ROM, external to core // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/SDC.sv b/pipelined/src/uncore/sdc/SDC.sv index f756e45e..b8c5cfde 100644 --- a/pipelined/src/uncore/sdc/SDC.sv +++ b/pipelined/src/uncore/sdc/SDC.sv @@ -6,7 +6,7 @@ // // Purpose: SDC interface to AHBLite BUS. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/SDCcounter.sv b/pipelined/src/uncore/sdc/SDCcounter.sv index 8009790f..e6107c04 100644 --- a/pipelined/src/uncore/sdc/SDCcounter.sv +++ b/pipelined/src/uncore/sdc/SDCcounter.sv @@ -7,7 +7,7 @@ // // Purpose: basic up counter // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/clkdivider.sv b/pipelined/src/uncore/sdc/clkdivider.sv index 44f58257..d475b395 100644 --- a/pipelined/src/uncore/sdc/clkdivider.sv +++ b/pipelined/src/uncore/sdc/clkdivider.sv @@ -7,7 +7,7 @@ // // Purpose: clock divider for sd flash // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/crc16_sipo_np_ce.sv b/pipelined/src/uncore/sdc/crc16_sipo_np_ce.sv index 4cc43211..6baabdba 100644 --- a/pipelined/src/uncore/sdc/crc16_sipo_np_ce.sv +++ b/pipelined/src/uncore/sdc/crc16_sipo_np_ce.sv @@ -8,7 +8,7 @@ // Purpose: CRC16 generator SIPO using register_ce // w/o appending any zero-bits to the message // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/crc7_pipo.sv b/pipelined/src/uncore/sdc/crc7_pipo.sv index 797e62f6..a2dc06fc 100644 --- a/pipelined/src/uncore/sdc/crc7_pipo.sv +++ b/pipelined/src/uncore/sdc/crc7_pipo.sv @@ -9,7 +9,7 @@ // clock cycle! // w/o appending any zero-bits to the message // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/crc7_sipo_np_ce.sv b/pipelined/src/uncore/sdc/crc7_sipo_np_ce.sv index 8f7fb928..3a52b5c4 100644 --- a/pipelined/src/uncore/sdc/crc7_sipo_np_ce.sv +++ b/pipelined/src/uncore/sdc/crc7_sipo_np_ce.sv @@ -7,7 +7,7 @@ // Purpose: CRC7 generator SIPO using register_ce // w/o appending any zero-bits othe message // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/piso_generic_ce.sv b/pipelined/src/uncore/sdc/piso_generic_ce.sv index 2d332b43..f134212c 100644 --- a/pipelined/src/uncore/sdc/piso_generic_ce.sv +++ b/pipelined/src/uncore/sdc/piso_generic_ce.sv @@ -5,7 +5,7 @@ // Modified: Ross Thompson September 18, 2021 // // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/regfile_p2r1w1_nibo.sv b/pipelined/src/uncore/sdc/regfile_p2r1w1_nibo.sv index 1956cbc7..e6318837 100644 --- a/pipelined/src/uncore/sdc/regfile_p2r1w1_nibo.sv +++ b/pipelined/src/uncore/sdc/regfile_p2r1w1_nibo.sv @@ -5,7 +5,7 @@ // Modified: 2 port register file with 1 read and 1 write // // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/regfile_p2r1w1bwen.sv b/pipelined/src/uncore/sdc/regfile_p2r1w1bwen.sv index d0817972..bd050c4e 100644 --- a/pipelined/src/uncore/sdc/regfile_p2r1w1bwen.sv +++ b/pipelined/src/uncore/sdc/regfile_p2r1w1bwen.sv @@ -5,7 +5,7 @@ // Modified: 2 port register file with 1 read and 1 write // // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/sd_clk_fsm.sv b/pipelined/src/uncore/sdc/sd_clk_fsm.sv index 327a833c..6ec8ada1 100644 --- a/pipelined/src/uncore/sdc/sd_clk_fsm.sv +++ b/pipelined/src/uncore/sdc/sd_clk_fsm.sv @@ -15,7 +15,7 @@ // It must be synchronized with 50 MHz and held for a minimum period of a full // 400 KHz pulse width. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/sd_cmd_fsm.sv b/pipelined/src/uncore/sdc/sd_cmd_fsm.sv index b1b4a163..4769e6ea 100644 --- a/pipelined/src/uncore/sdc/sd_cmd_fsm.sv +++ b/pipelined/src/uncore/sdc/sd_cmd_fsm.sv @@ -6,7 +6,7 @@ // // Purpose: Finite state machine for the SD CMD bus // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/sd_dat_fsm.sv b/pipelined/src/uncore/sdc/sd_dat_fsm.sv index 49ba94bf..47668752 100644 --- a/pipelined/src/uncore/sdc/sd_dat_fsm.sv +++ b/pipelined/src/uncore/sdc/sd_dat_fsm.sv @@ -8,7 +8,7 @@ // bus of the SD card. // 14 State Mealy FSM + Safe state = 15 State Mealy FSM // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/sd_top.sv b/pipelined/src/uncore/sdc/sd_top.sv index 7a9c35fa..90ae706a 100644 --- a/pipelined/src/uncore/sdc/sd_top.sv +++ b/pipelined/src/uncore/sdc/sd_top.sv @@ -6,7 +6,7 @@ // // Purpose: SD card controller // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/simple_timer.sv b/pipelined/src/uncore/sdc/simple_timer.sv index 0e6afa75..ad04877e 100644 --- a/pipelined/src/uncore/sdc/simple_timer.sv +++ b/pipelined/src/uncore/sdc/simple_timer.sv @@ -6,7 +6,7 @@ // // Purpose: SD card controller // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/sipo_generic_ce.sv b/pipelined/src/uncore/sdc/sipo_generic_ce.sv index ed55559d..54f513c3 100644 --- a/pipelined/src/uncore/sdc/sipo_generic_ce.sv +++ b/pipelined/src/uncore/sdc/sipo_generic_ce.sv @@ -9,7 +9,7 @@ // bit first. // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/sdc/up_down_counter.sv b/pipelined/src/uncore/sdc/up_down_counter.sv index 894df369..685f7408 100644 --- a/pipelined/src/uncore/sdc/up_down_counter.sv +++ b/pipelined/src/uncore/sdc/up_down_counter.sv @@ -6,7 +6,7 @@ // // Purpose: basic up counter // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/uartPC16550D.sv b/pipelined/src/uncore/uartPC16550D.sv index f627aca8..3217c3c6 100644 --- a/pipelined/src/uncore/uartPC16550D.sv +++ b/pipelined/src/uncore/uartPC16550D.sv @@ -13,7 +13,7 @@ // Generates 2 rather than 1.5 stop bits when 5-bit word length is slected and LCR[2] = 1 // Timeout not ye implemented*** // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/uart_apb.sv b/pipelined/src/uncore/uart_apb.sv index f1d6fd7a..d5389bb3 100644 --- a/pipelined/src/uncore/uart_apb.sv +++ b/pipelined/src/uncore/uart_apb.sv @@ -8,7 +8,7 @@ // Emulates interface of Texas Instruments PC165550D // Compatible with UART in Imperas Virtio model *** // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/uncore/uncore.sv b/pipelined/src/uncore/uncore.sv index 1ca9d3cb..7a6c3dc0 100644 --- a/pipelined/src/uncore/uncore.sv +++ b/pipelined/src/uncore/uncore.sv @@ -7,7 +7,7 @@ // Purpose: System-on-Chip components outside the core // Memories, peripherals, external bus control // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index b6d04b62..6954a9da 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -6,7 +6,7 @@ // // Purpose: Pipelined RISC-V Processor // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/wally/wallypipelinedsoc.sv b/pipelined/src/wally/wallypipelinedsoc.sv index 69c3ce04..066cecb2 100644 --- a/pipelined/src/wally/wallypipelinedsoc.sv +++ b/pipelined/src/wally/wallypipelinedsoc.sv @@ -12,7 +12,7 @@ //- Changing from RV64 to RV32 by writing the SXL/UXL bits of the STATUS register // As of January 2020, virtual memory is not yet supported // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University // diff --git a/pipelined/src/wally/wallypipelinedsocwrapper.v b/pipelined/src/wally/wallypipelinedsocwrapper.v index a812924c..33e454f3 100644 --- a/pipelined/src/wally/wallypipelinedsocwrapper.v +++ b/pipelined/src/wally/wallypipelinedsocwrapper.v @@ -12,7 +12,7 @@ //- Changing from RV64 to RV32 by writing the SXL/UXL bits of the STATUS register // As of January 2020, virtual memory is not yet supported // -// A component of the CORE-V Wally configurable RISC-V project. +// A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University //