From 8c4e6baf4883c5858e98c51858dc07ff39a83ccf Mon Sep 17 00:00:00 2001 From: bbracker Date: Mon, 25 Oct 2021 12:25:32 -0700 Subject: [PATCH] change CHECKPOINT to be a parameter (not a macro) so that do scripts can control it; clean up checkpoint initialization macros --- .../regression/regression-wally.py | 4 +- wally-pipelined/regression/sim-buildroot | 34 ++- .../regression/sim-buildroot-batch | 35 ++- .../regression/wally-buildroot-batch.do | 3 +- wally-pipelined/regression/wally-buildroot.do | 2 +- wally-pipelined/testbench/testbench-linux.sv | 221 +++++++++--------- 6 files changed, 176 insertions(+), 123 deletions(-) diff --git a/wally-pipelined/regression/regression-wally.py b/wally-pipelined/regression/regression-wally.py index c04941a0..ec06956b 100755 --- a/wally-pipelined/regression/regression-wally.py +++ b/wally-pipelined/regression/regression-wally.py @@ -34,10 +34,10 @@ def getBuildrootTC(short): INSTR_LIMIT = 100000 # multiple of 100000 MAX_EXPECTED = 3000000 if short: - BRcmd="vsim > {} -c < {} -c < {} -c < {} -c < 10000) ? INSTR_LIMIT-10000 : 1; // # of instructions at which to turn on waves in graphical sim - //parameter CHECKPOINT = 0; + // Recommend setting all of these in do script using -G option + parameter INSTR_LIMIT = 0; // # of instructions at which to stop + parameter INSTR_WAVEON = 0; // # of instructions at which to turn on waves in graphical sim + parameter CHECKPOINT = 0; /////////////////////////////////////////////////////////////////////////////// ////////////////////////////////// HARDWARE /////////////////////////////////// @@ -80,7 +75,8 @@ module testbench(); .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, .UARTSout); - // Write Back stage signals not needed by Wally itself + // Write Back stage signals not needed by Wally itself + parameter nop = 'h13; logic [`XLEN-1:0] PCW; logic [31:0] InstrW; logic InstrValidW; @@ -103,6 +99,9 @@ module testbench(); integer errorCount = 0; integer fault; string ProgramAddrMapFile, ProgramLabelMapFile; + // Checkpointing + string checkpointDir; + logic [1:0] initPriv; // Signals used to parse the trace file integer data_file_all; string name; @@ -207,30 +206,111 @@ module testbench(); /////////////////////////////////////////////////////////////////////////////// /////////////////////////////// INITIALIZATION //////////////////////////////// /////////////////////////////////////////////////////////////////////////////// + // Checkpoint initializations + `define MAKE_CHECKPOINT_INIT_SIGNAL(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \ + logic DIM init``SIGNAL[ARRAY_MAX:ARRAY_MIN]; \ + initial begin \ + #1; \ + if (CHECKPOINT!=0) $readmemh({checkpointDir,"checkpoint-",`"SIGNAL`"}, init``SIGNAL); \ + end + + `define INIT_CHECKPOINT_SIMPLE_ARRAY(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \ + `MAKE_CHECKPOINT_INIT_SIGNAL(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \ + initial begin \ + if (CHECKPOINT!=0) begin \ + force `SIGNAL = init``SIGNAL[ARRAY_MAX:ARRAY_MIN]; \ + #23; \ + release `SIGNAL; \ + end \ + end + + // For the annoying case where the pathname to the array elements includes + // a "genblk" in the signal name + `define INIT_CHECKPOINT_GENBLK_ARRAY(SIGNAL_BASE,SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \ + `MAKE_CHECKPOINT_INIT_SIGNAL(SIGNAL,DIM,ARRAY_MAX,ARRAY_MIN) \ + for (i=ARRAY_MIN; i> 3); - `ifdef CHECKPOINT - $readmemh({`CHECKPOINT_DIR,"ram.txt"}, dut.uncore.dtim.RAM); - `else - $readmemh({`LINUX_TEST_VECTORS,"ram.txt"}, dut.uncore.dtim.RAM); - `endif $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem); $readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.mem); ProgramAddrMapFile = {`LINUX_TEST_VECTORS,"vmlinux.objdump.addr"}; ProgramLabelMapFile = {`LINUX_TEST_VECTORS,"vmlinux.objdump.lab"}; - `ifdef CHECKPOINT - data_file_all = $fopen({`CHECKPOINT_DIR,"all.txt"}, "r"); - `else + if (CHECKPOINT==0) begin // normal + $readmemh({`LINUX_TEST_VECTORS,"ram.txt"}, dut.uncore.dtim.RAM); data_file_all = $fopen({`LINUX_TEST_VECTORS,"all.txt"}, "r"); - `endif - `ifdef CHECKPOINT - InstrCountW = `CHECKPOINT; - `else InstrCountW = '0; - `endif - force dut.hart.priv.SwIntM = 0; - force dut.hart.priv.TimerIntM = 0; - force dut.hart.priv.ExtIntM = 0; + end else begin // checkpoint + $sformat(checkpointDir,"checkpoint%0d/",CHECKPOINT); + checkpointDir = {`LINUX_TEST_VECTORS,checkpointDir}; + $readmemh({checkpointDir,"ram.txt"}, dut.uncore.dtim.RAM); + data_file_all = $fopen({checkpointDir,"all.txt"}, "r"); + InstrCountW = CHECKPOINT; + // manual checkpoint initializations that don't neatly fit into MACRO + force {`STATUS_TSR,`STATUS_TW,`STATUS_TVM,`STATUS_MXR,`STATUS_SUM,`STATUS_MPRV} = initMSTATUS[0][22:17]; + force {`STATUS_FS,`STATUS_MPP} = initMSTATUS[0][14:11]; + force {`STATUS_SPP,`STATUS_MPIE} = initMSTATUS[0][8:7]; + force {`STATUS_SPIE,`STATUS_UPIE,`STATUS_MIE} = initMSTATUS[0][5:3]; + force {`STATUS_SIE,`STATUS_UIE} = initMSTATUS[0][1:0]; + force `INSTRET = CHECKPOINT; + force `CURR_PRIV = initPriv; + #23; + release {`STATUS_TSR,`STATUS_TW,`STATUS_TVM,`STATUS_MXR,`STATUS_SUM,`STATUS_MPRV}; + release {`STATUS_FS,`STATUS_MPP}; + release {`STATUS_SPP,`STATUS_MPIE}; + release {`STATUS_SPIE,`STATUS_UPIE,`STATUS_MIE}; + release {`STATUS_SIE,`STATUS_UIE}; + release `INSTRET; + release `CURR_PRIV; + end end /////////////////////////////////////////////////////////////////////////////// @@ -473,94 +553,6 @@ module testbench(); .ProgramLabelMapFile(ProgramLabelMapFile)); - `ifdef CHECKPOINT - - `define INIT_CHECKPOINT_VAL(SIGNAL_BASE,SIGNAL,DIM,LARGE_INDEX,SMALL_INDEX) \ - logic DIM init``SIGNAL [LARGE_INDEX:SMALL_INDEX]; \ - initial $readmemh({`CHECKPOINT_DIR,"checkpoint-",`"SIGNAL`"}, init``SIGNAL); \ - for (i=SMALL_INDEX; i