From 8b8f045491f7a7cf88ceb1cdcd93a3bd189d9ad0 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 3 Aug 2022 09:33:56 -0700 Subject: [PATCH] Completed PLIC-S tests. Regression working. This completes peripheral tests. --- pipelined/testbench/tests.vh | 1 - tests/riscof/Makefile | 4 +- .../WALLY-plic-s-01.reference_output | 41 ++++++- .../rv32i_m/privilege/src/WALLY-plic-s-01.S | 109 +++++++++++++++++- 4 files changed, 149 insertions(+), 6 deletions(-) diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index f484c4b6..fe3bd62f 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -1899,7 +1899,6 @@ string imperas32f[] = '{ string wally32periph[] = '{ `WALLYTEST, - "rv32i_m/privilege/src/WALLY-plic-s-01.S", // ***duplicated during test "rv32i_m/privilege/src/WALLY-gpio-01.S", "rv32i_m/privilege/src/WALLY-clint-01.S", "rv32i_m/privilege/src/WALLY-uart-01.S", diff --git a/tests/riscof/Makefile b/tests/riscof/Makefile index 63f94900..28906e09 100644 --- a/tests/riscof/Makefile +++ b/tests/riscof/Makefile @@ -8,8 +8,8 @@ wally_workdir = $(work)/wally-riscv-arch-test current_dir = $(shell pwd) #XLEN ?= 64 -#all: root fsd_fld_tempfix arch32 wally32 wally32e arch64 wally64 -all: root fsd_fld_tempfix wally32 +all: root fsd_fld_tempfix arch32 wally32 wally32e arch64 wally64 +#all: root fsd_fld_tempfix wally32 root: mkdir -p $(work_dir) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-plic-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-plic-s-01.reference_output index 65a9f4d7..007e6b89 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-plic-s-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-plic-s-01.reference_output @@ -1,8 +1,45 @@ 0000000b # ecall for change to supervisor mode -00000200 # read SIP with supervisor interrupt -00000008 # check GPIO interrupt pending on intPending1 +00000200 # 1.1: read SIP with supervisor interrupt +00000008 # check GPIO interrupt pending on intPending0 00000003 # Claim GPIO in supervisor context 00000000 # No interrupts pending 00000000 # No interrupts pending +00000200 # 1.2: read SIP with supervisor interrupt +00000008 # check GPIO interrupt pending on intPending0 +00000003 # Claim GPIO in supervisor context +00000000 # No interrupts pending +00000000 # No interrupts pending + +00000000 # 1.3: read SIP with supervisor interrupt +00000008 # check GPIO interrupt pending on intPending0 +00000000 # No claim +00000008 # Interrupt unclaimed and still pending +00000000 # No interrupts pending + +00000000 # 1.4: read SIP with supervisor interrupt +00000008 # check GPIO interrupt pending on intPending0 +00000000 # No claim +00000008 # Interrupt unclaimed and still pending +00000000 # No interrupts pending + +00000000 # 1.5: read SIP with supervisor interrupt +00000008 # check GPIO interrupt pending on intPending0 +00000003 # Claim GPIO in supervisor context even though it is masked by priority +00000000 # No interrupts pending +00000000 # No interrupts pending + +00000200 # 1.6: read SIP with supervisor interrupt +00000008 # check GPIO interrupt pending on intPending0 +00000003 # Claim GPIO in supervisor context +00000000 # No interrupts pending +00000000 # No interrupts pending + +00000000 # 1.7: read SIP with supervisor interrupt +00000008 # check GPIO interrupt pending on intPending0 +00000003 # Glaim GPIO in supervisor conxtex even though it is masked by priority +00000000 # No interrupts pending +00000000 # No interrupts pending + + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-s-01.S index 0c801c29..68dcf82b 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-s-01.S @@ -105,19 +105,126 @@ test_cases: .4byte 0x0, 0x0, goto_s_mode # Enter supervisor mode # =========== Test interrupt enables and priorities =========== + +# Case 1.1: .4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1 .4byte PLIC_INTEN00, 0x00000008, write32_test # enable GPIO m-mode interrupts .4byte PLIC_INTEN10, 0x00000008, write32_test # enable GPIO s-mode interrupts .4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 .4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 .4byte output_val, 0x00000001, write32_test # cause rise_ip to go high -.4byte 0x0, 0x00000800, readsip_test # read mip +.4byte 0x0, 0x00000200, readsip_test # read sip .4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO .4byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register .4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO .4byte output_val, 0x00000000, write32_test # clear output_val .4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt .4byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier +.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt from PLIC .4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending +# Case 1.2: +.4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1 +.4byte PLIC_INTEN00, 0x00000000, write32_test # enable GPIO m-mode interrupts +.4byte PLIC_INTEN10, 0x00000008, write32_test # enable GPIO s-mode interrupts +.4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 +.4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 +.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.4byte 0x0, 0x00000200, readsip_test # read sip +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO +.4byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.4byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier +.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt from PLIC +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Case 1.3: +.4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1 +.4byte PLIC_INTEN00, 0x00000008, write32_test # enable GPIO m-mode interrupts +.4byte PLIC_INTEN10, 0x00000000, write32_test # enable GPIO s-mode interrupts +.4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 +.4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 +.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.4byte 0x0, 0x00000000, readsip_test # read sip +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO +.4byte PLIC_CLAIM1, 0x00000000, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for GPIO +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.4byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier +.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt from PLIC +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Case 1.4: +.4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1 +.4byte PLIC_INTEN00, 0x00000000, write32_test # enable GPIO m-mode interrupts +.4byte PLIC_INTEN10, 0x00000000, write32_test # enable GPIO s-mode interrupts +.4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 +.4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 +.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.4byte 0x0, 0x00000000, readsip_test # read sip +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO +.4byte PLIC_CLAIM1, 0x00000000, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for GPIO +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.4byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier +.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt from PLIC +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Case 1.5: +.4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1 +.4byte PLIC_INTEN00, 0x00000008, write32_test # enable GPIO m-mode interrupts +.4byte PLIC_INTEN10, 0x00000008, write32_test # enable GPIO s-mode interrupts +.4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 +.4byte PLIC_THRESH1, 0x00000005, write32_test # set s-mode threshold to 5 +.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.4byte 0x0, 0x00000000, readsip_test # read sip +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO +.4byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.4byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier +.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt from PLIC +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Case 1.6: +.4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1 +.4byte PLIC_INTEN00, 0x00000008, write32_test # enable GPIO m-mode interrupts +.4byte PLIC_INTEN10, 0x00000008, write32_test # enable GPIO s-mode interrupts +.4byte PLIC_THRESH0, 0x00000005, write32_test # set m-mode threshold to 5 +.4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 +.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.4byte 0x0, 0x00000200, readsip_test # read sip +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO +.4byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.4byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier +.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt from PLIC +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Case 1.7: +.4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1 +.4byte PLIC_INTEN00, 0x00000008, write32_test # enable GPIO m-mode interrupts +.4byte PLIC_INTEN10, 0x00000008, write32_test # enable GPIO s-mode interrupts +.4byte PLIC_THRESH0, 0x00000005, write32_test # set m-mode threshold to 5 +.4byte PLIC_THRESH1, 0x00000005, write32_test # set s-mode threshold to 5 +.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.4byte 0x0, 0x00000000, readsip_test # read sip +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO +.4byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.4byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier +.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt from PLIC +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# All done + .4byte 0x0, 0x0, terminate_test # terminate tests