diff --git a/wally-pipelined/src/mmu/adrdecs.sv b/wally-pipelined/src/mmu/adrdecs.sv
index 94951aad..3084b0ac 100644
--- a/wally-pipelined/src/mmu/adrdecs.sv
+++ b/wally-pipelined/src/mmu/adrdecs.sv
@@ -35,8 +35,8 @@ module adrdecs (
 
  // Determine which region of physical memory (if any) is being accessed
  // *** eventually uncomment Access signals
-  adrdec boottimdec(PhysicalAddress, `BOOTTIM_BASE, `BOOTTIM_RANGE, `BOOTTIM_SUPPORTED, 1'b1/*AccessRX*/, Size, 4'b1111, SelRegions[5]);
-  adrdec timdec(PhysicalAddress, `TIM_BASE, `TIM_RANGE, `TIM_SUPPORTED, 1'b1/*AccessRWX*/, Size, 4'b1111, SelRegions[4]);
+  adrdec boottimdec(PhysicalAddress, `BOOTTIM_BASE, `BOOTTIM_RANGE, `BOOTTIM_SUPPORTED, /*1'b1*/AccessRX, Size, 4'b1111, SelRegions[5]);
+  adrdec timdec(PhysicalAddress, `TIM_BASE, `TIM_RANGE, `TIM_SUPPORTED, /*1'b1*/AccessRWX, Size, 4'b1111, SelRegions[4]);
   adrdec clintdec(PhysicalAddress, `CLINT_BASE, `CLINT_RANGE, `CLINT_SUPPORTED, AccessRW, Size, 4'b1111, SelRegions[3]);
   adrdec gpiodec(PhysicalAddress, `GPIO_BASE, `GPIO_RANGE, `GPIO_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[2]);
   adrdec uartdec(PhysicalAddress, `UART_BASE, `UART_RANGE, `UART_SUPPORTED, AccessRW, Size, 4'b0001, SelRegions[1]);
diff --git a/wally-pipelined/src/privileged/csrsr.sv b/wally-pipelined/src/privileged/csrsr.sv
index b02baeb9..f918290a 100644
--- a/wally-pipelined/src/privileged/csrsr.sv
+++ b/wally-pipelined/src/privileged/csrsr.sv
@@ -112,6 +112,7 @@ module csrsr (
       STATUS_SUM_INT <= #1 0;
       STATUS_MPRV_INT <= #1 0; // Per Priv 3.3
       STATUS_FS_INT <= #1 0; //2'b01; // busybear: change all these reset values to 0
+      //STATUS_TVM_INT <= #1 0; // when S_SUPPORTED
       STATUS_MPP <= #1 0; //`M_MODE;
       STATUS_SPP <= #1 0; //1'b1;
       STATUS_MPIE <= #1 0; //1;
@@ -125,6 +126,7 @@ module csrsr (
         STATUS_SUM_INT <= #1 CSRWriteValM[18];
         STATUS_MPRV_INT <= #1 CSRWriteValM[17];
         STATUS_FS_INT <= #1 CSRWriteValM[14:13];
+        //STATUS_TVM_INT <= #1 CSRWriteValM[]
         STATUS_MPP <= #1 STATUS_MPP_NEXT;
         STATUS_SPP <= #1 `S_SUPPORTED & CSRWriteValM[8];
         STATUS_MPIE <= #1 CSRWriteValM[7];