diff --git a/.gitignore b/.gitignore index 1bacbd17..fca93ebb 100644 --- a/.gitignore +++ b/.gitignore @@ -52,5 +52,4 @@ examples/asm/sumtest/sumtest examples/asm/example/example examples/C/sum/sum examples/C/fir/fir - - +synthDC/hdl/*.sv diff --git a/.gitmodules b/.gitmodules index ba8877ce..b396b1d4 100644 --- a/.gitmodules +++ b/.gitmodules @@ -20,3 +20,6 @@ [submodule "addins/sky130_osu_sc_t18"] path = addins/sky130_osu_sc_t18 url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t18 +[submodule "addins/sky130_osu_sc_t12"] + path = addins/sky130_osu_sc_t12 + url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12 diff --git a/addins/sky130_osu_sc_t12 b/addins/sky130_osu_sc_t12 new file mode 160000 index 00000000..f1eef844 --- /dev/null +++ b/addins/sky130_osu_sc_t12 @@ -0,0 +1 @@ +Subproject commit f1eef844734f73d3c79d83b82352118263eb7686 diff --git a/tests/linux-testgen/buildroot-config-src/busybox.config b/linux/buildroot-config-src/busybox.config similarity index 100% rename from tests/linux-testgen/buildroot-config-src/busybox.config rename to linux/buildroot-config-src/busybox.config diff --git a/tests/linux-testgen/buildroot-config-src/linux.config b/linux/buildroot-config-src/linux.config similarity index 100% rename from tests/linux-testgen/buildroot-config-src/linux.config rename to linux/buildroot-config-src/linux.config diff --git a/tests/linux-testgen/buildroot-config-src/main.config b/linux/buildroot-config-src/main.config similarity index 100% rename from tests/linux-testgen/buildroot-config-src/main.config rename to linux/buildroot-config-src/main.config diff --git a/tests/linux-testgen/buildroot-config-src/make-buildroot.sh b/linux/buildroot-config-src/make-buildroot.sh similarity index 100% rename from tests/linux-testgen/buildroot-config-src/make-buildroot.sh rename to linux/buildroot-config-src/make-buildroot.sh diff --git a/pipelined/config/rv32etim/BTBPredictor.txt b/pipelined/config/rv32e/BTBPredictor.txt similarity index 100% rename from pipelined/config/rv32etim/BTBPredictor.txt rename to pipelined/config/rv32e/BTBPredictor.txt diff --git a/pipelined/config/rv32etim/twoBitPredictor.txt b/pipelined/config/rv32e/twoBitPredictor.txt similarity index 100% rename from pipelined/config/rv32etim/twoBitPredictor.txt rename to pipelined/config/rv32e/twoBitPredictor.txt diff --git a/pipelined/config/rv32etim/wally-config.vh b/pipelined/config/rv32e/wally-config.vh similarity index 97% rename from pipelined/config/rv32etim/wally-config.vh rename to pipelined/config/rv32e/wally-config.vh index 4f77ae8b..9102cf63 100644 --- a/pipelined/config/rv32etim/wally-config.vh +++ b/pipelined/config/rv32e/wally-config.vh @@ -48,6 +48,7 @@ `define UARCH_PIPELINED 1 `define UARCH_SUPERSCALR 0 `define UARCH_SINGLECYCLE 0 +// *** replace with MEM_BUS `define DMEM `MEM_BUS `define IMEM `MEM_BUS `define VIRTMEM_SUPPORTED 0 @@ -81,10 +82,10 @@ // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits `define BOOTROM_SUPPORTED 1'b1 `define BOOTROM_BASE 34'h00001000 -`define BOOTROM_RANGE 34'h000000FF +`define BOOTROM_RANGE 34'h00000FFF `define RAM_SUPPORTED 1'b1 `define RAM_BASE 34'h80000000 -`define RAM_RANGE 34'h000003FF +`define RAM_RANGE 34'h07FFFFFF `define EXT_MEM_SUPPORTED 1'b0 `define EXT_MEM_BASE 34'h80000000 `define EXT_MEM_RANGE 34'h07FFFFFF diff --git a/pipelined/config/rv32tim/BTBPredictor.txt b/pipelined/config/rv32tim/BTBPredictor.txt deleted file mode 100644 index fd3eedff..00000000 --- a/pipelined/config/rv32tim/BTBPredictor.txt +++ /dev/null @@ -1,1024 +0,0 @@ -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 diff --git a/pipelined/config/rv32tim/twoBitPredictor.txt b/pipelined/config/rv32tim/twoBitPredictor.txt deleted file mode 100644 index ff57bd47..00000000 --- a/pipelined/config/rv32tim/twoBitPredictor.txt +++ /dev/null @@ -1,1024 +0,0 @@ -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 diff --git a/pipelined/config/rv32tim/wally-config.vh b/pipelined/config/rv32tim/wally-config.vh deleted file mode 100644 index 713a6a6b..00000000 --- a/pipelined/config/rv32tim/wally-config.vh +++ /dev/null @@ -1,130 +0,0 @@ -////////////////////////////////////////// -// wally-config.vh -// -// Written: David_Harris@hmc.edu 4 January 2021 -// Modified: -// -// Purpose: Specify which features are configured -// Macros to determine which modes are supported based on MISA -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software -// is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -/////////////////////////////////////////// - -// include shared configuration -`include "wally-shared.vh" - -`define FPGA 0 -`define QEMU 0 -`define DESIGN_COMPILER 0 - -// RV32 or RV64: XLEN = 32 or 64 -`define XLEN 32 - -// IEEE 754 compliance -`define IEEE754 0 - -`define MISA (32'h00000104) -`define ZICSR_SUPPORTED 1 -`define ZIFENCEI_SUPPORTED 0 -`define COUNTERS 32 -`define ZICOUNTERS_SUPPORTED 0 - -// Microarchitectural Features -`define UARCH_PIPELINED 1 -`define UARCH_SUPERSCALR 0 -`define UARCH_SINGLECYCLE 0 -`define DMEM `MEM_TIM -`define IMEM `MEM_TIM -`define VIRTMEM_SUPPORTED 0 -`define VECTORED_INTERRUPTS_SUPPORTED 1 - -// TLB configuration. Entries should be a power of 2 -`define ITLB_ENTRIES 0 -`define DTLB_ENTRIES 0 - -// Cache configuration. Sizes should be a power of two -// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines -`define DCACHE_NUMWAYS 4 -`define DCACHE_WAYSIZEINBYTES 4096 -`define DCACHE_LINELENINBITS 256 -`define ICACHE_NUMWAYS 4 -`define ICACHE_WAYSIZEINBYTES 4096 -`define ICACHE_LINELENINBITS 256 - -// Integer Divider Configuration -// DIV_BITSPERCYCLE must be 1, 2, or 4 -`define DIV_BITSPERCYCLE 4 - -// Legal number of PMP entries are 0, 16, or 64 -`define PMP_ENTRIES 0 - -// Address space -`define RESET_VECTOR 32'h80000000 - -// Peripheral Addresses -// Peripheral memory space extends from BASE to BASE+RANGE -// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -`define BOOTROM_SUPPORTED 1'b1 -`define BOOTROM_BASE 34'h00001000 -`define BOOTROM_RANGE 34'h00000FFF -`define RAM_SUPPORTED 1'b1 -`define RAM_BASE 34'h80000000 -`define RAM_RANGE 34'h07FFFFFF -`define EXT_MEM_SUPPORTED 1'b0 -`define EXT_MEM_BASE 34'h80000000 -`define EXT_MEM_RANGE 34'h07FFFFFF -`define CLINT_SUPPORTED 1'b1 -`define CLINT_BASE 34'h02000000 -`define CLINT_RANGE 34'h0000FFFF -`define GPIO_SUPPORTED 1'b1 -`define GPIO_BASE 34'h10060000 -`define GPIO_RANGE 34'h000000FF -`define UART_SUPPORTED 1'b1 -`define UART_BASE 34'h10000000 -`define UART_RANGE 34'h00000007 -`define PLIC_SUPPORTED 1'b1 -`define PLIC_BASE 34'h0C000000 -`define PLIC_RANGE 34'h03FFFFFF -`define SDC_SUPPORTED 1'b0 -`define SDC_BASE 34'h00012100 -`define SDC_RANGE 34'h0000001F - -// Bus Interface width -`define AHBW 32 - -// Test modes - -// Tie GPIO outputs back to inputs -`define GPIO_LOOPBACK_TEST 1 - -// Hardware configuration -`define UART_PRESCALE 1 - -// Interrupt configuration -`define PLIC_NUM_SRC 4 -// comment out the following if >=32 sources -`define PLIC_NUM_SRC_LT_32 -`define PLIC_GPIO_ID 3 -`define PLIC_UART_ID 4 - -`define TWO_BIT_PRELOAD "../config/rv32ic/twoBitPredictor.txt" -`define BTB_PRELOAD "../config/rv32ic/BTBPredictor.txt" -`define BPRED_ENABLED 1 -`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE -`define TESTSBP 0 - -`define REPLAY 0 diff --git a/pipelined/regression/lint-wally b/pipelined/regression/lint-wally index 5968cb4d..564973a3 100755 --- a/pipelined/regression/lint-wally +++ b/pipelined/regression/lint-wally @@ -5,7 +5,7 @@ export PATH=$PATH:/usr/local/bin/ verilator=`which verilator` basepath=$(dirname $0)/.. -for config in rv64gc rv32gc rv32ic; do +for config in rv32e rv64gc rv32gc rv32ic ; do echo "$config linting..." if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes); then echo "Exiting after $config lint due to errors or warnings" diff --git a/pipelined/regression/regression-wally b/pipelined/regression/regression-wally index c3b4a1dc..a35684b3 100755 --- a/pipelined/regression/regression-wally +++ b/pipelined/regression/regression-wally @@ -48,17 +48,17 @@ def getBuildrootTC(short): INSTR_LIMIT = 100000 # multiple of 100000 MAX_EXPECTED = 246000000 if short: - BRcmd="vsim > {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c <" prompt: -# do wally-pipelined.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do wally-pipelined.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work-buildroot] { - vdel -all -lib work-buildroot -} -vlib work-buildroot - -# compile source files -# suppress spurious warnngs about -# "Extra checking for conflicts with always_comb done at vopt time" -# because vsim will run vopt -vlog -lint +incdir+../config/buildroot +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 - - -# start and run simulation -vopt work.testbench -G INSTR_LIMIT=$1 -G INSTR_WAVEON=$2 -G CHECKPOINT=$3 -o workopt - -vsim workopt -suppress 8852,12070 - -run -all -run -all -exec ./slack-notifier/slack-notifier.py -quit diff --git a/pipelined/regression/wally-buildroot.do b/pipelined/regression/wally-buildroot.do deleted file mode 100644 index 2ef74547..00000000 --- a/pipelined/regression/wally-buildroot.do +++ /dev/null @@ -1,44 +0,0 @@ -# wally-pipelined.do -# -# Modification by Oklahoma State University & Harvey Mudd College -# James Stine, 2008; David Harris 2021 -# Go Cowboys!!!!!! -# -# Takes 1:10 to run RV64IC tests using gui - -# Use this wally-pipelined.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do wally-pipelined.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do wally-pipelined.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work-buildroot] { - vdel -all -lib work-buildroot -} -vlib work-buildroot - -# compile source files -# suppress spurious warnngs about -# "Extra checking for conflicts with always_comb done at vopt time" -# because vsim will run vopt -vlog +incdir+../config/buildroot +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 - - -# start and run simulation -# remove +acc flag for faster sim during regressions if there is no need to access internal signals -vopt +acc work.testbench -G INSTR_LIMIT=$1 -G INSTR_WAVEON=$2 -G CHECKPOINT=$3 -o workopt - -vsim workopt -suppress 8852,12070 - -#-- Run the Simulation -run -all -do linux-wave.do -add log -recursive /* -run -all - -exec ./slack-notifier/slack-notifier.py -#quit diff --git a/pipelined/regression/wally-pipelined-batch.do b/pipelined/regression/wally-pipelined-batch.do index 30abbd7b..25dc23d7 100644 --- a/pipelined/regression/wally-pipelined-batch.do +++ b/pipelined/regression/wally-pipelined-batch.do @@ -32,19 +32,31 @@ vlib work_${1}_${2} # default to config/rv64ic, but allow this to be overridden at the command line. For example: # do wally-pipelined-batch.do ../config/rv32ic rv32ic -vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 +if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { + vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 + # start and run simulation + vopt work_${1}_${2}.testbench -work work_${1}_${2} -G INSTR_LIMIT=$3 -G INSTR_WAVEON=$4 -G CHECKPOINT=$5 -o testbenchopt + vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070 -# start and run simulation -# remove +acc flag for faster sim during regressions if there is no need to access internal signals -vopt work_${1}_${2}.testbench -work work_${1}_${2} -G TEST=$2 -o testbenchopt -vsim -lib work_${1}_${2} testbenchopt -# Adding coverage increases runtime from 2:00 to 4:29. Can't run it all the time -#vopt work_$2.testbench -work work_$2 -o workopt_$2 +cover=sbectf -#vsim -coverage -lib work_$2 workopt_$2 + run -all + run -all + exec ./slack-notifier/slack-notifier.py + quit +} else { + vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063 + # start and run simulation + # remove +acc flag for faster sim during regressions if there is no need to access internal signals + vopt work_${1}_${2}.testbench -work work_${1}_${2} -G TEST=$2 -o testbenchopt + vsim -lib work_${1}_${2} testbenchopt + # Adding coverage increases runtime from 2:00 to 4:29. Can't run it all the time + #vopt work_$2.testbench -work work_$2 -o workopt_$2 +cover=sbectf + #vsim -coverage -lib work_$2 workopt_$2 + + run -all + quit +} -run -all #coverage report -file wally-pipelined-coverage.txt # These aren't doing anything helpful #coverage report -memory #profile report -calltree -file wally-pipelined-calltree.rpt -cutoff 2 -quit diff --git a/pipelined/regression/wally-pipelined-tim-batch.do b/pipelined/regression/wally-pipelined-tim-batch.do deleted file mode 100644 index cc9b1c25..00000000 --- a/pipelined/regression/wally-pipelined-tim-batch.do +++ /dev/null @@ -1,50 +0,0 @@ -# wally-pipelined-batch.do -# -# Modification by Oklahoma State University & Harvey Mudd College -# Use with Testbench -# James Stine, 2008; David Harris 2021 -# Go Cowboys!!!!!! -# -# Takes 1:10 to run RV64IC tests using gui - -# Usage: do wally-pipelined-batch.do -# Example: do wally-pipelined-batch.do rv32ic imperas-32i - -# Use this wally-pipelined-batch.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do wally-pipelined-batch.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do wally-pipelined-batch.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work_${1}_${2}] { - vdel -lib work_${1}_${2} -all -} -vlib work_${1}_${2} - -# compile source files -# suppress spurious warnngs about -# "Extra checking for conflicts with always_comb done at vopt time" -# because vsim will run vopt - -# default to config/rv64ic, but allow this to be overridden at the command line. For example: -# do wally-pipelined-batch.do ../config/rv32ic rv32ic -vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-tim.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 - -# start and run simulation -# remove +acc flag for faster sim during regressions if there is no need to access internal signals -vopt work_${1}_${2}.testbench -work work_${1}_${2} -G TEST=$2 -o testbenchopt -vsim -lib work_${1}_${2} testbenchopt -# Adding coverage increases runtime from 2:00 to 4:29. Can't run it all the time -#vopt work_$2.testbench -work work_$2 -o workopt_$2 +cover=sbectf -#vsim -coverage -lib work_$2 workopt_$2 - -run -all -#coverage report -file wally-pipelined-coverage.txt -# These aren't doing anything helpful -#coverage report -memory -#profile report -calltree -file wally-pipelined-calltree.rpt -cutoff 2 -quit diff --git a/pipelined/regression/wally-pipelined-tim.do b/pipelined/regression/wally-pipelined-tim.do deleted file mode 100644 index f8244f40..00000000 --- a/pipelined/regression/wally-pipelined-tim.do +++ /dev/null @@ -1,56 +0,0 @@ -# wally-pipelined.do -# -# Modification by Oklahoma State University & Harvey Mudd College -# Use with Testbench -# James Stine, 2008; David Harris 2021 -# Go Cowboys!!!!!! -# -# Takes 1:10 to run RV64IC tests using gui - -# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m" - -# Use this wally-pipelined.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do wally-pipelined.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do wally-pipelined.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -# suppress spurious warnngs about -# "Extra checking for conflicts with always_comb done at vopt time" -# because vsim will run vopt - -# default to config/rv64ic, but allow this to be overridden at the command line. For example: -# do wally-pipelined.do ../config/rv32ic -#switch $argc { -# 0 {vlog +incdir+../config/rv64ic +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583} -# 1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583} -#} -# start and run simulation -# remove +acc flag for faster sim during regressions if there is no need to access internal signals -vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-tim.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -vopt +acc work.testbench -G TEST=$2 -o workopt -vsim workopt - -view wave --- display input and output signals as hexidecimal values -#do ./wave-dos/peripheral-waves.do -add log -recursive /* -do wave.do - --- Run the Simulation -#run 3600 -run -all -#quit -#noview ../testbench/testbench-imperas.sv -noview ../testbench/testbench.sv -view wave diff --git a/pipelined/regression/wally-pipelined.do b/pipelined/regression/wally-pipelined.do index b3ad6edf..db84feb4 100644 --- a/pipelined/regression/wally-pipelined.do +++ b/pipelined/regression/wally-pipelined.do @@ -29,28 +29,41 @@ vlib work # "Extra checking for conflicts with always_comb done at vopt time" # because vsim will run vopt -# default to config/rv64ic, but allow this to be overridden at the command line. For example: -# do wally-pipelined.do ../config/rv32ic -#switch $argc { -# 0 {vlog +incdir+../config/rv64ic +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583} -# 1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583} -#} # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals -vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -vopt +acc work.testbench -G TEST=$2 -G DEBUG=1 -o workopt -vsim workopt +nowarn3829 +if {$2 eq "buildroot"} { + vlog +incdir+../config/buildroot +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -view wave --- display input and output signals as hexidecimal values -#do ./wave-dos/peripheral-waves.do -add log -recursive /* -do wave.do --- Run the Simulation -#run 3600 -run -all -#quit -#noview ../testbench/testbench-imperas.sv -noview ../testbench/testbench.sv -view wave + # start and run simulation + # remove +acc flag for faster sim during regressions if there is no need to access internal signals + vopt +acc work.testbench -G INSTR_LIMIT=$3 -G INSTR_WAVEON=$4 -G CHECKPOINT=$5 -o workopt + + vsim workopt -suppress 8852,12070 + + #-- Run the Simulation + run -all + do linux-wave.do + add log -recursive /* + run -all + + exec ./slack-notifier/slack-notifier.py + } else { + vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063 + vopt +acc work.testbench -G TEST=$2 -G DEBUG=1 -o workopt + + vsim workopt +nowarn3829 + + view wave + #-- display input and output signals as hexidecimal values + #do ./wave-dos/peripheral-waves.do + add log -recursive /* + do wave.do + + #-- Run the Simulation + #run 3600 + run -all + noview ../testbench/testbench.sv + view wave +} + diff --git a/pipelined/src/ieu/controller.sv b/pipelined/src/ieu/controller.sv index af426975..bde552ab 100644 --- a/pipelined/src/ieu/controller.sv +++ b/pipelined/src/ieu/controller.sv @@ -166,7 +166,7 @@ module controller( // unswizzle control bits // squash control signals if coming from an illegal compressed instruction // On RV32E, can't write to upper 16 registers. Checking reads to upper 16 is more costly so disregard them. - assign IllegalERegAdrD = `E_SUPPORTED & RegWriteD & InstrD[11]; + assign IllegalERegAdrD = `E_SUPPORTED & `ZICSR_SUPPORTED & ControlsD[`CTRLW-1] & InstrD[11]; assign IllegalBaseInstrFaultD = ControlsD[0] | IllegalERegAdrD; assign {RegWriteD, ImmSrcD, ALUSrcAD, ALUSrcBD, MemRWD, ResultSrcD, BranchD, ALUOpD, JumpD, ALUResultSrcD, W64D, CSRReadD, diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 2505b657..7be1b56f 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -158,7 +158,7 @@ module ifu ( end else begin assign {ITLBMissF, InstrAccessFaultF, InstrPageFaultF} = '0; - assign PCPF = PCF; + assign PCPF = PCFExt[`PA_BITS-1:0]; assign CacheableF = '1; end @@ -170,7 +170,7 @@ module ifu ( assign InstrRawF = AllInstrRawF[31:0]; - if (`IMEM == `MEM_TIM) begin : irom // *** fix up dtim taking PA_BITS rather than XLEN + if (`IMEM == `MEM_TIM) begin : irom // *** fix up dtim taking PA_BITS rather than XLEN, *** IEUAdr is a bad name. Probably use a ROM rather than DTIM dtim irom(.clk, .reset, .CPUBusy, .LSURWM(2'b10), .IEUAdrM(PCPF[31:0]), .IEUAdrE(PCNextFSpill), .TrapM(1'b0), .FinalWriteDataM(), .ReadDataWordM(AllInstrRawF), .BusStall, .LSUBusWrite(), .LSUBusRead(IFUBusRead), @@ -200,10 +200,6 @@ module ifu ( .FinalAMOWriteDataM(), .ReadDataWordM(FinalInstrRawF), .ReadDataWordMuxM(AllInstrRawF[31:0]), .IgnoreRequest(ITLBMissF), .LSURWM(2'b10), .CPUBusy, .CacheableM(CacheableF), .BusStall, .BusCommittedM()); - - subcachelineread #(LINELEN, 32, 16) subcachelineread( - .clk, .reset, .PAdr(PCPF), .save, .restore, - .ReadDataLine, .ReadDataWord(FinalInstrRawF)); if(`IMEM == `MEM_CACHE) begin : icache logic [1:0] IFURWF; @@ -226,6 +222,10 @@ module ifu ( .PAdr(PCPF), .CacheCommitted(), .InvalidateCacheM(InvalidateICacheM)); + subcachelineread #(LINELEN, 32, 16) subcachelineread( + .clk, .reset, .PAdr(PCPF), .save, .restore, + .ReadDataLine, .ReadDataWord(FinalInstrRawF)); + end else begin : passthrough assign {ICacheFetchLine, ICacheBusAdr, ICacheStallF, FinalInstrRawF} = '0; assign ICacheAccess = CacheableF; assign ICacheMiss = CacheableF; diff --git a/pipelined/src/lsu/dtim.sv b/pipelined/src/lsu/dtim.sv index 7ebb0e8c..7fbdd42f 100644 --- a/pipelined/src/lsu/dtim.sv +++ b/pipelined/src/lsu/dtim.sv @@ -48,18 +48,18 @@ module dtim( output logic DCacheMiss, output logic DCacheAccess); - simpleram #(.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram ( - .clk, - .a(CPUBusy | LSURWM[0] | reset ? IEUAdrM[31:0] : IEUAdrE[31:0]), - .we(LSURWM[0] & ~TrapM), // have to ignore write if Trap. - .wd(FinalWriteDataM), .rd(ReadDataWordM)); + simpleram #(.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram ( + .clk, + .a(CPUBusy | LSURWM[0] | reset ? IEUAdrM[31:0] : IEUAdrE[31:0]), // move mux out; this shouldn't be needed when stails are handled differently *** + .we(LSURWM[0] & ~TrapM), // have to ignore write if Trap. + .wd(FinalWriteDataM), .rd(ReadDataWordM)); - // since we have a local memory the bus connections are all disabled. - // There are no peripherals supported. - assign {BusStall, LSUBusWrite, LSUBusRead, BusCommittedM} = '0; - assign ReadDataWordMuxM = ReadDataWordM; - assign {DCacheStallM, DCacheCommittedM} = '0; - assign {DCacheMiss, DCacheAccess} = '0; + // since we have a local memory the bus connections are all disabled. + // There are no peripherals supported. + assign {BusStall, LSUBusWrite, LSUBusRead, BusCommittedM} = '0; + assign ReadDataWordMuxM = ReadDataWordM; + assign {DCacheStallM, DCacheCommittedM} = '0; + assign {DCacheMiss, DCacheAccess} = '0; endmodule diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index c078ec89..fe8e4b76 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -207,9 +207,6 @@ module lsu ( assign WordOffsetAddr = LSUBusWrite ? ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) : LSUPAdrM; - subcachelineread #(LINELEN, `XLEN, `XLEN) subcachelineread( - .clk, .reset, .PAdr(WordOffsetAddr), .save, .restore, - .ReadDataLine(ReadDataLineM), .ReadDataWord(ReadDataWordM)); if(`DMEM == `MEM_CACHE) begin : dcache cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN), @@ -225,6 +222,10 @@ module lsu ( .CacheFetchLine(DCacheFetchLine), .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .InvalidateCacheM(1'b0)); + subcachelineread #(LINELEN, `XLEN, `XLEN) subcachelineread( + .clk, .reset, .PAdr(WordOffsetAddr), .save, .restore, + .ReadDataLine(ReadDataLineM), .ReadDataWord(ReadDataWordM)); + end else begin : passthrough assign {ReadDataWordM, DCacheStallM, DCacheCommittedM, DCacheFetchLine, DCacheWriteLine} = '0; assign DCacheMiss = CacheableM; assign DCacheAccess = CacheableM; diff --git a/pipelined/testbench/testbench-tim.sv b/pipelined/testbench/testbench-tim.sv deleted file mode 100644 index 63c96178..00000000 --- a/pipelined/testbench/testbench-tim.sv +++ /dev/null @@ -1,476 +0,0 @@ -/////////////////////////////////////////// -// testbench.sv -// -// Written: David_Harris@hmc.edu 9 January 2021 -// Modified: -// -// Purpose: Wally Testbench and helper modules -// Applies test programs from the riscv-arch-test and Imperas suites -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// MIT LICENSE -// Permission is hereby granted, free of charge, to any person obtaining a copy of this -// software and associated documentation files (the "Software"), to deal in the Software -// without restriction, including without limitation the rights to use, copy, modify, merge, -// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons -// to whom the Software is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or -// substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE -// OR OTHER DEALINGS IN THE SOFTWARE. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" -`include "tests.vh" - -module testbench; - parameter TESTSPERIPH = 0; // set to 0 for regression - parameter TESTSPRIV = 0; // set to 0 for regression - parameter DEBUG=0; - parameter TEST="none"; - - logic clk; - logic reset_ext, reset; - - parameter SIGNATURESIZE = 5000000; - - int test, i, errors, totalerrors; - logic [31:0] sig32[0:SIGNATURESIZE]; - logic [`XLEN-1:0] signature[0:SIGNATURESIZE]; - logic [`XLEN-1:0] testadr; - string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; - logic [31:0] InstrW; - logic [`XLEN-1:0] meminit; - - -string tests[]; -logic [3:0] dummy; - - string ProgramAddrMapFile, ProgramLabelMapFile; - logic [`AHBW-1:0] HRDATAEXT; - logic HREADYEXT, HRESPEXT; - logic [31:0] HADDR; - logic [`AHBW-1:0] HWDATA; - logic HWRITE; - logic [2:0] HSIZE; - logic [2:0] HBURST; - logic [3:0] HPROT; - logic [1:0] HTRANS; - logic HMASTLOCK; - logic HCLK, HRESETn; - logic [`XLEN-1:0] PCW; - - logic DCacheFlushDone, DCacheFlushStart; - - flopenr #(`XLEN) PCWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.PCM, PCW); - flopenr #(32) InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.InstrM, InstrW); - - // check assertions for a legal configuration - riscvassertions riscvassertions(); - - // pick tests based on modes supported - initial begin - $display("TEST is %s", TEST); - //tests = '{}; - if (`XLEN == 64) begin // RV64 - case (TEST) - "arch64i": tests = arch64i; - "arch64priv": tests = arch64priv; - "arch64c": if (`C_SUPPORTED) - if (`ZICSR_SUPPORTED) tests = {arch64c, arch64cpriv}; - else tests = {arch64c}; - "arch64m": if (`M_SUPPORTED) tests = arch64m; - "arch64d": if (`D_SUPPORTED) tests = arch64d; - "imperas64i": tests = imperas64i; - "imperas64p": tests = imperas64p; -// "imperas64mmu": if (`VIRTMEM_SUPPORTED) tests = imperas64mmu; - "imperas64f": if (`F_SUPPORTED) tests = imperas64f; - "imperas64d": if (`D_SUPPORTED) tests = imperas64d; - "imperas64m": if (`M_SUPPORTED) tests = imperas64m; - "imperas64a": if (`A_SUPPORTED) tests = imperas64a; - "imperas64c": if (`C_SUPPORTED) tests = imperas64c; - else tests = imperas64iNOc; - "testsBP64": tests = testsBP64; - "wally64i": tests = wally64i; // *** redo - "wally64priv": tests = wally64priv;// *** redo - "imperas64periph": tests = imperas64periph; - endcase - end else begin // RV32 - case (TEST) - "arch32i": tests = arch32i; - "arch32priv": tests = arch32priv; - "arch32c": if (`C_SUPPORTED) - if (`ZICSR_SUPPORTED) tests = {arch32c, arch32cpriv}; - else tests = {arch32c}; - "arch32m": if (`M_SUPPORTED) tests = arch32m; - "arch32f": if (`F_SUPPORTED) tests = arch32f; - "imperas32i": tests = imperas32i; - "imperas32p": tests = imperas32p; -// "imperas32mmu": if (`VIRTMEM_SUPPORTED) tests = imperas32mmu; - "imperas32f": if (`F_SUPPORTED) tests = imperas32f; - "imperas32m": if (`M_SUPPORTED) tests = imperas32m; - "imperas32a": if (`A_SUPPORTED) tests = imperas32a; - "imperas32c": if (`C_SUPPORTED) tests = imperas32c; - else tests = imperas32iNOc; - "wally32i": tests = wally32i; // *** redo - "wally32priv": tests = wally32priv; // *** redo - "imperas32periph": tests = imperas32periph; - endcase - end - if (tests.size() == 0) begin - $display("TEST %s not supported in this configuration", TEST); - $stop; - end - end - - string signame, memfilename, pathname; - - logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn; - logic UARTSin, UARTSout; - - logic SDCCLK; - logic SDCCmdIn; - logic SDCCmdOut; - logic SDCCmdOE; - logic [3:0] SDCDatIn; - - logic HREADY; - logic HSELEXT; - - - // instantiate device to be tested - assign GPIOPinsIn = 0; - assign UARTSin = 1; - assign HREADYEXT = 1; - assign HRESPEXT = 0; - assign HRDATAEXT = 0; - - wallypipelinedsoc dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT, - .HCLK, .HRESETn, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT, - .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, - .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); - - // Track names of instructions - instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE, - dut.core.ifu.FinalInstrRawF, - dut.core.ifu.InstrD, dut.core.ifu.InstrE, - dut.core.ifu.InstrM, InstrW, - InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); - - // initialize tests - localparam integer MemStartAddr = `RAM_BASE>>(1+`XLEN/32); - localparam integer MemEndAddr = (`RAM_RANGE+`RAM_BASE)>>1+(`XLEN/32); - - initial - begin - test = 1; - totalerrors = 0; - testadr = 0; - // fill memory with defined values to reduce Xs in simulation - // Quick note the memory will need to be initialized. The C library does not - // guarantee the initialized reads. For example a strcmp can read 6 byte - // strings, but uses a load double to read them in. If the last 2 bytes are - // not initialized the compare results in an 'x' which propagates through - // the design. - if (`XLEN == 32) meminit = 32'hFEDC0123; - else meminit = 64'hFEDCBA9876543210; - // *** broken because DTIM also drives RAM - if (`TESTSBP) begin - for (i=MemStartAddr; i= 128 | (`DMEM != `MEM_CACHE)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled"); - assert (`DCACHE_LINELENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size"); - assert (`ICACHE_WAYSIZEINBYTES <= 4096 | (`IMEM != `MEM_CACHE) | `VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); - assert (`ICACHE_LINELENINBITS >= 32 | (`IMEM != `MEM_CACHE)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled"); - assert (`ICACHE_LINELENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size"); - assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS | (`DMEM != `MEM_CACHE)) else $error("DCACHE_LINELENINBITS must be a power of 2"); - assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES | (`DMEM != `MEM_CACHE)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2"); - assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS | (`IMEM != `MEM_CACHE)) else $error("ICACHE_LINELENINBITS must be a power of 2"); - assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES | (`IMEM != `MEM_CACHE)) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2"); - assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("ITLB_ENTRIES must be a power of 2"); - assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("DTLB_ENTRIES must be a power of 2"); - assert (`RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if RAM_RANGE is less than 56'h07FFFFFF"); - assert (`ZICSR_SUPPORTED == 1 | (`PMP_ENTRIES == 0 & `VIRTMEM_SUPPORTED == 0)) else $error("PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported."); - assert (`ZICSR_SUPPORTED == 1 | (`S_SUPPORTED == 0 & `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZISR not supported"); - assert (`U_SUPPORTED | (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported"); - end -endmodule - - -/* verilator lint_on STMTDLY */ -/* verilator lint_on WIDTH */ - -module DCacheFlushFSM - (input logic clk, - input logic reset, - input logic start, - output logic done); - - genvar adr; - - logic [`XLEN-1:0] ShadowRAM[`RAM_BASE>>(1+`XLEN/32):(`RAM_RANGE+`RAM_BASE)>>1+(`XLEN/32)]; - - if(`DMEM == `MEM_CACHE) begin - localparam integer numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES; - localparam integer numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS; - localparam integer linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN; - localparam integer numwords = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN/`XLEN; - localparam integer lognumlines = $clog2(numlines); - localparam integer loglinebytelen = $clog2(linebytelen); - localparam integer lognumways = $clog2(numways); - localparam integer tagstart = lognumlines + loglinebytelen; - - - - genvar index, way, cacheWord; - logic [`XLEN-1:0] CacheData [numways-1:0] [numlines-1:0] [numwords-1:0]; - logic [`XLEN-1:0] CacheTag [numways-1:0] [numlines-1:0] [numwords-1:0]; - logic CacheValid [numways-1:0] [numlines-1:0] [numwords-1:0]; - logic CacheDirty [numways-1:0] [numlines-1:0] [numwords-1:0]; - logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [numwords-1:0]; - for(index = 0; index < numlines; index++) begin - for(way = 0; way < numways; way++) begin - for(cacheWord = 0; cacheWord < numwords; cacheWord++) begin - copyShadow #(.tagstart(tagstart), - .loglinebytelen(loglinebytelen)) - copyShadow(.clk, - .start, - .tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.StoredData[index]), - .valid(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].ValidBits[index]), - .dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].DirtyBits[index]), - .data(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].word[cacheWord].CacheDataMem.StoredData[index]), - .index(index), - .cacheWord(cacheWord), - .CacheData(CacheData[way][index][cacheWord]), - .CacheAdr(CacheAdr[way][index][cacheWord]), - .CacheTag(CacheTag[way][index][cacheWord]), - .CacheValid(CacheValid[way][index][cacheWord]), - .CacheDirty(CacheDirty[way][index][cacheWord])); - end - end - end - - integer i, j, k; - - always @(posedge clk) begin - if (start) begin #1 - #1 - for(i = 0; i < numlines; i++) begin - for(j = 0; j < numways; j++) begin - for(k = 0; k < numwords; k++) begin - if (CacheValid[j][i][k] & CacheDirty[j][i][k]) begin - ShadowRAM[CacheAdr[j][i][k] >> $clog2(`XLEN/8)] = CacheData[j][i][k]; - end - end - end - end - end - end - - - end - flop #(1) doneReg(.clk, .d(start), .q(done)); -endmodule - -module copyShadow - #(parameter tagstart, loglinebytelen) - (input logic clk, - input logic start, - input logic [`PA_BITS-1:tagstart] tag, - input logic valid, dirty, - input logic [`XLEN-1:0] data, - input logic [32-1:0] index, - input logic [32-1:0] cacheWord, - output logic [`XLEN-1:0] CacheData, - output logic [`PA_BITS-1:0] CacheAdr, - output logic [`XLEN-1:0] CacheTag, - output logic CacheValid, - output logic CacheDirty); - - - always_ff @(posedge clk) begin - if(start) begin - CacheTag = tag; - CacheValid = valid; - CacheDirty = dirty; - CacheData = data; - CacheAdr = (tag << tagstart) + (index << loglinebytelen) + (cacheWord << $clog2(`XLEN/8)); - end - end - -endmodule - diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 41c41a2c..3117c111 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -49,8 +49,6 @@ module testbench; logic [`XLEN-1:0] testadr; string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; logic [31:0] InstrW; - logic [`XLEN-1:0] meminit; - string tests[]; logic [3:0] dummy; @@ -123,6 +121,7 @@ logic [3:0] dummy; "imperas32c": if (`C_SUPPORTED) tests = imperas32c; else tests = imperas32iNOc; "wally32i": tests = wally32i; // *** redo + "wally32e": tests = wally32e; "wally32priv": tests = wally32priv; // *** redo "imperas32periph": tests = imperas32periph; endcase @@ -182,22 +181,20 @@ logic [3:0] dummy; // strings, but uses a load double to read them in. If the last 2 bytes are // not initialized the compare results in an 'x' which propagates through // the design. - //if (`XLEN == 32) meminit = 32'hFEDC0123; - //else meminit = 64'hFEDCBA9876543210; - // *** broken because DTIM also drives RAM - if (TEST == "coremark") begin - for (i=MemStartAddr; i= 4 & sig32[i-4] === 'bx) begin + if (i == 4) begin i = SIGNATURESIZE+1; // flag empty file $display(" Error: empty test file"); end else i = SIGNATURESIZE; // skip over the rest of the x's for efficiency @@ -252,17 +250,21 @@ logic [3:0] dummy; testadr = (`RAM_BASE+tests[test+1].atohex())/(`XLEN/8); /* verilator lint_off INFINITELOOP */ while (signature[i] !== 'bx) begin - //$display("signature[%h] = %h", i, signature[i]); - // *** have to figure out how to exclude shadowram when not using a dcache. - if (signature[i] !== dut.uncore.ram.ram.RAM[testadr+i] & + logic [`XLEN-1:0] sig; + if (`DMEM == `MEM_TIM) sig = dut.core.lsu.dtim.dtim.ram.RAM[testadr+i]; + else sig = dut.uncore.ram.ram.RAM[testadr+i]; +// $display("signature[%h] = %h sig = %h", i, signature[i], sig); + if (signature[i] !== sig & //if (signature[i] !== dut.core.lsu.dtim.ram.RAM[testadr+i] & - (signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin - if (signature[i+4] !== 'bx | signature[i] !== 32'hFFFFFFFF) begin + (signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin // ***i+1? + if ((signature[i] !== '0 | signature[i+4] !== 'x)) begin +// if (signature[i+4] !== 'bx | (signature[i] !== 32'hFFFFFFFF & signature[i] !== 32'h00000000)) begin // report errors unless they are garbage at the end of the sim // kind of hacky test for garbage right now + $display("sig4 = %h ne %b", signature[i+4], signature[i+4] !== 'bx); errors = errors+1; - $display(" Error on test %s result %d: adr = %h sim (D$) %h sim (TIM) = %h, signature = %h", - tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], dut.uncore.ram.ram.RAM[testadr+i], signature[i]); + $display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DMEM) = %h, signature = %h", + tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]); // tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], dut.core.lsu.dtim.ram.RAM[testadr+i], signature[i]); $stop;//***debug end @@ -286,7 +288,11 @@ logic [3:0] dummy; else begin //pathname = tvpaths[tests[0]]; memfilename = {pathname, tests[test], ".elf.memfile"}; - $readmemh(memfilename, dut.uncore.ram.ram.RAM); + //$readmemh(memfilename, dut.uncore.ram.ram.RAM); + if (`IMEM == `MEM_TIM) $readmemh(memfilename, dut.core.ifu.irom.irom.ram.RAM); + else $readmemh(memfilename, dut.uncore.ram.ram.RAM); + if (`DMEM == `MEM_TIM) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM); + ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"}; ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"}; $display("Read memfile %s", memfilename); diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index 14c131cf..4a78455e 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -101,739 +101,739 @@ string tvpaths[] = '{ string imperas32f[] = '{ `IMPERASTEST, "rv32i_m/F/FADD-S-DYN-RDN-01", "002010", - "rv32i_m/F/FADD-S-DYN-RMM-01", "002010", - "rv32i_m/F/FADD-S-DYN-RNE-01", "002010", - "rv32i_m/F/FADD-S-DYN-RTZ-01", "002010", - "rv32i_m/F/FADD-S-DYN-RUP-01", "002010", - "rv32i_m/F/FADD-S-RDN-01", "002010", - "rv32i_m/F/FADD-S-RMM-01", "002010", - "rv32i_m/F/FADD-S-RNE-01", "002010", - "rv32i_m/F/FADD-S-RTZ-01", "002010", - "rv32i_m/F/FADD-S-RUP-01", "002010", - "rv32i_m/F/FCLASS-S-01", "002010", - "rv32i_m/F/FCVT-S-W-DYN-RDN-01", "002010", - "rv32i_m/F/FCVT-S-W-DYN-RMM-01", "002010", - "rv32i_m/F/FCVT-S-W-DYN-RNE-01", "002010", - "rv32i_m/F/FCVT-S-W-DYN-RTZ-01", "002010", - "rv32i_m/F/FCVT-S-W-DYN-RUP-01", "002010", - "rv32i_m/F/FCVT-S-W-RDN-01", "002010", - "rv32i_m/F/FCVT-S-W-RMM-01", "002010", - "rv32i_m/F/FCVT-S-W-RNE-01", "002010", - "rv32i_m/F/FCVT-S-W-RTZ-01", "002010", - "rv32i_m/F/FCVT-S-W-RUP-01", "002010", - "rv32i_m/F/FCVT-S-WU-DYN-RDN-01", "002010", - "rv32i_m/F/FCVT-S-WU-DYN-RMM-01", "002010", - "rv32i_m/F/FCVT-S-WU-DYN-RNE-01", "002010", - "rv32i_m/F/FCVT-S-WU-DYN-RTZ-01", "002010", - "rv32i_m/F/FCVT-S-WU-DYN-RUP-01", "002010", - "rv32i_m/F/FCVT-S-WU-RDN-01", "002010", - "rv32i_m/F/FCVT-S-WU-RMM-01", "002010", - "rv32i_m/F/FCVT-S-WU-RNE-01", "002010", - "rv32i_m/F/FCVT-S-WU-RTZ-01", "002010", - "rv32i_m/F/FCVT-S-WU-RUP-01", "002010", - "rv32i_m/F/FCVT-W-S-DYN-RDN-01", "002010", - "rv32i_m/F/FCVT-W-S-DYN-RMM-01", "002010", - "rv32i_m/F/FCVT-W-S-DYN-RNE-01", "002010", - "rv32i_m/F/FCVT-W-S-DYN-RTZ-01", "002010", - "rv32i_m/F/FCVT-W-S-DYN-RUP-01", "002010", - "rv32i_m/F/FCVT-W-S-RDN-01", "002010", - "rv32i_m/F/FCVT-W-S-RMM-01", "002010", - "rv32i_m/F/FCVT-W-S-RNE-01", "002010", - "rv32i_m/F/FCVT-W-S-RTZ-01", "002010", - "rv32i_m/F/FCVT-W-S-RUP-01", "002010", - "rv32i_m/F/FCVT-WU-S-DYN-RDN-01", "002010", - "rv32i_m/F/FCVT-WU-S-DYN-RMM-01", "002010", - "rv32i_m/F/FCVT-WU-S-DYN-RNE-01", "002010", - "rv32i_m/F/FCVT-WU-S-DYN-RTZ-01", "002010", - "rv32i_m/F/FCVT-WU-S-DYN-RUP-01", "002010", - "rv32i_m/F/FCVT-WU-S-RDN-01", "002010", - "rv32i_m/F/FCVT-WU-S-RMM-01", "002010", - "rv32i_m/F/FCVT-WU-S-RNE-01", "002010", - "rv32i_m/F/FCVT-WU-S-RTZ-01", "002010", - "rv32i_m/F/FCVT-WU-S-RUP-01", "002010", - // "rv32i_m/F/FDIV-S-DYN-RDN-01", "002010", - // "rv32i_m/F/FDIV-S-DYN-RMM-01", "002010", - // "rv32i_m/F/FDIV-S-DYN-RNE-01", "002010", - // "rv32i_m/F/FDIV-S-DYN-RTZ-01", "002010", - // "rv32i_m/F/FDIV-S-DYN-RUP-01", "002010", - // "rv32i_m/F/FDIV-S-RDN-01", "002010", - // "rv32i_m/F/FDIV-S-RMM-01", "002010", - // "rv32i_m/F/FDIV-S-RNE-01", "002010", - // "rv32i_m/F/FDIV-S-RTZ-01", "002010", - // "rv32i_m/F/FDIV-S-RUP-01", "002010", - "rv32i_m/F/FEQ-S-01", "002010", - "rv32i_m/F/FLE-S-01", "002010", - "rv32i_m/F/FLT-S-01", "002010", - "rv32i_m/F/FLW-01", "002120", - "rv32i_m/F/FMADD-S-DYN-RDN-01", "002010", - "rv32i_m/F/FMADD-S-DYN-RMM-01", "002010", - "rv32i_m/F/FMADD-S-DYN-RNE-01", "002010", - "rv32i_m/F/FMADD-S-DYN-RTZ-01", "002010", - "rv32i_m/F/FMADD-S-DYN-RUP-01", "002010", - "rv32i_m/F/FMADD-S-RDN-01", "002010", - "rv32i_m/F/FMADD-S-RMM-01", "002010", - "rv32i_m/F/FMADD-S-RNE-01", "002010", - "rv32i_m/F/FMADD-S-RTZ-01", "002010", - "rv32i_m/F/FMADD-S-RUP-01", "002010", - "rv32i_m/F/FMAX-S-01", "002010", - "rv32i_m/F/FMIN-S-01", "002010", - "rv32i_m/F/FMSUB-S-DYN-RDN-01", "002010", - "rv32i_m/F/FMSUB-S-DYN-RMM-01", "002010", - "rv32i_m/F/FMSUB-S-DYN-RNE-01", "002010", - "rv32i_m/F/FMSUB-S-DYN-RTZ-01", "002010", - "rv32i_m/F/FMSUB-S-DYN-RUP-01", "002010", - "rv32i_m/F/FMSUB-S-RDN-01", "002010", - "rv32i_m/F/FMSUB-S-RMM-01", "002010", - "rv32i_m/F/FMSUB-S-RNE-01", "002010", - "rv32i_m/F/FMSUB-S-RTZ-01", "002010", - "rv32i_m/F/FMSUB-S-RUP-01", "002010", - "rv32i_m/F/FMUL-S-DYN-RDN-01", "002010", - "rv32i_m/F/FMUL-S-DYN-RMM-01", "002010", - "rv32i_m/F/FMUL-S-DYN-RNE-01", "002010", - "rv32i_m/F/FMUL-S-DYN-RTZ-01", "002010", - "rv32i_m/F/FMUL-S-DYN-RUP-01", "002010", - "rv32i_m/F/FMUL-S-RDN-01", "002010", - "rv32i_m/F/FMUL-S-RMM-01", "002010", - "rv32i_m/F/FMUL-S-RNE-01", "002010", - "rv32i_m/F/FMUL-S-RTZ-01", "002010", - "rv32i_m/F/FMUL-S-RUP-01", "002010", - "rv32i_m/F/FMV-W-X-01", "002010", - "rv32i_m/F/FMV-X-W-01", "002010", - "rv32i_m/F/FNMADD-S-DYN-RDN-01", "002010", - "rv32i_m/F/FNMADD-S-DYN-RMM-01", "002010", - "rv32i_m/F/FNMADD-S-DYN-RNE-01", "002010", - "rv32i_m/F/FNMADD-S-DYN-RTZ-01", "002010", - "rv32i_m/F/FNMADD-S-DYN-RUP-01", "002010", - "rv32i_m/F/FNMADD-S-RDN-01", "002010", - "rv32i_m/F/FNMADD-S-RMM-01", "002010", - "rv32i_m/F/FNMADD-S-RNE-01", "002010", - "rv32i_m/F/FNMADD-S-RTZ-01", "002010", - "rv32i_m/F/FNMADD-S-RUP-01", "002010", - "rv32i_m/F/FNMSUB-S-DYN-RDN-01", "002010", - "rv32i_m/F/FNMSUB-S-DYN-RMM-01", "002010", - "rv32i_m/F/FNMSUB-S-DYN-RNE-01", "002010", - "rv32i_m/F/FNMSUB-S-DYN-RTZ-01", "002010", - "rv32i_m/F/FNMSUB-S-DYN-RUP-01", "002010", - "rv32i_m/F/FNMSUB-S-RDN-01", "002010", - "rv32i_m/F/FNMSUB-S-RMM-01", "002010", - "rv32i_m/F/FNMSUB-S-RNE-01", "002010", - "rv32i_m/F/FNMSUB-S-RTZ-01", "002010", - "rv32i_m/F/FNMSUB-S-RUP-01", "002010", - "rv32i_m/F/FSGNJN-S-01", "002010", - "rv32i_m/F/FSGNJ-S-01", "002010", - "rv32i_m/F/FSGNJX-S-01", "002010", - // "rv32i_m/F/FSQRT-S-DYN-RDN-01", "002010", - // "rv32i_m/F/FSQRT-S-DYN-RMM-01", "002010", - // "rv32i_m/F/FSQRT-S-DYN-RNE-01", "002010", - // "rv32i_m/F/FSQRT-S-DYN-RTZ-01", "002010", - // "rv32i_m/F/FSQRT-S-DYN-RUP-01", "002010", - // "rv32i_m/F/FSQRT-S-RDN-01", "002010", - // "rv32i_m/F/FSQRT-S-RMM-01", "002010", - // "rv32i_m/F/FSQRT-S-RNE-01", "002010", - // "rv32i_m/F/FSQRT-S-RTZ-01", "002010", - // "rv32i_m/F/FSQRT-S-RUP-01", "002010", - "rv32i_m/F/FSUB-S-DYN-RDN-01", "002010", - "rv32i_m/F/FSUB-S-DYN-RMM-01", "002010", - "rv32i_m/F/FSUB-S-DYN-RNE-01", "002010", - "rv32i_m/F/FSUB-S-DYN-RTZ-01", "002010", - "rv32i_m/F/FSUB-S-DYN-RUP-01", "002010", - "rv32i_m/F/FSUB-S-RDN-01", "002010", - "rv32i_m/F/FSUB-S-RMM-01", "002010", - "rv32i_m/F/FSUB-S-RNE-01", "002010", - "rv32i_m/F/FSUB-S-RTZ-01", "002010", - "rv32i_m/F/FSUB-S-RUP-01", "002010", - "rv32i_m/F/FSW-01", "002010" + "rv32i_m/F/FADD-S-DYN-RMM-01", "002010", + "rv32i_m/F/FADD-S-DYN-RNE-01", "002010", + "rv32i_m/F/FADD-S-DYN-RTZ-01", "002010", + "rv32i_m/F/FADD-S-DYN-RUP-01", "002010", + "rv32i_m/F/FADD-S-RDN-01", "002010", + "rv32i_m/F/FADD-S-RMM-01", "002010", + "rv32i_m/F/FADD-S-RNE-01", "002010", + "rv32i_m/F/FADD-S-RTZ-01", "002010", + "rv32i_m/F/FADD-S-RUP-01", "002010", + "rv32i_m/F/FCLASS-S-01", "002010", + "rv32i_m/F/FCVT-S-W-DYN-RDN-01", "002010", + "rv32i_m/F/FCVT-S-W-DYN-RMM-01", "002010", + "rv32i_m/F/FCVT-S-W-DYN-RNE-01", "002010", + "rv32i_m/F/FCVT-S-W-DYN-RTZ-01", "002010", + "rv32i_m/F/FCVT-S-W-DYN-RUP-01", "002010", + "rv32i_m/F/FCVT-S-W-RDN-01", "002010", + "rv32i_m/F/FCVT-S-W-RMM-01", "002010", + "rv32i_m/F/FCVT-S-W-RNE-01", "002010", + "rv32i_m/F/FCVT-S-W-RTZ-01", "002010", + "rv32i_m/F/FCVT-S-W-RUP-01", "002010", + "rv32i_m/F/FCVT-S-WU-DYN-RDN-01", "002010", + "rv32i_m/F/FCVT-S-WU-DYN-RMM-01", "002010", + "rv32i_m/F/FCVT-S-WU-DYN-RNE-01", "002010", + "rv32i_m/F/FCVT-S-WU-DYN-RTZ-01", "002010", + "rv32i_m/F/FCVT-S-WU-DYN-RUP-01", "002010", + "rv32i_m/F/FCVT-S-WU-RDN-01", "002010", + "rv32i_m/F/FCVT-S-WU-RMM-01", "002010", + "rv32i_m/F/FCVT-S-WU-RNE-01", "002010", + "rv32i_m/F/FCVT-S-WU-RTZ-01", "002010", + "rv32i_m/F/FCVT-S-WU-RUP-01", "002010", + "rv32i_m/F/FCVT-W-S-DYN-RDN-01", "002010", + "rv32i_m/F/FCVT-W-S-DYN-RMM-01", "002010", + "rv32i_m/F/FCVT-W-S-DYN-RNE-01", "002010", + "rv32i_m/F/FCVT-W-S-DYN-RTZ-01", "002010", + "rv32i_m/F/FCVT-W-S-DYN-RUP-01", "002010", + "rv32i_m/F/FCVT-W-S-RDN-01", "002010", + "rv32i_m/F/FCVT-W-S-RMM-01", "002010", + "rv32i_m/F/FCVT-W-S-RNE-01", "002010", + "rv32i_m/F/FCVT-W-S-RTZ-01", "002010", + "rv32i_m/F/FCVT-W-S-RUP-01", "002010", + "rv32i_m/F/FCVT-WU-S-DYN-RDN-01", "002010", + "rv32i_m/F/FCVT-WU-S-DYN-RMM-01", "002010", + "rv32i_m/F/FCVT-WU-S-DYN-RNE-01", "002010", + "rv32i_m/F/FCVT-WU-S-DYN-RTZ-01", "002010", + "rv32i_m/F/FCVT-WU-S-DYN-RUP-01", "002010", + "rv32i_m/F/FCVT-WU-S-RDN-01", "002010", + "rv32i_m/F/FCVT-WU-S-RMM-01", "002010", + "rv32i_m/F/FCVT-WU-S-RNE-01", "002010", + "rv32i_m/F/FCVT-WU-S-RTZ-01", "002010", + "rv32i_m/F/FCVT-WU-S-RUP-01", "002010", + // "rv32i_m/F/FDIV-S-DYN-RDN-01", "002010", + // "rv32i_m/F/FDIV-S-DYN-RMM-01", "002010", + // "rv32i_m/F/FDIV-S-DYN-RNE-01", "002010", + // "rv32i_m/F/FDIV-S-DYN-RTZ-01", "002010", + // "rv32i_m/F/FDIV-S-DYN-RUP-01", "002010", + // "rv32i_m/F/FDIV-S-RDN-01", "002010", + // "rv32i_m/F/FDIV-S-RMM-01", "002010", + // "rv32i_m/F/FDIV-S-RNE-01", "002010", + // "rv32i_m/F/FDIV-S-RTZ-01", "002010", + // "rv32i_m/F/FDIV-S-RUP-01", "002010", + "rv32i_m/F/FEQ-S-01", "002010", + "rv32i_m/F/FLE-S-01", "002010", + "rv32i_m/F/FLT-S-01", "002010", + "rv32i_m/F/FLW-01", "002120", + "rv32i_m/F/FMADD-S-DYN-RDN-01", "002010", + "rv32i_m/F/FMADD-S-DYN-RMM-01", "002010", + "rv32i_m/F/FMADD-S-DYN-RNE-01", "002010", + "rv32i_m/F/FMADD-S-DYN-RTZ-01", "002010", + "rv32i_m/F/FMADD-S-DYN-RUP-01", "002010", + "rv32i_m/F/FMADD-S-RDN-01", "002010", + "rv32i_m/F/FMADD-S-RMM-01", "002010", + "rv32i_m/F/FMADD-S-RNE-01", "002010", + "rv32i_m/F/FMADD-S-RTZ-01", "002010", + "rv32i_m/F/FMADD-S-RUP-01", "002010", + "rv32i_m/F/FMAX-S-01", "002010", + "rv32i_m/F/FMIN-S-01", "002010", + "rv32i_m/F/FMSUB-S-DYN-RDN-01", "002010", + "rv32i_m/F/FMSUB-S-DYN-RMM-01", "002010", + "rv32i_m/F/FMSUB-S-DYN-RNE-01", "002010", + "rv32i_m/F/FMSUB-S-DYN-RTZ-01", "002010", + "rv32i_m/F/FMSUB-S-DYN-RUP-01", "002010", + "rv32i_m/F/FMSUB-S-RDN-01", "002010", + "rv32i_m/F/FMSUB-S-RMM-01", "002010", + "rv32i_m/F/FMSUB-S-RNE-01", "002010", + "rv32i_m/F/FMSUB-S-RTZ-01", "002010", + "rv32i_m/F/FMSUB-S-RUP-01", "002010", + "rv32i_m/F/FMUL-S-DYN-RDN-01", "002010", + "rv32i_m/F/FMUL-S-DYN-RMM-01", "002010", + "rv32i_m/F/FMUL-S-DYN-RNE-01", "002010", + "rv32i_m/F/FMUL-S-DYN-RTZ-01", "002010", + "rv32i_m/F/FMUL-S-DYN-RUP-01", "002010", + "rv32i_m/F/FMUL-S-RDN-01", "002010", + "rv32i_m/F/FMUL-S-RMM-01", "002010", + "rv32i_m/F/FMUL-S-RNE-01", "002010", + "rv32i_m/F/FMUL-S-RTZ-01", "002010", + "rv32i_m/F/FMUL-S-RUP-01", "002010", + "rv32i_m/F/FMV-W-X-01", "002010", + "rv32i_m/F/FMV-X-W-01", "002010", + "rv32i_m/F/FNMADD-S-DYN-RDN-01", "002010", + "rv32i_m/F/FNMADD-S-DYN-RMM-01", "002010", + "rv32i_m/F/FNMADD-S-DYN-RNE-01", "002010", + "rv32i_m/F/FNMADD-S-DYN-RTZ-01", "002010", + "rv32i_m/F/FNMADD-S-DYN-RUP-01", "002010", + "rv32i_m/F/FNMADD-S-RDN-01", "002010", + "rv32i_m/F/FNMADD-S-RMM-01", "002010", + "rv32i_m/F/FNMADD-S-RNE-01", "002010", + "rv32i_m/F/FNMADD-S-RTZ-01", "002010", + "rv32i_m/F/FNMADD-S-RUP-01", "002010", + "rv32i_m/F/FNMSUB-S-DYN-RDN-01", "002010", + "rv32i_m/F/FNMSUB-S-DYN-RMM-01", "002010", + "rv32i_m/F/FNMSUB-S-DYN-RNE-01", "002010", + "rv32i_m/F/FNMSUB-S-DYN-RTZ-01", "002010", + "rv32i_m/F/FNMSUB-S-DYN-RUP-01", "002010", + "rv32i_m/F/FNMSUB-S-RDN-01", "002010", + "rv32i_m/F/FNMSUB-S-RMM-01", "002010", + "rv32i_m/F/FNMSUB-S-RNE-01", "002010", + "rv32i_m/F/FNMSUB-S-RTZ-01", "002010", + "rv32i_m/F/FNMSUB-S-RUP-01", "002010", + "rv32i_m/F/FSGNJN-S-01", "002010", + "rv32i_m/F/FSGNJ-S-01", "002010", + "rv32i_m/F/FSGNJX-S-01", "002010", + // "rv32i_m/F/FSQRT-S-DYN-RDN-01", "002010", + // "rv32i_m/F/FSQRT-S-DYN-RMM-01", "002010", + // "rv32i_m/F/FSQRT-S-DYN-RNE-01", "002010", + // "rv32i_m/F/FSQRT-S-DYN-RTZ-01", "002010", + // "rv32i_m/F/FSQRT-S-DYN-RUP-01", "002010", + // "rv32i_m/F/FSQRT-S-RDN-01", "002010", + // "rv32i_m/F/FSQRT-S-RMM-01", "002010", + // "rv32i_m/F/FSQRT-S-RNE-01", "002010", + // "rv32i_m/F/FSQRT-S-RTZ-01", "002010", + // "rv32i_m/F/FSQRT-S-RUP-01", "002010", + "rv32i_m/F/FSUB-S-DYN-RDN-01", "002010", + "rv32i_m/F/FSUB-S-DYN-RMM-01", "002010", + "rv32i_m/F/FSUB-S-DYN-RNE-01", "002010", + "rv32i_m/F/FSUB-S-DYN-RTZ-01", "002010", + "rv32i_m/F/FSUB-S-DYN-RUP-01", "002010", + "rv32i_m/F/FSUB-S-RDN-01", "002010", + "rv32i_m/F/FSUB-S-RMM-01", "002010", + "rv32i_m/F/FSUB-S-RNE-01", "002010", + "rv32i_m/F/FSUB-S-RTZ-01", "002010", + "rv32i_m/F/FSUB-S-RUP-01", "002010", + "rv32i_m/F/FSW-01", "002010" }; string imperas64f[] = '{ `IMPERASTEST, - "rv64i_m/F/FADD-S-DYN-RDN-01", "002010", - "rv64i_m/F/FADD-S-DYN-RMM-01", "002010", - "rv64i_m/F/FADD-S-DYN-RNE-01", "002010", - "rv64i_m/F/FADD-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FADD-S-DYN-RUP-01", "002010", - "rv64i_m/F/FADD-S-RDN-01", "002010", - "rv64i_m/F/FADD-S-RMM-01", "002010", - "rv64i_m/F/FADD-S-RNE-01", "002010", - "rv64i_m/F/FADD-S-RTZ-01", "002010", - "rv64i_m/F/FADD-S-RUP-01", "002010", - "rv64i_m/F/FCLASS-S-01", "002010", - "rv64i_m/F/FCVT-L-S-DYN-RDN-01", "002010", - "rv64i_m/F/FCVT-L-S-DYN-RMM-01", "002010", - "rv64i_m/F/FCVT-L-S-DYN-RNE-01", "002010", - "rv64i_m/F/FCVT-L-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FCVT-L-S-DYN-RUP-01", "002010", - "rv64i_m/F/FCVT-L-S-RDN-01", "002010", - "rv64i_m/F/FCVT-L-S-RMM-01", "002010", - "rv64i_m/F/FCVT-L-S-RNE-01", "002010", - "rv64i_m/F/FCVT-L-S-RTZ-01", "002010", - "rv64i_m/F/FCVT-L-S-RUP-01", "002010", - "rv64i_m/F/FCVT-LU-S-DYN-RDN-01", "002010", - "rv64i_m/F/FCVT-LU-S-DYN-RMM-01", "002010", - "rv64i_m/F/FCVT-LU-S-DYN-RNE-01", "002010", - "rv64i_m/F/FCVT-LU-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FCVT-LU-S-DYN-RUP-01", "002010", - "rv64i_m/F/FCVT-LU-S-RDN-01", "002010", - "rv64i_m/F/FCVT-LU-S-RMM-01", "002010", - "rv64i_m/F/FCVT-LU-S-RNE-01", "002010", - "rv64i_m/F/FCVT-LU-S-RTZ-01", "002010", - "rv64i_m/F/FCVT-LU-S-RUP-01", "002010", - "rv64i_m/F/FCVT-S-L-DYN-RDN-01", "002010", - "rv64i_m/F/FCVT-S-L-DYN-RMM-01", "002010", - "rv64i_m/F/FCVT-S-L-DYN-RNE-01", "002010", - "rv64i_m/F/FCVT-S-L-DYN-RTZ-01", "002010", - "rv64i_m/F/FCVT-S-L-DYN-RUP-01", "002010", - "rv64i_m/F/FCVT-S-L-RDN-01", "002010", - "rv64i_m/F/FCVT-S-L-RMM-01", "002010", - "rv64i_m/F/FCVT-S-L-RNE-01", "002010", - "rv64i_m/F/FCVT-S-L-RTZ-01", "002010", - "rv64i_m/F/FCVT-S-L-RUP-01", "002010", - "rv64i_m/F/FCVT-S-LU-DYN-RDN-01", "002010", - "rv64i_m/F/FCVT-S-LU-DYN-RMM-01", "002010", - "rv64i_m/F/FCVT-S-LU-DYN-RNE-01", "002010", - "rv64i_m/F/FCVT-S-LU-DYN-RTZ-01", "002010", - "rv64i_m/F/FCVT-S-LU-DYN-RUP-01", "002010", - "rv64i_m/F/FCVT-S-LU-RDN-01", "002010", - "rv64i_m/F/FCVT-S-LU-RMM-01", "002010", - "rv64i_m/F/FCVT-S-LU-RNE-01", "002010", - "rv64i_m/F/FCVT-S-LU-RTZ-01", "002010", - "rv64i_m/F/FCVT-S-LU-RUP-01", "002010", - "rv64i_m/F/FCVT-S-W-DYN-RDN-01", "002010", - "rv64i_m/F/FCVT-S-W-DYN-RMM-01", "002010", - "rv64i_m/F/FCVT-S-W-DYN-RNE-01", "002010", - "rv64i_m/F/FCVT-S-W-DYN-RTZ-01", "002010", - "rv64i_m/F/FCVT-S-W-DYN-RUP-01", "002010", - "rv64i_m/F/FCVT-S-W-RDN-01", "002010", - "rv64i_m/F/FCVT-S-W-RMM-01", "002010", - "rv64i_m/F/FCVT-S-W-RNE-01", "002010", - "rv64i_m/F/FCVT-S-W-RTZ-01", "002010", - "rv64i_m/F/FCVT-S-W-RUP-01", "002010", - "rv64i_m/F/FCVT-S-WU-DYN-RDN-01", "002010", - "rv64i_m/F/FCVT-S-WU-DYN-RMM-01", "002010", - "rv64i_m/F/FCVT-S-WU-DYN-RNE-01", "002010", - "rv64i_m/F/FCVT-S-WU-DYN-RTZ-01", "002010", - "rv64i_m/F/FCVT-S-WU-DYN-RUP-01", "002010", - "rv64i_m/F/FCVT-S-WU-RDN-01", "002010", - "rv64i_m/F/FCVT-S-WU-RMM-01", "002010", - "rv64i_m/F/FCVT-S-WU-RNE-01", "002010", - "rv64i_m/F/FCVT-S-WU-RTZ-01", "002010", - "rv64i_m/F/FCVT-S-WU-RUP-01", "002010", - "rv64i_m/F/FCVT-W-S-DYN-RDN-01", "002010", - "rv64i_m/F/FCVT-W-S-DYN-RMM-01", "002010", - "rv64i_m/F/FCVT-W-S-DYN-RNE-01", "002010", - "rv64i_m/F/FCVT-W-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FCVT-W-S-DYN-RUP-01", "002010", - "rv64i_m/F/FCVT-W-S-RDN-01", "002010", - "rv64i_m/F/FCVT-W-S-RMM-01", "002010", - "rv64i_m/F/FCVT-W-S-RNE-01", "002010", - "rv64i_m/F/FCVT-W-S-RTZ-01", "002010", - "rv64i_m/F/FCVT-W-S-RUP-01", "002010", - "rv64i_m/F/FCVT-WU-S-DYN-RDN-01", "002010", - "rv64i_m/F/FCVT-WU-S-DYN-RMM-01", "002010", - "rv64i_m/F/FCVT-WU-S-DYN-RNE-01", "002010", - "rv64i_m/F/FCVT-WU-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FCVT-WU-S-DYN-RUP-01", "002010", - "rv64i_m/F/FCVT-WU-S-RDN-01", "002010", - "rv64i_m/F/FCVT-WU-S-RMM-01", "002010", - "rv64i_m/F/FCVT-WU-S-RNE-01", "002010", - "rv64i_m/F/FCVT-WU-S-RTZ-01", "002010", - "rv64i_m/F/FCVT-WU-S-RUP-01", "002010", - // "rv64i_m/F/FDIV-S-DYN-RDN-01", "002010", - // "rv64i_m/F/FDIV-S-DYN-RMM-01", "002010", - // "rv64i_m/F/FDIV-S-DYN-RNE-01", "002010", - // "rv64i_m/F/FDIV-S-DYN-RTZ-01", "002010", - // "rv64i_m/F/FDIV-S-DYN-RUP-01", "002010", - // "rv64i_m/F/FDIV-S-RDN-01", "002010", - // "rv64i_m/F/FDIV-S-RMM-01", "002010", - // "rv64i_m/F/FDIV-S-RNE-01", "002010", - // "rv64i_m/F/FDIV-S-RTZ-01", "002010", - // "rv64i_m/F/FDIV-S-RUP-01", "002010", - "rv64i_m/F/FEQ-S-01", "002010", - "rv64i_m/F/FLE-S-01", "002010", - "rv64i_m/F/FLT-S-01", "002010", - "rv64i_m/F/FLW-01", "002210", - "rv64i_m/F/FMADD-S-DYN-RDN-01", "002010", - "rv64i_m/F/FMADD-S-DYN-RMM-01", "002010", - "rv64i_m/F/FMADD-S-DYN-RNE-01", "002010", - "rv64i_m/F/FMADD-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FMADD-S-DYN-RUP-01", "002010", - "rv64i_m/F/FMADD-S-RDN-01", "002010", - "rv64i_m/F/FMADD-S-RMM-01", "002010", - "rv64i_m/F/FMADD-S-RNE-01", "002010", - "rv64i_m/F/FMADD-S-RTZ-01", "002010", - "rv64i_m/F/FMADD-S-RUP-01", "002010", - "rv64i_m/F/FMAX-S-01", "002010", - "rv64i_m/F/FMIN-S-01", "002010", - "rv64i_m/F/FMSUB-S-DYN-RDN-01", "002010", - "rv64i_m/F/FMSUB-S-DYN-RMM-01", "002010", - "rv64i_m/F/FMSUB-S-DYN-RNE-01", "002010", - "rv64i_m/F/FMSUB-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FMSUB-S-DYN-RUP-01", "002010", - "rv64i_m/F/FMSUB-S-RDN-01", "002010", - "rv64i_m/F/FMSUB-S-RMM-01", "002010", - "rv64i_m/F/FMSUB-S-RNE-01", "002010", - "rv64i_m/F/FMSUB-S-RTZ-01", "002010", - "rv64i_m/F/FMSUB-S-RUP-01", "002010", - "rv64i_m/F/FMUL-S-DYN-RDN-01", "002010", - "rv64i_m/F/FMUL-S-DYN-RMM-01", "002010", - "rv64i_m/F/FMUL-S-DYN-RNE-01", "002010", - "rv64i_m/F/FMUL-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FMUL-S-DYN-RUP-01", "002010", - "rv64i_m/F/FMUL-S-RDN-01", "002010", - "rv64i_m/F/FMUL-S-RMM-01", "002010", - "rv64i_m/F/FMUL-S-RNE-01", "002010", - "rv64i_m/F/FMUL-S-RTZ-01", "002010", - "rv64i_m/F/FMUL-S-RUP-01", "002010", - "rv64i_m/F/FMV-W-X-01", "002010", - "rv64i_m/F/FMV-X-W-01", "002010", - "rv64i_m/F/FNMADD-S-DYN-RDN-01", "002010", - "rv64i_m/F/FNMADD-S-DYN-RMM-01", "002010", - "rv64i_m/F/FNMADD-S-DYN-RNE-01", "002010", - "rv64i_m/F/FNMADD-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FNMADD-S-DYN-RUP-01", "002010", - "rv64i_m/F/FNMADD-S-RDN-01", "002010", - "rv64i_m/F/FNMADD-S-RMM-01", "002010", - "rv64i_m/F/FNMADD-S-RNE-01", "002010", - "rv64i_m/F/FNMADD-S-RTZ-01", "002010", - "rv64i_m/F/FNMADD-S-RUP-01", "002010", - "rv64i_m/F/FNMSUB-S-DYN-RDN-01", "002010", - "rv64i_m/F/FNMSUB-S-DYN-RMM-01", "002010", - "rv64i_m/F/FNMSUB-S-DYN-RNE-01", "002010", - "rv64i_m/F/FNMSUB-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FNMSUB-S-DYN-RUP-01", "002010", - "rv64i_m/F/FNMSUB-S-RDN-01", "002010", - "rv64i_m/F/FNMSUB-S-RMM-01", "002010", - "rv64i_m/F/FNMSUB-S-RNE-01", "002010", - "rv64i_m/F/FNMSUB-S-RTZ-01", "002010", - "rv64i_m/F/FNMSUB-S-RUP-01", "002010", - "rv64i_m/F/FSGNJN-S-01", "002010", - "rv64i_m/F/FSGNJ-S-01", "002010", - "rv64i_m/F/FSGNJX-S-01", "002010", - // "rv64i_m/F/FSQRT-S-DYN-RDN-01", "002010", - // "rv64i_m/F/FSQRT-S-DYN-RMM-01", "002010", - // "rv64i_m/F/FSQRT-S-DYN-RNE-01", "002010", - // "rv64i_m/F/FSQRT-S-DYN-RTZ-01", "002010", - // "rv64i_m/F/FSQRT-S-DYN-RUP-01", "002010", - // "rv64i_m/F/FSQRT-S-RDN-01", "002010", - // "rv64i_m/F/FSQRT-S-RMM-01", "002010", - // "rv64i_m/F/FSQRT-S-RNE-01", "002010", - // "rv64i_m/F/FSQRT-S-RTZ-01", "002010", - // "rv64i_m/F/FSQRT-S-RUP-01", "002010", - "rv64i_m/F/FSUB-S-DYN-RDN-01", "002010", - "rv64i_m/F/FSUB-S-DYN-RMM-01", "002010", - "rv64i_m/F/FSUB-S-DYN-RNE-01", "002010", - "rv64i_m/F/FSUB-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FSUB-S-DYN-RUP-01", "002010", - "rv64i_m/F/FSUB-S-RDN-01", "002010", - "rv64i_m/F/FSUB-S-RMM-01", "002010", - "rv64i_m/F/FSUB-S-RNE-01", "002010", - "rv64i_m/F/FSUB-S-RTZ-01", "002010", - "rv64i_m/F/FSUB-S-RUP-01", "002010", - "rv64i_m/F/FSW-01", "002010" + "rv64i_m/F/FADD-S-DYN-RDN-01", "002010", + "rv64i_m/F/FADD-S-DYN-RMM-01", "002010", + "rv64i_m/F/FADD-S-DYN-RNE-01", "002010", + "rv64i_m/F/FADD-S-DYN-RTZ-01", "002010", + "rv64i_m/F/FADD-S-DYN-RUP-01", "002010", + "rv64i_m/F/FADD-S-RDN-01", "002010", + "rv64i_m/F/FADD-S-RMM-01", "002010", + "rv64i_m/F/FADD-S-RNE-01", "002010", + "rv64i_m/F/FADD-S-RTZ-01", "002010", + "rv64i_m/F/FADD-S-RUP-01", "002010", + "rv64i_m/F/FCLASS-S-01", "002010", + "rv64i_m/F/FCVT-L-S-DYN-RDN-01", "002010", + "rv64i_m/F/FCVT-L-S-DYN-RMM-01", "002010", + "rv64i_m/F/FCVT-L-S-DYN-RNE-01", "002010", + "rv64i_m/F/FCVT-L-S-DYN-RTZ-01", "002010", + "rv64i_m/F/FCVT-L-S-DYN-RUP-01", "002010", + "rv64i_m/F/FCVT-L-S-RDN-01", "002010", + "rv64i_m/F/FCVT-L-S-RMM-01", "002010", + "rv64i_m/F/FCVT-L-S-RNE-01", "002010", + "rv64i_m/F/FCVT-L-S-RTZ-01", "002010", + "rv64i_m/F/FCVT-L-S-RUP-01", "002010", + "rv64i_m/F/FCVT-LU-S-DYN-RDN-01", "002010", + "rv64i_m/F/FCVT-LU-S-DYN-RMM-01", "002010", + "rv64i_m/F/FCVT-LU-S-DYN-RNE-01", "002010", + "rv64i_m/F/FCVT-LU-S-DYN-RTZ-01", "002010", + "rv64i_m/F/FCVT-LU-S-DYN-RUP-01", "002010", + "rv64i_m/F/FCVT-LU-S-RDN-01", "002010", + "rv64i_m/F/FCVT-LU-S-RMM-01", "002010", + "rv64i_m/F/FCVT-LU-S-RNE-01", "002010", + "rv64i_m/F/FCVT-LU-S-RTZ-01", "002010", + "rv64i_m/F/FCVT-LU-S-RUP-01", "002010", + "rv64i_m/F/FCVT-S-L-DYN-RDN-01", "002010", + "rv64i_m/F/FCVT-S-L-DYN-RMM-01", "002010", + "rv64i_m/F/FCVT-S-L-DYN-RNE-01", "002010", + "rv64i_m/F/FCVT-S-L-DYN-RTZ-01", "002010", + "rv64i_m/F/FCVT-S-L-DYN-RUP-01", "002010", + "rv64i_m/F/FCVT-S-L-RDN-01", "002010", + "rv64i_m/F/FCVT-S-L-RMM-01", "002010", + "rv64i_m/F/FCVT-S-L-RNE-01", "002010", + "rv64i_m/F/FCVT-S-L-RTZ-01", "002010", + "rv64i_m/F/FCVT-S-L-RUP-01", "002010", + "rv64i_m/F/FCVT-S-LU-DYN-RDN-01", "002010", + "rv64i_m/F/FCVT-S-LU-DYN-RMM-01", "002010", + "rv64i_m/F/FCVT-S-LU-DYN-RNE-01", "002010", + "rv64i_m/F/FCVT-S-LU-DYN-RTZ-01", "002010", + "rv64i_m/F/FCVT-S-LU-DYN-RUP-01", "002010", + "rv64i_m/F/FCVT-S-LU-RDN-01", "002010", + "rv64i_m/F/FCVT-S-LU-RMM-01", "002010", + "rv64i_m/F/FCVT-S-LU-RNE-01", "002010", + "rv64i_m/F/FCVT-S-LU-RTZ-01", "002010", + "rv64i_m/F/FCVT-S-LU-RUP-01", "002010", + "rv64i_m/F/FCVT-S-W-DYN-RDN-01", "002010", + "rv64i_m/F/FCVT-S-W-DYN-RMM-01", "002010", + "rv64i_m/F/FCVT-S-W-DYN-RNE-01", "002010", + "rv64i_m/F/FCVT-S-W-DYN-RTZ-01", "002010", + "rv64i_m/F/FCVT-S-W-DYN-RUP-01", "002010", + "rv64i_m/F/FCVT-S-W-RDN-01", "002010", + "rv64i_m/F/FCVT-S-W-RMM-01", "002010", + "rv64i_m/F/FCVT-S-W-RNE-01", "002010", + "rv64i_m/F/FCVT-S-W-RTZ-01", "002010", + "rv64i_m/F/FCVT-S-W-RUP-01", "002010", + "rv64i_m/F/FCVT-S-WU-DYN-RDN-01", "002010", + "rv64i_m/F/FCVT-S-WU-DYN-RMM-01", "002010", + "rv64i_m/F/FCVT-S-WU-DYN-RNE-01", "002010", + "rv64i_m/F/FCVT-S-WU-DYN-RTZ-01", "002010", + "rv64i_m/F/FCVT-S-WU-DYN-RUP-01", "002010", + "rv64i_m/F/FCVT-S-WU-RDN-01", "002010", + "rv64i_m/F/FCVT-S-WU-RMM-01", "002010", + "rv64i_m/F/FCVT-S-WU-RNE-01", "002010", + "rv64i_m/F/FCVT-S-WU-RTZ-01", "002010", + "rv64i_m/F/FCVT-S-WU-RUP-01", "002010", + "rv64i_m/F/FCVT-W-S-DYN-RDN-01", "002010", + "rv64i_m/F/FCVT-W-S-DYN-RMM-01", "002010", + "rv64i_m/F/FCVT-W-S-DYN-RNE-01", "002010", + "rv64i_m/F/FCVT-W-S-DYN-RTZ-01", "002010", + "rv64i_m/F/FCVT-W-S-DYN-RUP-01", "002010", + "rv64i_m/F/FCVT-W-S-RDN-01", "002010", + "rv64i_m/F/FCVT-W-S-RMM-01", "002010", + "rv64i_m/F/FCVT-W-S-RNE-01", "002010", + "rv64i_m/F/FCVT-W-S-RTZ-01", "002010", + "rv64i_m/F/FCVT-W-S-RUP-01", "002010", + "rv64i_m/F/FCVT-WU-S-DYN-RDN-01", "002010", + "rv64i_m/F/FCVT-WU-S-DYN-RMM-01", "002010", + "rv64i_m/F/FCVT-WU-S-DYN-RNE-01", "002010", + "rv64i_m/F/FCVT-WU-S-DYN-RTZ-01", "002010", + "rv64i_m/F/FCVT-WU-S-DYN-RUP-01", "002010", + "rv64i_m/F/FCVT-WU-S-RDN-01", "002010", + "rv64i_m/F/FCVT-WU-S-RMM-01", "002010", + "rv64i_m/F/FCVT-WU-S-RNE-01", "002010", + "rv64i_m/F/FCVT-WU-S-RTZ-01", "002010", + "rv64i_m/F/FCVT-WU-S-RUP-01", "002010", + // "rv64i_m/F/FDIV-S-DYN-RDN-01", "002010", + // "rv64i_m/F/FDIV-S-DYN-RMM-01", "002010", + // "rv64i_m/F/FDIV-S-DYN-RNE-01", "002010", + // "rv64i_m/F/FDIV-S-DYN-RTZ-01", "002010", + // "rv64i_m/F/FDIV-S-DYN-RUP-01", "002010", + // "rv64i_m/F/FDIV-S-RDN-01", "002010", + // "rv64i_m/F/FDIV-S-RMM-01", "002010", + // "rv64i_m/F/FDIV-S-RNE-01", "002010", + // "rv64i_m/F/FDIV-S-RTZ-01", "002010", + // "rv64i_m/F/FDIV-S-RUP-01", "002010", + "rv64i_m/F/FEQ-S-01", "002010", + "rv64i_m/F/FLE-S-01", "002010", + "rv64i_m/F/FLT-S-01", "002010", + "rv64i_m/F/FLW-01", "002210", + "rv64i_m/F/FMADD-S-DYN-RDN-01", "002010", + "rv64i_m/F/FMADD-S-DYN-RMM-01", "002010", + "rv64i_m/F/FMADD-S-DYN-RNE-01", "002010", + "rv64i_m/F/FMADD-S-DYN-RTZ-01", "002010", + "rv64i_m/F/FMADD-S-DYN-RUP-01", "002010", + "rv64i_m/F/FMADD-S-RDN-01", "002010", + "rv64i_m/F/FMADD-S-RMM-01", "002010", + "rv64i_m/F/FMADD-S-RNE-01", "002010", + "rv64i_m/F/FMADD-S-RTZ-01", "002010", + "rv64i_m/F/FMADD-S-RUP-01", "002010", + "rv64i_m/F/FMAX-S-01", "002010", + "rv64i_m/F/FMIN-S-01", "002010", + "rv64i_m/F/FMSUB-S-DYN-RDN-01", "002010", + "rv64i_m/F/FMSUB-S-DYN-RMM-01", "002010", + "rv64i_m/F/FMSUB-S-DYN-RNE-01", "002010", + "rv64i_m/F/FMSUB-S-DYN-RTZ-01", "002010", + "rv64i_m/F/FMSUB-S-DYN-RUP-01", "002010", + "rv64i_m/F/FMSUB-S-RDN-01", "002010", + "rv64i_m/F/FMSUB-S-RMM-01", "002010", + "rv64i_m/F/FMSUB-S-RNE-01", "002010", + "rv64i_m/F/FMSUB-S-RTZ-01", "002010", + "rv64i_m/F/FMSUB-S-RUP-01", "002010", + "rv64i_m/F/FMUL-S-DYN-RDN-01", "002010", + "rv64i_m/F/FMUL-S-DYN-RMM-01", "002010", + "rv64i_m/F/FMUL-S-DYN-RNE-01", "002010", + "rv64i_m/F/FMUL-S-DYN-RTZ-01", "002010", + "rv64i_m/F/FMUL-S-DYN-RUP-01", "002010", + "rv64i_m/F/FMUL-S-RDN-01", "002010", + "rv64i_m/F/FMUL-S-RMM-01", "002010", + "rv64i_m/F/FMUL-S-RNE-01", "002010", + "rv64i_m/F/FMUL-S-RTZ-01", "002010", + "rv64i_m/F/FMUL-S-RUP-01", "002010", + "rv64i_m/F/FMV-W-X-01", "002010", + "rv64i_m/F/FMV-X-W-01", "002010", + "rv64i_m/F/FNMADD-S-DYN-RDN-01", "002010", + "rv64i_m/F/FNMADD-S-DYN-RMM-01", "002010", + "rv64i_m/F/FNMADD-S-DYN-RNE-01", "002010", + "rv64i_m/F/FNMADD-S-DYN-RTZ-01", "002010", + "rv64i_m/F/FNMADD-S-DYN-RUP-01", "002010", + "rv64i_m/F/FNMADD-S-RDN-01", "002010", + "rv64i_m/F/FNMADD-S-RMM-01", "002010", + "rv64i_m/F/FNMADD-S-RNE-01", "002010", + "rv64i_m/F/FNMADD-S-RTZ-01", "002010", + "rv64i_m/F/FNMADD-S-RUP-01", "002010", + "rv64i_m/F/FNMSUB-S-DYN-RDN-01", "002010", + "rv64i_m/F/FNMSUB-S-DYN-RMM-01", "002010", + "rv64i_m/F/FNMSUB-S-DYN-RNE-01", "002010", + "rv64i_m/F/FNMSUB-S-DYN-RTZ-01", "002010", + "rv64i_m/F/FNMSUB-S-DYN-RUP-01", "002010", + "rv64i_m/F/FNMSUB-S-RDN-01", "002010", + "rv64i_m/F/FNMSUB-S-RMM-01", "002010", + "rv64i_m/F/FNMSUB-S-RNE-01", "002010", + "rv64i_m/F/FNMSUB-S-RTZ-01", "002010", + "rv64i_m/F/FNMSUB-S-RUP-01", "002010", + "rv64i_m/F/FSGNJN-S-01", "002010", + "rv64i_m/F/FSGNJ-S-01", "002010", + "rv64i_m/F/FSGNJX-S-01", "002010", + // "rv64i_m/F/FSQRT-S-DYN-RDN-01", "002010", + // "rv64i_m/F/FSQRT-S-DYN-RMM-01", "002010", + // "rv64i_m/F/FSQRT-S-DYN-RNE-01", "002010", + // "rv64i_m/F/FSQRT-S-DYN-RTZ-01", "002010", + // "rv64i_m/F/FSQRT-S-DYN-RUP-01", "002010", + // "rv64i_m/F/FSQRT-S-RDN-01", "002010", + // "rv64i_m/F/FSQRT-S-RMM-01", "002010", + // "rv64i_m/F/FSQRT-S-RNE-01", "002010", + // "rv64i_m/F/FSQRT-S-RTZ-01", "002010", + // "rv64i_m/F/FSQRT-S-RUP-01", "002010", + "rv64i_m/F/FSUB-S-DYN-RDN-01", "002010", + "rv64i_m/F/FSUB-S-DYN-RMM-01", "002010", + "rv64i_m/F/FSUB-S-DYN-RNE-01", "002010", + "rv64i_m/F/FSUB-S-DYN-RTZ-01", "002010", + "rv64i_m/F/FSUB-S-DYN-RUP-01", "002010", + "rv64i_m/F/FSUB-S-RDN-01", "002010", + "rv64i_m/F/FSUB-S-RMM-01", "002010", + "rv64i_m/F/FSUB-S-RNE-01", "002010", + "rv64i_m/F/FSUB-S-RTZ-01", "002010", + "rv64i_m/F/FSUB-S-RUP-01", "002010", + "rv64i_m/F/FSW-01", "002010" }; string imperas64d[] = '{ `IMPERASTEST, - "rv64i_m/D/FADD-D-DYN-RDN-01", "002010", - "rv64i_m/D/FADD-D-DYN-RMM-01", "002010", - "rv64i_m/D/FADD-D-DYN-RNE-01", "002010", - "rv64i_m/D/FADD-D-DYN-RTZ-01", "002010", - "rv64i_m/D/FADD-D-DYN-RUP-01", "002010", - "rv64i_m/D/FADD-D-RDN-01", "002010", - "rv64i_m/D/FADD-D-RMM-01", "002010", - "rv64i_m/D/FADD-D-RNE-01", "002010", - "rv64i_m/D/FADD-D-RTZ-01", "002010", - "rv64i_m/D/FADD-D-RUP-01", "002010", - "rv64i_m/D/FCLASS-D-01", "002010", - "rv64i_m/D/FCVT-D-L-DYN-RDN-01", "002010", - "rv64i_m/D/FCVT-D-L-DYN-RMM-01", "002010", - "rv64i_m/D/FCVT-D-L-DYN-RNE-01", "002010", - "rv64i_m/D/FCVT-D-L-DYN-RTZ-01", "002010", - "rv64i_m/D/FCVT-D-L-DYN-RUP-01", "002010", - "rv64i_m/D/FCVT-D-L-RDN-01", "002010", - "rv64i_m/D/FCVT-D-L-RMM-01", "002010", - "rv64i_m/D/FCVT-D-L-RNE-01", "002010", - "rv64i_m/D/FCVT-D-L-RTZ-01", "002010", - "rv64i_m/D/FCVT-D-L-RUP-01", "002010", - "rv64i_m/D/FCVT-D-LU-DYN-RDN-01", "002010", - "rv64i_m/D/FCVT-D-LU-DYN-RMM-01", "002010", - "rv64i_m/D/FCVT-D-LU-DYN-RNE-01", "002010", - "rv64i_m/D/FCVT-D-LU-DYN-RTZ-01", "002010", - "rv64i_m/D/FCVT-D-LU-DYN-RUP-01", "002010", - "rv64i_m/D/FCVT-D-LU-RDN-01", "002010", - "rv64i_m/D/FCVT-D-LU-RMM-01", "002010", - "rv64i_m/D/FCVT-D-LU-RNE-01", "002010", - "rv64i_m/D/FCVT-D-LU-RTZ-01", "002010", - "rv64i_m/D/FCVT-D-LU-RUP-01", "002010", - "rv64i_m/D/FCVT-D-S-01", "002010", - "rv64i_m/D/FCVT-D-W-01", "002010", - "rv64i_m/D/FCVT-D-WU-01", "002010", - "rv64i_m/D/FCVT-L-D-DYN-RDN-01", "002010", - "rv64i_m/D/FCVT-L-D-DYN-RMM-01", "002010", - "rv64i_m/D/FCVT-L-D-DYN-RNE-01", "002010", - "rv64i_m/D/FCVT-L-D-DYN-RTZ-01", "002010", - "rv64i_m/D/FCVT-L-D-DYN-RUP-01", "002010", - "rv64i_m/D/FCVT-L-D-RDN-01", "002010", - "rv64i_m/D/FCVT-L-D-RMM-01", "002010", - "rv64i_m/D/FCVT-L-D-RNE-01", "002010", - "rv64i_m/D/FCVT-L-D-RTZ-01", "002010", - "rv64i_m/D/FCVT-L-D-RUP-01", "002010", - "rv64i_m/D/FCVT-LU-D-DYN-RDN-01", "002010", - "rv64i_m/D/FCVT-LU-D-DYN-RMM-01", "002010", - "rv64i_m/D/FCVT-LU-D-DYN-RNE-01", "002010", - "rv64i_m/D/FCVT-LU-D-DYN-RTZ-01", "002010", - "rv64i_m/D/FCVT-LU-D-DYN-RUP-01", "002010", - "rv64i_m/D/FCVT-LU-D-RDN-01", "002010", - "rv64i_m/D/FCVT-LU-D-RMM-01", "002010", - "rv64i_m/D/FCVT-LU-D-RNE-01", "002010", - "rv64i_m/D/FCVT-LU-D-RTZ-01", "002010", - "rv64i_m/D/FCVT-LU-D-RUP-01", "002010", - "rv64i_m/D/FCVT-S-D-DYN-RDN-01", "002010", - "rv64i_m/D/FCVT-S-D-DYN-RMM-01", "002010", - "rv64i_m/D/FCVT-S-D-DYN-RNE-01", "002010", - "rv64i_m/D/FCVT-S-D-DYN-RTZ-01", "002010", - "rv64i_m/D/FCVT-S-D-DYN-RUP-01", "002010", - "rv64i_m/D/FCVT-S-D-RDN-01", "002010", - "rv64i_m/D/FCVT-S-D-RMM-01", "002010", - "rv64i_m/D/FCVT-S-D-RNE-01", "002010", - "rv64i_m/D/FCVT-S-D-RTZ-01", "002010", - "rv64i_m/D/FCVT-S-D-RUP-01", "002010", - "rv64i_m/D/FCVT-W-D-DYN-RDN-01", "002010", - "rv64i_m/D/FCVT-W-D-DYN-RMM-01", "002010", - "rv64i_m/D/FCVT-W-D-DYN-RNE-01", "002010", - "rv64i_m/D/FCVT-W-D-DYN-RTZ-01", "002010", - "rv64i_m/D/FCVT-W-D-DYN-RUP-01", "002010", - "rv64i_m/D/FCVT-W-D-RDN-01", "002010", - "rv64i_m/D/FCVT-W-D-RMM-01", "002010", - "rv64i_m/D/FCVT-W-D-RNE-01", "002010", - "rv64i_m/D/FCVT-W-D-RTZ-01", "002010", - "rv64i_m/D/FCVT-W-D-RUP-01", "002010", - "rv64i_m/D/FCVT-WU-D-DYN-RDN-01", "002010", - "rv64i_m/D/FCVT-WU-D-DYN-RMM-01", "002010", - "rv64i_m/D/FCVT-WU-D-DYN-RNE-01", "002010", - "rv64i_m/D/FCVT-WU-D-DYN-RTZ-01", "002010", - "rv64i_m/D/FCVT-WU-D-DYN-RUP-01", "002010", - "rv64i_m/D/FCVT-WU-D-RDN-01", "002010", - "rv64i_m/D/FCVT-WU-D-RMM-01", "002010", - "rv64i_m/D/FCVT-WU-D-RNE-01", "002010", - "rv64i_m/D/FCVT-WU-D-RTZ-01", "002010", - "rv64i_m/D/FCVT-WU-D-RUP-01", "002010", - // "rv64i_m/D/FDIV-D-DYN-RDN-01", "002010", - // "rv64i_m/D/FDIV-D-DYN-RMM-01", "002010", - // "rv64i_m/D/FDIV-D-DYN-RNE-01", "002010", - // "rv64i_m/D/FDIV-D-DYN-RTZ-01", "002010", - // "rv64i_m/D/FDIV-D-DYN-RUP-01", "002010", - // "rv64i_m/D/FDIV-D-RDN-01", "002010", - // "rv64i_m/D/FDIV-D-RMM-01", "002010", - // "rv64i_m/D/FDIV-D-RNE-01", "002010", - // "rv64i_m/D/FDIV-D-RTZ-01", "002010", - // "rv64i_m/D/FDIV-D-RUP-01", "002010", - "rv64i_m/D/FEQ-D-01", "002010", - "rv64i_m/D/FLD-01", "002520", - "rv64i_m/D/FLE-D-01", "002010", - "rv64i_m/D/FLT-D-01", "002010", - "rv64i_m/D/FMADD-D-DYN-RDN-01", "003010", - "rv64i_m/D/FMADD-D-DYN-RMM-01", "003010", - "rv64i_m/D/FMADD-D-DYN-RNE-01", "003010", - "rv64i_m/D/FMADD-D-DYN-RTZ-01", "003010", - "rv64i_m/D/FMADD-D-DYN-RUP-01", "003010", - "rv64i_m/D/FMADD-D-RDN-01", "003010", - "rv64i_m/D/FMADD-D-RMM-01", "003010", - "rv64i_m/D/FMADD-D-RNE-01", "003010", - "rv64i_m/D/FMADD-D-RTZ-01", "003010", - "rv64i_m/D/FMADD-D-RUP-01", "003010", - "rv64i_m/D/FMAX-D-01", "002010", - "rv64i_m/D/FMIN-D-01", "002010", - "rv64i_m/D/FMSUB-D-DYN-RDN-01", "003010", - "rv64i_m/D/FMSUB-D-DYN-RMM-01", "003010", - "rv64i_m/D/FMSUB-D-DYN-RNE-01", "003010", - "rv64i_m/D/FMSUB-D-DYN-RTZ-01", "003010", - "rv64i_m/D/FMSUB-D-DYN-RUP-01", "003010", - "rv64i_m/D/FMSUB-D-RDN-01", "003010", - "rv64i_m/D/FMSUB-D-RMM-01", "003010", - "rv64i_m/D/FMSUB-D-RNE-01", "003010", - "rv64i_m/D/FMSUB-D-RTZ-01", "003010", - "rv64i_m/D/FMSUB-D-RUP-01", "003010", - "rv64i_m/D/FMUL-D-DYN-RDN-01", "002010", - "rv64i_m/D/FMUL-D-DYN-RMM-01", "002010", - "rv64i_m/D/FMUL-D-DYN-RNE-01", "002010", - "rv64i_m/D/FMUL-D-DYN-RTZ-01", "002010", - "rv64i_m/D/FMUL-D-DYN-RUP-01", "002010", - "rv64i_m/D/FMUL-D-RDN-01", "002010", - "rv64i_m/D/FMUL-D-RMM-01", "002010", - "rv64i_m/D/FMUL-D-RNE-01", "002010", - "rv64i_m/D/FMUL-D-RTZ-01", "002010", - "rv64i_m/D/FMUL-D-RUP-01", "002010", - "rv64i_m/D/FMV-D-X-01", "002010", - "rv64i_m/D/FMV-X-D-01", "002010", - "rv64i_m/D/FNMADD-D-DYN-RDN-01", "003010", - "rv64i_m/D/FNMADD-D-DYN-RMM-01", "003010", - "rv64i_m/D/FNMADD-D-DYN-RNE-01", "003010", - "rv64i_m/D/FNMADD-D-DYN-RTZ-01", "003010", - "rv64i_m/D/FNMADD-D-DYN-RUP-01", "003010", - "rv64i_m/D/FNMADD-D-RDN-01", "003010", - "rv64i_m/D/FNMADD-D-RMM-01", "003010", - "rv64i_m/D/FNMADD-D-RNE-01", "003010", - "rv64i_m/D/FNMADD-D-RTZ-01", "003010", - "rv64i_m/D/FNMADD-D-RUP-01", "003010", - "rv64i_m/D/FNMSUB-D-DYN-RDN-01", "003010", - "rv64i_m/D/FNMSUB-D-DYN-RMM-01", "003010", - "rv64i_m/D/FNMSUB-D-DYN-RNE-01", "003010", - "rv64i_m/D/FNMSUB-D-DYN-RTZ-01", "003010", - "rv64i_m/D/FNMSUB-D-DYN-RUP-01", "003010", - "rv64i_m/D/FNMSUB-D-RDN-01", "003010", - "rv64i_m/D/FNMSUB-D-RMM-01", "003010", - "rv64i_m/D/FNMSUB-D-RNE-01", "003010", - "rv64i_m/D/FNMSUB-D-RTZ-01", "003010", - "rv64i_m/D/FNMSUB-D-RUP-01", "003010", - "rv64i_m/D/FSD-01", "002010", - "rv64i_m/D/FSGNJ-D-01", "002010", - "rv64i_m/D/FSGNJN-D-01", "002010", - "rv64i_m/D/FSGNJX-D-01", "002010", - // "rv64i_m/D/FSQRT-D-DYN-RDN-01", "002010", - // "rv64i_m/D/FSQRT-D-DYN-RMM-01", "002010", - // "rv64i_m/D/FSQRT-D-DYN-RNE-01", "002010", - // "rv64i_m/D/FSQRT-D-DYN-RTZ-01", "002010", - // "rv64i_m/D/FSQRT-D-DYN-RUP-01", "002010", - // "rv64i_m/D/FSQRT-D-RDN-01", "002010", - // "rv64i_m/D/FSQRT-D-RMM-01", "002010", - // "rv64i_m/D/FSQRT-D-RNE-01", "002010", - // "rv64i_m/D/FSQRT-D-RTZ-01", "002010", - // "rv64i_m/D/FSQRT-D-RUP-01", "002010", - "rv64i_m/D/FSUB-D-DYN-RDN-01", "002010", - "rv64i_m/D/FSUB-D-DYN-RMM-01", "002010", - "rv64i_m/D/FSUB-D-DYN-RNE-01", "002010", - "rv64i_m/D/FSUB-D-DYN-RTZ-01", "002010", - "rv64i_m/D/FSUB-D-DYN-RUP-01", "002010", - "rv64i_m/D/FSUB-D-RDN-01", "002010", - "rv64i_m/D/FSUB-D-RMM-01", "002010", - "rv64i_m/D/FSUB-D-RNE-01", "002010", - "rv64i_m/D/FSUB-D-RTZ-01", "002010", - "rv64i_m/D/FSUB-D-RUP-01", "002010" + "rv64i_m/D/FADD-D-DYN-RDN-01", "002010", + "rv64i_m/D/FADD-D-DYN-RMM-01", "002010", + "rv64i_m/D/FADD-D-DYN-RNE-01", "002010", + "rv64i_m/D/FADD-D-DYN-RTZ-01", "002010", + "rv64i_m/D/FADD-D-DYN-RUP-01", "002010", + "rv64i_m/D/FADD-D-RDN-01", "002010", + "rv64i_m/D/FADD-D-RMM-01", "002010", + "rv64i_m/D/FADD-D-RNE-01", "002010", + "rv64i_m/D/FADD-D-RTZ-01", "002010", + "rv64i_m/D/FADD-D-RUP-01", "002010", + "rv64i_m/D/FCLASS-D-01", "002010", + "rv64i_m/D/FCVT-D-L-DYN-RDN-01", "002010", + "rv64i_m/D/FCVT-D-L-DYN-RMM-01", "002010", + "rv64i_m/D/FCVT-D-L-DYN-RNE-01", "002010", + "rv64i_m/D/FCVT-D-L-DYN-RTZ-01", "002010", + "rv64i_m/D/FCVT-D-L-DYN-RUP-01", "002010", + "rv64i_m/D/FCVT-D-L-RDN-01", "002010", + "rv64i_m/D/FCVT-D-L-RMM-01", "002010", + "rv64i_m/D/FCVT-D-L-RNE-01", "002010", + "rv64i_m/D/FCVT-D-L-RTZ-01", "002010", + "rv64i_m/D/FCVT-D-L-RUP-01", "002010", + "rv64i_m/D/FCVT-D-LU-DYN-RDN-01", "002010", + "rv64i_m/D/FCVT-D-LU-DYN-RMM-01", "002010", + "rv64i_m/D/FCVT-D-LU-DYN-RNE-01", "002010", + "rv64i_m/D/FCVT-D-LU-DYN-RTZ-01", "002010", + "rv64i_m/D/FCVT-D-LU-DYN-RUP-01", "002010", + "rv64i_m/D/FCVT-D-LU-RDN-01", "002010", + "rv64i_m/D/FCVT-D-LU-RMM-01", "002010", + "rv64i_m/D/FCVT-D-LU-RNE-01", "002010", + "rv64i_m/D/FCVT-D-LU-RTZ-01", "002010", + "rv64i_m/D/FCVT-D-LU-RUP-01", "002010", + "rv64i_m/D/FCVT-D-S-01", "002010", + "rv64i_m/D/FCVT-D-W-01", "002010", + "rv64i_m/D/FCVT-D-WU-01", "002010", + "rv64i_m/D/FCVT-L-D-DYN-RDN-01", "002010", + "rv64i_m/D/FCVT-L-D-DYN-RMM-01", "002010", + "rv64i_m/D/FCVT-L-D-DYN-RNE-01", "002010", + "rv64i_m/D/FCVT-L-D-DYN-RTZ-01", "002010", + "rv64i_m/D/FCVT-L-D-DYN-RUP-01", "002010", + "rv64i_m/D/FCVT-L-D-RDN-01", "002010", + "rv64i_m/D/FCVT-L-D-RMM-01", "002010", + "rv64i_m/D/FCVT-L-D-RNE-01", "002010", + "rv64i_m/D/FCVT-L-D-RTZ-01", "002010", + "rv64i_m/D/FCVT-L-D-RUP-01", "002010", + "rv64i_m/D/FCVT-LU-D-DYN-RDN-01", "002010", + "rv64i_m/D/FCVT-LU-D-DYN-RMM-01", "002010", + "rv64i_m/D/FCVT-LU-D-DYN-RNE-01", "002010", + "rv64i_m/D/FCVT-LU-D-DYN-RTZ-01", "002010", + "rv64i_m/D/FCVT-LU-D-DYN-RUP-01", "002010", + "rv64i_m/D/FCVT-LU-D-RDN-01", "002010", + "rv64i_m/D/FCVT-LU-D-RMM-01", "002010", + "rv64i_m/D/FCVT-LU-D-RNE-01", "002010", + "rv64i_m/D/FCVT-LU-D-RTZ-01", "002010", + "rv64i_m/D/FCVT-LU-D-RUP-01", "002010", + "rv64i_m/D/FCVT-S-D-DYN-RDN-01", "002010", + "rv64i_m/D/FCVT-S-D-DYN-RMM-01", "002010", + "rv64i_m/D/FCVT-S-D-DYN-RNE-01", "002010", + "rv64i_m/D/FCVT-S-D-DYN-RTZ-01", "002010", + "rv64i_m/D/FCVT-S-D-DYN-RUP-01", "002010", + "rv64i_m/D/FCVT-S-D-RDN-01", "002010", + "rv64i_m/D/FCVT-S-D-RMM-01", "002010", + "rv64i_m/D/FCVT-S-D-RNE-01", "002010", + "rv64i_m/D/FCVT-S-D-RTZ-01", "002010", + "rv64i_m/D/FCVT-S-D-RUP-01", "002010", + "rv64i_m/D/FCVT-W-D-DYN-RDN-01", "002010", + "rv64i_m/D/FCVT-W-D-DYN-RMM-01", "002010", + "rv64i_m/D/FCVT-W-D-DYN-RNE-01", "002010", + "rv64i_m/D/FCVT-W-D-DYN-RTZ-01", "002010", + "rv64i_m/D/FCVT-W-D-DYN-RUP-01", "002010", + "rv64i_m/D/FCVT-W-D-RDN-01", "002010", + "rv64i_m/D/FCVT-W-D-RMM-01", "002010", + "rv64i_m/D/FCVT-W-D-RNE-01", "002010", + "rv64i_m/D/FCVT-W-D-RTZ-01", "002010", + "rv64i_m/D/FCVT-W-D-RUP-01", "002010", + "rv64i_m/D/FCVT-WU-D-DYN-RDN-01", "002010", + "rv64i_m/D/FCVT-WU-D-DYN-RMM-01", "002010", + "rv64i_m/D/FCVT-WU-D-DYN-RNE-01", "002010", + "rv64i_m/D/FCVT-WU-D-DYN-RTZ-01", "002010", + "rv64i_m/D/FCVT-WU-D-DYN-RUP-01", "002010", + "rv64i_m/D/FCVT-WU-D-RDN-01", "002010", + "rv64i_m/D/FCVT-WU-D-RMM-01", "002010", + "rv64i_m/D/FCVT-WU-D-RNE-01", "002010", + "rv64i_m/D/FCVT-WU-D-RTZ-01", "002010", + "rv64i_m/D/FCVT-WU-D-RUP-01", "002010", + // "rv64i_m/D/FDIV-D-DYN-RDN-01", "002010", + // "rv64i_m/D/FDIV-D-DYN-RMM-01", "002010", + // "rv64i_m/D/FDIV-D-DYN-RNE-01", "002010", + // "rv64i_m/D/FDIV-D-DYN-RTZ-01", "002010", + // "rv64i_m/D/FDIV-D-DYN-RUP-01", "002010", + // "rv64i_m/D/FDIV-D-RDN-01", "002010", + // "rv64i_m/D/FDIV-D-RMM-01", "002010", + // "rv64i_m/D/FDIV-D-RNE-01", "002010", + // "rv64i_m/D/FDIV-D-RTZ-01", "002010", + // "rv64i_m/D/FDIV-D-RUP-01", "002010", + "rv64i_m/D/FEQ-D-01", "002010", + "rv64i_m/D/FLD-01", "002520", + "rv64i_m/D/FLE-D-01", "002010", + "rv64i_m/D/FLT-D-01", "002010", + "rv64i_m/D/FMADD-D-DYN-RDN-01", "003010", + "rv64i_m/D/FMADD-D-DYN-RMM-01", "003010", + "rv64i_m/D/FMADD-D-DYN-RNE-01", "003010", + "rv64i_m/D/FMADD-D-DYN-RTZ-01", "003010", + "rv64i_m/D/FMADD-D-DYN-RUP-01", "003010", + "rv64i_m/D/FMADD-D-RDN-01", "003010", + "rv64i_m/D/FMADD-D-RMM-01", "003010", + "rv64i_m/D/FMADD-D-RNE-01", "003010", + "rv64i_m/D/FMADD-D-RTZ-01", "003010", + "rv64i_m/D/FMADD-D-RUP-01", "003010", + "rv64i_m/D/FMAX-D-01", "002010", + "rv64i_m/D/FMIN-D-01", "002010", + "rv64i_m/D/FMSUB-D-DYN-RDN-01", "003010", + "rv64i_m/D/FMSUB-D-DYN-RMM-01", "003010", + "rv64i_m/D/FMSUB-D-DYN-RNE-01", "003010", + "rv64i_m/D/FMSUB-D-DYN-RTZ-01", "003010", + "rv64i_m/D/FMSUB-D-DYN-RUP-01", "003010", + "rv64i_m/D/FMSUB-D-RDN-01", "003010", + "rv64i_m/D/FMSUB-D-RMM-01", "003010", + "rv64i_m/D/FMSUB-D-RNE-01", "003010", + "rv64i_m/D/FMSUB-D-RTZ-01", "003010", + "rv64i_m/D/FMSUB-D-RUP-01", "003010", + "rv64i_m/D/FMUL-D-DYN-RDN-01", "002010", + "rv64i_m/D/FMUL-D-DYN-RMM-01", "002010", + "rv64i_m/D/FMUL-D-DYN-RNE-01", "002010", + "rv64i_m/D/FMUL-D-DYN-RTZ-01", "002010", + "rv64i_m/D/FMUL-D-DYN-RUP-01", "002010", + "rv64i_m/D/FMUL-D-RDN-01", "002010", + "rv64i_m/D/FMUL-D-RMM-01", "002010", + "rv64i_m/D/FMUL-D-RNE-01", "002010", + "rv64i_m/D/FMUL-D-RTZ-01", "002010", + "rv64i_m/D/FMUL-D-RUP-01", "002010", + "rv64i_m/D/FMV-D-X-01", "002010", + "rv64i_m/D/FMV-X-D-01", "002010", + "rv64i_m/D/FNMADD-D-DYN-RDN-01", "003010", + "rv64i_m/D/FNMADD-D-DYN-RMM-01", "003010", + "rv64i_m/D/FNMADD-D-DYN-RNE-01", "003010", + "rv64i_m/D/FNMADD-D-DYN-RTZ-01", "003010", + "rv64i_m/D/FNMADD-D-DYN-RUP-01", "003010", + "rv64i_m/D/FNMADD-D-RDN-01", "003010", + "rv64i_m/D/FNMADD-D-RMM-01", "003010", + "rv64i_m/D/FNMADD-D-RNE-01", "003010", + "rv64i_m/D/FNMADD-D-RTZ-01", "003010", + "rv64i_m/D/FNMADD-D-RUP-01", "003010", + "rv64i_m/D/FNMSUB-D-DYN-RDN-01", "003010", + "rv64i_m/D/FNMSUB-D-DYN-RMM-01", "003010", + "rv64i_m/D/FNMSUB-D-DYN-RNE-01", "003010", + "rv64i_m/D/FNMSUB-D-DYN-RTZ-01", "003010", + "rv64i_m/D/FNMSUB-D-DYN-RUP-01", "003010", + "rv64i_m/D/FNMSUB-D-RDN-01", "003010", + "rv64i_m/D/FNMSUB-D-RMM-01", "003010", + "rv64i_m/D/FNMSUB-D-RNE-01", "003010", + "rv64i_m/D/FNMSUB-D-RTZ-01", "003010", + "rv64i_m/D/FNMSUB-D-RUP-01", "003010", + "rv64i_m/D/FSD-01", "002010", + "rv64i_m/D/FSGNJ-D-01", "002010", + "rv64i_m/D/FSGNJN-D-01", "002010", + "rv64i_m/D/FSGNJX-D-01", "002010", + // "rv64i_m/D/FSQRT-D-DYN-RDN-01", "002010", + // "rv64i_m/D/FSQRT-D-DYN-RMM-01", "002010", + // "rv64i_m/D/FSQRT-D-DYN-RNE-01", "002010", + // "rv64i_m/D/FSQRT-D-DYN-RTZ-01", "002010", + // "rv64i_m/D/FSQRT-D-DYN-RUP-01", "002010", + // "rv64i_m/D/FSQRT-D-RDN-01", "002010", + // "rv64i_m/D/FSQRT-D-RMM-01", "002010", + // "rv64i_m/D/FSQRT-D-RNE-01", "002010", + // "rv64i_m/D/FSQRT-D-RTZ-01", "002010", + // "rv64i_m/D/FSQRT-D-RUP-01", "002010", + "rv64i_m/D/FSUB-D-DYN-RDN-01", "002010", + "rv64i_m/D/FSUB-D-DYN-RMM-01", "002010", + "rv64i_m/D/FSUB-D-DYN-RNE-01", "002010", + "rv64i_m/D/FSUB-D-DYN-RTZ-01", "002010", + "rv64i_m/D/FSUB-D-DYN-RUP-01", "002010", + "rv64i_m/D/FSUB-D-RDN-01", "002010", + "rv64i_m/D/FSUB-D-RMM-01", "002010", + "rv64i_m/D/FSUB-D-RNE-01", "002010", + "rv64i_m/D/FSUB-D-RTZ-01", "002010", + "rv64i_m/D/FSUB-D-RUP-01", "002010" }; string imperas64m[] = '{ `IMPERASTEST, - "rv64i_m/M/DIV-01", "004010", - "rv64i_m/M/DIVU-01", "004010", - "rv64i_m/M/DIVUW-01", "003010", - "rv64i_m/M/DIVW-01", "003010", - "rv64i_m/M/MUL-01", "004010", - "rv64i_m/M/MULH-01", "004010", - "rv64i_m/M/MULHSU-01", "004010", - "rv64i_m/M/MULHU-01", "004010", - "rv64i_m/M/MULW-01", "003010", - "rv64i_m/M/REM-01", "004010", - "rv64i_m/M/REMU-01", "004010", - "rv64i_m/M/REMUW-01", "003010", - "rv64i_m/M/REMW-01", "003010" + "rv64i_m/M/DIV-01", "004010", + "rv64i_m/M/DIVU-01", "004010", + "rv64i_m/M/DIVUW-01", "003010", + "rv64i_m/M/DIVW-01", "003010", + "rv64i_m/M/MUL-01", "004010", + "rv64i_m/M/MULH-01", "004010", + "rv64i_m/M/MULHSU-01", "004010", + "rv64i_m/M/MULHU-01", "004010", + "rv64i_m/M/MULW-01", "003010", + "rv64i_m/M/REM-01", "004010", + "rv64i_m/M/REMU-01", "004010", + "rv64i_m/M/REMUW-01", "003010", + "rv64i_m/M/REMW-01", "003010" }; string imperas64c[] = '{ `IMPERASTEST, - "rv64i_m/C/C-ADD-01", "003010", - "rv64i_m/C/C-ADDI-01", "003010", - "rv64i_m/C/C-ADDI16SP-01", "003010", - "rv64i_m/C/C-ADDI4SPN-01", "003010", - "rv64i_m/C/C-ADDIW-01", "003010", - "rv64i_m/C/C-ADDW-01", "003010", - "rv64i_m/C/C-AND-01", "003010", - "rv64i_m/C/C-ANDI-01", "003010", - "rv64i_m/C/C-BEQZ-01", "004010", - "rv64i_m/C/C-BNEZ-01", "004010", - "rv64i_m/C/C-J-01", "003010", - "rv64i_m/C/C-JALR-01", "004010", - "rv64i_m/C/C-JR-01", "004010", - "rv64i_m/C/C-LD-01", "003520", - "rv64i_m/C/C-LDSP-01", "003520", - "rv64i_m/C/C-LI-01", "003010", - "rv64i_m/C/C-LUI-01", "002010", - "rv64i_m/C/C-LW-01", "003210", - "rv64i_m/C/C-LWSP-01", "003210", - "rv64i_m/C/C-MV-01", "003010", - "rv64i_m/C/C-OR-01", "003010", - "rv64i_m/C/C-SD-01", "003010", - "rv64i_m/C/C-SDSP-01", "003010", - "rv64i_m/C/C-SLLI-01", "003010", - "rv64i_m/C/C-SRAI-01", "003010", - "rv64i_m/C/C-SRLI-01", "003010", - "rv64i_m/C/C-SUB-01", "003010", - "rv64i_m/C/C-SUBW-01", "003010", - "rv64i_m/C/C-SW-01", "003010", - "rv64i_m/C/C-SWSP-01", "003010", - "rv64i_m/C/C-XOR-01", "003010", - "rv64i_m/C/I-C-EBREAK-01", "002000", - "rv64i_m/C/I-C-NOP-01", "002000" + "rv64i_m/C/C-ADD-01", "003010", + "rv64i_m/C/C-ADDI-01", "003010", + "rv64i_m/C/C-ADDI16SP-01", "003010", + "rv64i_m/C/C-ADDI4SPN-01", "003010", + "rv64i_m/C/C-ADDIW-01", "003010", + "rv64i_m/C/C-ADDW-01", "003010", + "rv64i_m/C/C-AND-01", "003010", + "rv64i_m/C/C-ANDI-01", "003010", + "rv64i_m/C/C-BEQZ-01", "004010", + "rv64i_m/C/C-BNEZ-01", "004010", + "rv64i_m/C/C-J-01", "003010", + "rv64i_m/C/C-JALR-01", "004010", + "rv64i_m/C/C-JR-01", "004010", + "rv64i_m/C/C-LD-01", "003520", + "rv64i_m/C/C-LDSP-01", "003520", + "rv64i_m/C/C-LI-01", "003010", + "rv64i_m/C/C-LUI-01", "002010", + "rv64i_m/C/C-LW-01", "003210", + "rv64i_m/C/C-LWSP-01", "003210", + "rv64i_m/C/C-MV-01", "003010", + "rv64i_m/C/C-OR-01", "003010", + "rv64i_m/C/C-SD-01", "003010", + "rv64i_m/C/C-SDSP-01", "003010", + "rv64i_m/C/C-SLLI-01", "003010", + "rv64i_m/C/C-SRAI-01", "003010", + "rv64i_m/C/C-SRLI-01", "003010", + "rv64i_m/C/C-SUB-01", "003010", + "rv64i_m/C/C-SUBW-01", "003010", + "rv64i_m/C/C-SW-01", "003010", + "rv64i_m/C/C-SWSP-01", "003010", + "rv64i_m/C/C-XOR-01", "003010", + "rv64i_m/C/I-C-EBREAK-01", "002000", + "rv64i_m/C/I-C-NOP-01", "002000" }; string imperas64iNOc[] = { `IMPERASTEST, - "rv64i_m/I/I-MISALIGN_JMP-01", "002000" + "rv64i_m/I/I-MISALIGN_JMP-01", "002000" }; string imperas64i[] = '{ `IMPERASTEST, - "rv64i_m/I/I-DELAY_SLOTS-01", "002010", - "rv64i_m/I/ADD-01", "004010", - "rv64i_m/I/ADDI-01", "003010", - "rv64i_m/I/ADDIW-01", "003010", - "rv64i_m/I/ADDW-01", "003010", - "rv64i_m/I/AND-01", "004010", - "rv64i_m/I/ANDI-01", "003010", - "rv64i_m/I/AUIPC-01", "003010", - "rv64i_m/I/BEQ-01", "005010", - "rv64i_m/I/BGE-01", "005010", - "rv64i_m/I/BGEU-01", "005010", - "rv64i_m/I/BLT-01", "005010", - "rv64i_m/I/BLTU-01", "005010", - "rv64i_m/I/BNE-01", "005010", - "rv64i_m/I/I-DELAY_SLOTS-01", "002010", - "rv64i_m/I/I-EBREAK-01", "002010", - "rv64i_m/I/I-ECALL-01", "002010", - "rv64i_m/I/I-ENDIANESS-01", "002010", - "rv64i_m/I/I-IO-01", "002050", -// "rv64i_m/I/I-MISALIGN_JMP-01", "002000", - "rv64i_m/I/I-MISALIGN_LDST-01", "002010", - "rv64i_m/I/I-NOP-01", "002000", - "rv64i_m/I/I-RF_size-01", "002000", - "rv64i_m/I/I-RF_width-01", "002000", - "rv64i_m/I/I-RF_x0-01", "002010", - "rv64i_m/I/JAL-01", "004010", - "rv64i_m/I/JALR-01", "005010", - "rv64i_m/I/LB-01", "004120", - "rv64i_m/I/LBU-01", "004120", - "rv64i_m/I/LD-01", "004520", - "rv64i_m/I/LH-01", "004150", - "rv64i_m/I/LHU-01", "004150", - "rv64i_m/I/LUI-01", "002010", - "rv64i_m/I/LW-01", "004210", - "rv64i_m/I/LWU-01", "004210", - "rv64i_m/I/OR-01", "004010", - "rv64i_m/I/ORI-01", "003010", - "rv64i_m/I/SB-01", "004010", - "rv64i_m/I/SD-01", "004010", - "rv64i_m/I/SH-01", "004010", - "rv64i_m/I/SLL-01", "003010", - "rv64i_m/I/SLLI-01", "003010", - "rv64i_m/I/SLLIW-01", "003010", - "rv64i_m/I/SLLW-01", "003010", - "rv64i_m/I/SLT-01", "004010", - "rv64i_m/I/SLTI-01", "003010", - "rv64i_m/I/SLTIU-01", "003010", - "rv64i_m/I/SLTU-01", "004010", - "rv64i_m/I/SRA-01", "003010", - "rv64i_m/I/SRAI-01", "003010", - "rv64i_m/I/SRAIW-01", "003010", - "rv64i_m/I/SRAW-01", "003010", - "rv64i_m/I/SRL-01", "003010", - "rv64i_m/I/SRLI-01", "003010", - "rv64i_m/I/SRLIW-01", "003010", - "rv64i_m/I/SRLW-01", "003010", - "rv64i_m/I/SUB-01", "004010", - "rv64i_m/I/SUBW-01", "003010", - "rv64i_m/I/SW-01", "004010", - "rv64i_m/I/XOR-01", "004010", - "rv64i_m/I/XORI-01", "003010" + "rv64i_m/I/I-DELAY_SLOTS-01", "002010", + "rv64i_m/I/ADD-01", "004010", + "rv64i_m/I/ADDI-01", "003010", + "rv64i_m/I/ADDIW-01", "003010", + "rv64i_m/I/ADDW-01", "003010", + "rv64i_m/I/AND-01", "004010", + "rv64i_m/I/ANDI-01", "003010", + "rv64i_m/I/AUIPC-01", "003010", + "rv64i_m/I/BEQ-01", "005010", + "rv64i_m/I/BGE-01", "005010", + "rv64i_m/I/BGEU-01", "005010", + "rv64i_m/I/BLT-01", "005010", + "rv64i_m/I/BLTU-01", "005010", + "rv64i_m/I/BNE-01", "005010", + "rv64i_m/I/I-DELAY_SLOTS-01", "002010", + "rv64i_m/I/I-EBREAK-01", "002010", + "rv64i_m/I/I-ECALL-01", "002010", + "rv64i_m/I/I-ENDIANESS-01", "002010", + "rv64i_m/I/I-IO-01", "002050", +// "rv64i_m/I/I-MISALIGN_JMP-01", "002000", + "rv64i_m/I/I-MISALIGN_LDST-01", "002010", + "rv64i_m/I/I-NOP-01", "002000", + "rv64i_m/I/I-RF_size-01", "002000", + "rv64i_m/I/I-RF_width-01", "002000", + "rv64i_m/I/I-RF_x0-01", "002010", + "rv64i_m/I/JAL-01", "004010", + "rv64i_m/I/JALR-01", "005010", + "rv64i_m/I/LB-01", "004120", + "rv64i_m/I/LBU-01", "004120", + "rv64i_m/I/LD-01", "004520", + "rv64i_m/I/LH-01", "004150", + "rv64i_m/I/LHU-01", "004150", + "rv64i_m/I/LUI-01", "002010", + "rv64i_m/I/LW-01", "004210", + "rv64i_m/I/LWU-01", "004210", + "rv64i_m/I/OR-01", "004010", + "rv64i_m/I/ORI-01", "003010", + "rv64i_m/I/SB-01", "004010", + "rv64i_m/I/SD-01", "004010", + "rv64i_m/I/SH-01", "004010", + "rv64i_m/I/SLL-01", "003010", + "rv64i_m/I/SLLI-01", "003010", + "rv64i_m/I/SLLIW-01", "003010", + "rv64i_m/I/SLLW-01", "003010", + "rv64i_m/I/SLT-01", "004010", + "rv64i_m/I/SLTI-01", "003010", + "rv64i_m/I/SLTIU-01", "003010", + "rv64i_m/I/SLTU-01", "004010", + "rv64i_m/I/SRA-01", "003010", + "rv64i_m/I/SRAI-01", "003010", + "rv64i_m/I/SRAIW-01", "003010", + "rv64i_m/I/SRAW-01", "003010", + "rv64i_m/I/SRL-01", "003010", + "rv64i_m/I/SRLI-01", "003010", + "rv64i_m/I/SRLIW-01", "003010", + "rv64i_m/I/SRLW-01", "003010", + "rv64i_m/I/SUB-01", "004010", + "rv64i_m/I/SUBW-01", "003010", + "rv64i_m/I/SW-01", "004010", + "rv64i_m/I/XOR-01", "004010", + "rv64i_m/I/XORI-01", "003010" }; string imperas32m[] = '{ `IMPERASTEST, - "rv32i_m/M/DIV-01", "002010", - "rv32i_m/M/DIVU-01", "002010", - "rv32i_m/M/MUL-01", "002010", - "rv32i_m/M/MULH-01", "002010", - "rv32i_m/M/MULHSU-01", "002010", - "rv32i_m/M/MULHU-01", "002010", - "rv32i_m/M/REM-01", "002010", - "rv32i_m/M/REMU-01", "002010" + "rv32i_m/M/DIV-01", "002010", + "rv32i_m/M/DIVU-01", "002010", + "rv32i_m/M/MUL-01", "002010", + "rv32i_m/M/MULH-01", "002010", + "rv32i_m/M/MULHSU-01", "002010", + "rv32i_m/M/MULHU-01", "002010", + "rv32i_m/M/REM-01", "002010", + "rv32i_m/M/REMU-01", "002010" }; string imperas32c[] = '{ `IMPERASTEST, - "rv32i_m/C/C-ADD-01", "002010", - "rv32i_m/C/C-ADDI-01", "002010", - "rv32i_m/C/C-ADDI16SP-01", "002010", - "rv32i_m/C/C-ADDI4SPN-01", "002010", - "rv32i_m/C/C-AND-01", "002010", - "rv32i_m/C/C-ANDI-01", "002010", - "rv32i_m/C/C-BEQZ-01", "003010", - "rv32i_m/C/C-BNEZ-01", "003010", - "rv32i_m/C/C-J-01", "002010", - "rv32i_m/C/C-JAL-01", "002010", - "rv32i_m/C/C-JALR-01", "003010", - "rv32i_m/C/C-JR-01", "003010", - "rv32i_m/C/C-LI-01", "002010", - "rv32i_m/C/C-LUI-01", "002010", - "rv32i_m/C/C-LW-01", "002120", - "rv32i_m/C/C-LWSP-01", "002120", - "rv32i_m/C/C-MV-01", "002010", - "rv32i_m/C/C-OR-01", "002010", - "rv32i_m/C/C-SLLI-01", "002010", - "rv32i_m/C/C-SRAI-01", "002010", - "rv32i_m/C/C-SRLI-01", "002010", - "rv32i_m/C/C-SUB-01", "002010", - "rv32i_m/C/C-SW-01", "002010", - "rv32i_m/C/C-SWSP-01", "002010", - "rv32i_m/C/C-XOR-01", "002010", - "rv32i_m/C/I-C-EBREAK-01", "002000", - "rv32i_m/C/I-C-NOP-01", "002000" + "rv32i_m/C/C-ADD-01", "002010", + "rv32i_m/C/C-ADDI-01", "002010", + "rv32i_m/C/C-ADDI16SP-01", "002010", + "rv32i_m/C/C-ADDI4SPN-01", "002010", + "rv32i_m/C/C-AND-01", "002010", + "rv32i_m/C/C-ANDI-01", "002010", + "rv32i_m/C/C-BEQZ-01", "003010", + "rv32i_m/C/C-BNEZ-01", "003010", + "rv32i_m/C/C-J-01", "002010", + "rv32i_m/C/C-JAL-01", "002010", + "rv32i_m/C/C-JALR-01", "003010", + "rv32i_m/C/C-JR-01", "003010", + "rv32i_m/C/C-LI-01", "002010", + "rv32i_m/C/C-LUI-01", "002010", + "rv32i_m/C/C-LW-01", "002120", + "rv32i_m/C/C-LWSP-01", "002120", + "rv32i_m/C/C-MV-01", "002010", + "rv32i_m/C/C-OR-01", "002010", + "rv32i_m/C/C-SLLI-01", "002010", + "rv32i_m/C/C-SRAI-01", "002010", + "rv32i_m/C/C-SRLI-01", "002010", + "rv32i_m/C/C-SUB-01", "002010", + "rv32i_m/C/C-SW-01", "002010", + "rv32i_m/C/C-SWSP-01", "002010", + "rv32i_m/C/C-XOR-01", "002010", + "rv32i_m/C/I-C-EBREAK-01", "002000", + "rv32i_m/C/I-C-NOP-01", "002000" }; string imperas32iNOc[] = { `IMPERASTEST, - "rv32i_m/I/I-MISALIGN_JMP-01", "002000" + "rv32i_m/I/I-MISALIGN_JMP-01", "002000" }; string imperas32i[] = { `IMPERASTEST, - "rv32i_m/I/ADD-01", "002010", - "rv32i_m/I/ADDI-01", "002010", - "rv32i_m/I/AND-01", "002010", - "rv32i_m/I/ANDI-01", "002010", - "rv32i_m/I/AUIPC-01", "002010", - "rv32i_m/I/BEQ-01", "003010", - "rv32i_m/I/BGE-01", "003010", - "rv32i_m/I/BGEU-01", "003010", - "rv32i_m/I/BLT-01", "003010", - "rv32i_m/I/BLTU-01", "003010", - "rv32i_m/I/BNE-01", "003010", - "rv32i_m/I/I-DELAY_SLOTS-01", "002010", - "rv32i_m/I/I-EBREAK-01", "002010", - "rv32i_m/I/I-ECALL-01", "002010", - "rv32i_m/I/I-ENDIANESS-01", "002010", - "rv32i_m/I/I-IO-01", "002030", -// "rv32i_m/I/I-MISALIGN_JMP-01", "002000", - "rv32i_m/I/I-MISALIGN_LDST-01", "002010", - "rv32i_m/I/I-NOP-01", "002000", - "rv32i_m/I/I-RF_size-01", "002000", - "rv32i_m/I/I-RF_width-01", "002000", - "rv32i_m/I/I-RF_x0-01", "002010", - "rv32i_m/I/JAL-01", "003010", - "rv32i_m/I/JALR-01", "003010", - "rv32i_m/I/LB-01", "003030", - "rv32i_m/I/LBU-01", "003030", - "rv32i_m/I/LH-01", "003060", - "rv32i_m/I/LHU-01", "003060", - "rv32i_m/I/LUI-01", "002010", - "rv32i_m/I/LW-01", "003120", - "rv32i_m/I/OR-01", "002010", - "rv32i_m/I/ORI-01", "002010", - "rv32i_m/I/SB-01", "003010", - "rv32i_m/I/SH-01", "003010", - "rv32i_m/I/SLL-01", "002010", - "rv32i_m/I/SLLI-01", "002010", - "rv32i_m/I/SLT-01", "002010", - "rv32i_m/I/SLTI-01", "002010", - "rv32i_m/I/SLTIU-01", "002010", - "rv32i_m/I/SLTU-01", "002010", - "rv32i_m/I/SRA-01", "002010", - "rv32i_m/I/SRAI-01", "002010", - "rv32i_m/I/SRL-01", "002010", - "rv32i_m/I/SRLI-01", "002010", - "rv32i_m/I/SUB-01", "002010", - "rv32i_m/I/SW-01", "003010", - "rv32i_m/I/XOR-01", "002010", - "rv32i_m/I/XORI-01", "002010" + "rv32i_m/I/ADD-01", "002010", + "rv32i_m/I/ADDI-01", "002010", + "rv32i_m/I/AND-01", "002010", + "rv32i_m/I/ANDI-01", "002010", + "rv32i_m/I/AUIPC-01", "002010", + "rv32i_m/I/BEQ-01", "003010", + "rv32i_m/I/BGE-01", "003010", + "rv32i_m/I/BGEU-01", "003010", + "rv32i_m/I/BLT-01", "003010", + "rv32i_m/I/BLTU-01", "003010", + "rv32i_m/I/BNE-01", "003010", + "rv32i_m/I/I-DELAY_SLOTS-01", "002010", + "rv32i_m/I/I-EBREAK-01", "002010", + "rv32i_m/I/I-ECALL-01", "002010", + "rv32i_m/I/I-ENDIANESS-01", "002010", + "rv32i_m/I/I-IO-01", "002030", +// "rv32i_m/I/I-MISALIGN_JMP-01", "002000", + "rv32i_m/I/I-MISALIGN_LDST-01", "002010", + "rv32i_m/I/I-NOP-01", "002000", + "rv32i_m/I/I-RF_size-01", "002000", + "rv32i_m/I/I-RF_width-01", "002000", + "rv32i_m/I/I-RF_x0-01", "002010", + "rv32i_m/I/JAL-01", "003010", + "rv32i_m/I/JALR-01", "003010", + "rv32i_m/I/LB-01", "003030", + "rv32i_m/I/LBU-01", "003030", + "rv32i_m/I/LH-01", "003060", + "rv32i_m/I/LHU-01", "003060", + "rv32i_m/I/LUI-01", "002010", + "rv32i_m/I/LW-01", "003120", + "rv32i_m/I/OR-01", "002010", + "rv32i_m/I/ORI-01", "002010", + "rv32i_m/I/SB-01", "003010", + "rv32i_m/I/SH-01", "003010", + "rv32i_m/I/SLL-01", "002010", + "rv32i_m/I/SLLI-01", "002010", + "rv32i_m/I/SLT-01", "002010", + "rv32i_m/I/SLTI-01", "002010", + "rv32i_m/I/SLTIU-01", "002010", + "rv32i_m/I/SLTU-01", "002010", + "rv32i_m/I/SRA-01", "002010", + "rv32i_m/I/SRAI-01", "002010", + "rv32i_m/I/SRL-01", "002010", + "rv32i_m/I/SRLI-01", "002010", + "rv32i_m/I/SUB-01", "002010", + "rv32i_m/I/SW-01", "003010", + "rv32i_m/I/XOR-01", "002010", + "rv32i_m/I/XORI-01", "002010" }; string testsBP64[] = '{ @@ -1475,10 +1475,10 @@ string imperas32f[] = '{ string wally64i[] = '{ `WALLYTEST, "rv64i_m/I/WALLY-ADD", "002010", - "rv64i_m/I/WALLY-SLT", "002010", - "rv64i_m/I/WALLY-SLTU", "002010", - "rv64i_m/I/WALLY-SUB", "002010", - "rv64i_m/I/WALLY-XOR", "002010" + "rv64i_m/I/WALLY-SLT", "002010", + "rv64i_m/I/WALLY-SLTU", "002010", + "rv64i_m/I/WALLY-SUB", "002010", + "rv64i_m/I/WALLY-XOR", "002010" }; string wally64priv[] = '{ @@ -1487,20 +1487,63 @@ string imperas32f[] = '{ "rv64i_m/privilege/WALLY-MMU-SV48", "30A0", "rv64i_m/privilege/WALLY-PMP", "30A0", "rv64i_m/privilege/WALLY-PMA", "30A0", - "rv64i_m/privilege/WALLY-minfo-01", "30A0" + "rv64i_m/privilege/WALLY-minfo-01", "30A0", + "rv64i_m/privilege/WALLY-CSR-permission-s-01", "40A0", + "rv64i_m/privilege/WALLY-CSR-permission-u-01", "40A0" }; string wally64periph[] = '{ `WALLYTEST }; + string wally32e[] = '{ + `WALLYTEST, + "rv32i_m/I/E-add-01", "005010", + "rv32i_m/I/E-addi-01", "004010", + "rv32i_m/I/E-and-01", "005010", + "rv32i_m/I/E-andi-01", "004010", + "rv32i_m/I/E-auipc-01", "002010", + "rv32i_m/I/E-beq-01", "03b010", + "rv32i_m/I/E-bge-01", "034010", + "rv32i_m/I/E-bgeu-01", "047010", + "rv32i_m/I/E-blt-01", "038010", + "rv32i_m/I/E-bltu-01", "03e010", + "rv32i_m/I/E-bne-01", "038010", + "rv32i_m/I/E-jal-01", "e02010", + "rv32i_m/I/E-jalr-01", "002010", + "rv32i_m/I/E-lb-align-01", "002010", + "rv32i_m/I/E-lbu-align-01", "002010", + "rv32i_m/I/E-lh-align-01", "002010", + "rv32i_m/I/E-lhu-align-01", "002010", + "rv32i_m/I/E-lui-01", "002010", + "rv32i_m/I/E-lw-align-01", "002010", + "rv32i_m/I/E-or-01", "005010", + "rv32i_m/I/E-ori-01", "004010", + "rv32i_m/I/E-sb-align-01", "002010", + "rv32i_m/I/E-sh-align-01", "002010", + "rv32i_m/I/E-sll-01", "002010", + "rv32i_m/I/E-slli-01", "002010", + "rv32i_m/I/E-slt-01", "005010", + "rv32i_m/I/E-slti-01", "004010", + "rv32i_m/I/E-sltiu-01", "004010", + "rv32i_m/I/E-sltu-01", "005010", + "rv32i_m/I/E-sra-01", "002010", + "rv32i_m/I/E-srai-01", "002010", + "rv32i_m/I/E-srl-01", "002010", + "rv32i_m/I/E-srli-01", "002010", + "rv32i_m/I/E-sub-01", "005010", + "rv32i_m/I/E-sw-align-01", "002010", + "rv32i_m/I/E-xor-01", "005010", + "rv32i_m/I/E-xori-01", "004010" + }; + string wally32i[] = '{ `WALLYTEST, "rv32i_m/I/WALLY-ADD", "002010", - "rv32i_m/I/WALLY-SLT", "002010", - "rv32i_m/I/WALLY-SLTU", "002010", - "rv32i_m/I/WALLY-SUB", "002010", - "rv32i_m/I/WALLY-XOR", "002010" + "rv32i_m/I/WALLY-SLT", "002010", + "rv32i_m/I/WALLY-SLTU", "002010", + "rv32i_m/I/WALLY-SUB", "002010", + "rv32i_m/I/WALLY-XOR", "002010" }; string wally32priv[] = '{ diff --git a/synthDC/.synopsys_dc.setup b/synthDC/.synopsys_dc.setup index e4441ef3..f5d7f0ec 100755 --- a/synthDC/.synopsys_dc.setup +++ b/synthDC/.synopsys_dc.setup @@ -3,7 +3,7 @@ set CURRENT_DIR [exec pwd] set search_path [list "./" ] -set s8lib ../addins/sky130_osu_sc_t18/18T_ms/lib +set s8lib ../addins/sky130_osu_sc_t12/12T_ms/lib lappend search_path $s8lib # Synthetic libraries @@ -12,7 +12,7 @@ set synthetic_library [list dw_foundation.sldb] # Set OKSTATE standard cell libraries set target_library [list] -lappend target_library sky130_osu_sc_18T_ms_TT_1P8_25C.ccs.db +lappend target_library sky130_osu_sc_12T_ms_TT_1P8_25C.ccs.db # Set Link Library set link_library "$target_library $synthetic_library" diff --git a/synthDC/hdl/wally-shared.vh b/synthDC/hdl/wally-shared.vh new file mode 100644 index 00000000..277814f8 --- /dev/null +++ b/synthDC/hdl/wally-shared.vh @@ -0,0 +1,62 @@ +////////////////////////////////////////// +// wally-shared.vh +// +// Written: david_harris@hmc.edu 7 June 2021 +// +// Purpose: Shared and default configuration values common to all designs +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +// include shared constants +`include "wally-constants.vh" + +// macros to define supported modes +// NOTE: No hardware support fo Q yet + +`define A_SUPPORTED ((`MISA >> 0) % 2 == 1) +`define C_SUPPORTED ((`MISA >> 2) % 2 == 1) +`define D_SUPPORTED ((`MISA >> 3) % 2 == 1) +`define E_SUPPORTED ((`MISA >> 4) % 2 == 1) +`define F_SUPPORTED ((`MISA >> 5) % 2 == 1) +`define I_SUPPORTED ((`MISA >> 8) % 2 == 1) +`define M_SUPPORTED ((`MISA >> 12) % 2 == 1) +`define Q_SUPPORTED ((`MISA >> 16) % 2 == 1) +`define S_SUPPORTED ((`MISA >> 18) % 2 == 1) +`define U_SUPPORTED ((`MISA >> 20) % 2 == 1) + +// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21 +//`define N_SUPPORTED ((MISA >> 13) % 2 == 1) +`define N_SUPPORTED 0 + + +// logarithm of XLEN, used for number of index bits to select +`define LOG_XLEN (`XLEN == 32 ? 5 : 6) + +// Number of 64 bit PMP Configuration Register entries (or pairs of 32 bit entries) +`define PMPCFG_ENTRIES (`PMP_ENTRIES/8) + +// Floating point length FLEN and number of exponent (NE) and fraction (NF) bits +`define FLEN 64//(`Q_SUPPORTED ? 128 : `D_SUPPORTED ? 64 : 32) +`define NE 11//(`Q_SUPPORTED ? 15 : `D_SUPPORTED ? 11 : 8) +`define NF 52//(`Q_SUPPORTED ? 112 : `D_SUPPORTED ? 52 : 23) + +// Disable spurious Verilator warnings + +/* verilator lint_off STMTDLY */ +/* verilator lint_off ASSIGNDLY */ +/* verilator lint_off PINCONNECTEMPTY */ diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index a52abaa9..23a30593 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -6,11 +6,11 @@ # Config set hdl_src "../pipelined/src" -eval file copy ${hdl_src}/../config/rv64gc/wally-config.vh {hdl/} -eval file copy ${hdl_src}/../config/rv64gc/wally-config.vh {reports/} -eval file copy [glob ${hdl_src}/../config/shared/*.vh] {hdl/} -eval file copy [glob ${hdl_src}/*/*.sv] {hdl/} -eval file copy [glob ${hdl_src}/*/flop/*.sv] {hdl/} +eval file copy -force ${hdl_src}/../config/rv32e/wally-config.vh {hdl/} +eval file copy -force ${hdl_src}/../config/rv32e/wally-config.vh {reports/} +eval file copy -force [glob ${hdl_src}/../config/shared/*.vh] {hdl/} +eval file copy -force [glob ${hdl_src}/*/*.sv] {hdl/} +eval file copy -force [glob ${hdl_src}/*/flop/*.sv] {hdl/} # Verilog files set my_verilog_files [glob hdl/*] @@ -47,7 +47,7 @@ reset_design # Set Frequency in [MHz] or [ps] set my_clock_pin clk -set my_clk_freq_MHz 10 +set my_clk_freq_MHz 500 set my_period [expr 1000 / $my_clk_freq_MHz] set my_uncertainty [expr .1 * $my_period] @@ -76,14 +76,14 @@ set all_in_ex_clk [remove_from_collection [all_inputs] [get_ports $my_clk]] set_propagated_clock [get_clocks $my_clk] # Setting constraints on input ports -set_driving_cell -lib_cell sky130_osu_sc_18T_ms__dff_1 -pin Q $all_in_ex_clk +set_driving_cell -lib_cell sky130_osu_sc_12T_ms__dff_1 -pin Q $all_in_ex_clk # Set input/output delay set_input_delay 0.0 -max -clock $my_clk $all_in_ex_clk set_output_delay 0.0 -max -clock $my_clk [all_outputs] # Setting load constraint on output ports -set_load [expr [load_of sky130_osu_sc_18T_ms_TT_1P8_25C.ccs/sky130_osu_sc_18T_ms__dff_1/D] * 1] [all_outputs] +set_load [expr [load_of sky130_osu_sc_12T_ms_TT_1P8_25C.ccs/sky130_osu_sc_12T_ms__dff_1/D] * 1] [all_outputs] # Set the wire load model set_wire_load_mode "top" @@ -111,7 +111,7 @@ write_file -format ddc -hierarchy -o $filename # Compile statements - either compile or compile_ultra # compile -scan -incr -map_effort low -# compile_ultra -no_seq_output_inversion -no_boundary_optimization +compile_ultra -no_seq_output_inversion -no_boundary_optimization # Eliminate need for assign statements (yuck!) set verilogout_no_tri true diff --git a/tests/wally-riscv-arch-test/Makefile b/tests/wally-riscv-arch-test/Makefile index eef7857b..168f03c3 100644 --- a/tests/wally-riscv-arch-test/Makefile +++ b/tests/wally-riscv-arch-test/Makefile @@ -87,7 +87,7 @@ simulate: run -C $(SUITEDIR) verify: simulate - riscv-test-env/verify.sh # dmh 1 November 2021 removed because these tests don't have expected values + riscv-test-env/verify.sh postverify: ifeq ($(wildcard $(TARGETDIR)/$(RISCV_TARGET)/postverify.sh),) diff --git a/tests/wally-riscv-arch-test/riscv-test-env/arch_test.h b/tests/wally-riscv-arch-test/riscv-test-env/arch_test.h deleted file mode 120000 index c1b8c50b..00000000 --- a/tests/wally-riscv-arch-test/riscv-test-env/arch_test.h +++ /dev/null @@ -1 +0,0 @@ -../riscv-test-suite/env/arch_test.h \ No newline at end of file diff --git a/tests/wally-riscv-arch-test/riscv-test-env/encoding.h b/tests/wally-riscv-arch-test/riscv-test-env/encoding.h deleted file mode 120000 index fd1833f0..00000000 --- a/tests/wally-riscv-arch-test/riscv-test-env/encoding.h +++ /dev/null @@ -1 +0,0 @@ -../riscv-test-suite/env/encoding.h \ No newline at end of file diff --git a/tests/wally-riscv-arch-test/riscv-test-env/p/link.ld b/tests/wally-riscv-arch-test/riscv-test-env/p/link.ld deleted file mode 100644 index 392e74f9..00000000 --- a/tests/wally-riscv-arch-test/riscv-test-env/p/link.ld +++ /dev/null @@ -1,22 +0,0 @@ -OUTPUT_ARCH( "riscv" ) -ENTRY(_start) - -SECTIONS -{ - . = 0x00000000; - .text.trap : { *(.text.trap) } - - . = 0x80000000; - .text.init : { *(.text.init) } - - . = ALIGN(0x1000); - .tohost : { *(.tohost) } - . = ALIGN(0x1000); - .text : { *(.text) } - . = ALIGN(0x1000); - .data : { *(.data) } - .data.string : { *(.data.string)} - .bss : { *(.bss) } - _end = .; -} - diff --git a/tests/wally-riscv-arch-test/riscv-test-env/p/riscv_test.h b/tests/wally-riscv-arch-test/riscv-test-env/p/riscv_test.h deleted file mode 100644 index e452261c..00000000 --- a/tests/wally-riscv-arch-test/riscv-test-env/p/riscv_test.h +++ /dev/null @@ -1,251 +0,0 @@ -// See LICENSE for license details. - -#ifndef _ENV_PHYSICAL_SINGLE_CORE_H -#define _ENV_PHYSICAL_SINGLE_CORE_H - -#include "../encoding.h" - -//----------------------------------------------------------------------- -// Begin Macro -//----------------------------------------------------------------------- - -#define RVTEST_RV64U \ - .macro init; \ - .endm - -#define RVTEST_RV64UF \ - .macro init; \ - RVTEST_FP_ENABLE; \ - .endm - -#define RVTEST_RV32U \ - .macro init; \ - .endm - -#define RVTEST_RV32UF \ - .macro init; \ - RVTEST_FP_ENABLE; \ - .endm - -#define RVTEST_RV64M \ - .macro init; \ - RVTEST_ENABLE_MACHINE; \ - .endm - -#define RVTEST_RV64S \ - .macro init; \ - RVTEST_ENABLE_SUPERVISOR; \ - .endm - -#define RVTEST_RV32M \ - .macro init; \ - RVTEST_ENABLE_MACHINE; \ - .endm - -#define RVTEST_RV32S \ - .macro init; \ - RVTEST_ENABLE_SUPERVISOR; \ - .endm - -#if __riscv_xlen == 64 -# define CHECK_XLEN li a0, 1; slli a0, a0, 31; bgez a0, 1f; RVTEST_PASS; 1: -#else -# define CHECK_XLEN li a0, 1; slli a0, a0, 31; bltz a0, 1f; RVTEST_PASS; 1: -#endif - -#define INIT_PMP \ - la t0, 1f; \ - csrw mtvec, t0; \ - li t0, -1; /* Set up a PMP to permit all accesses */ \ - csrw pmpaddr0, t0; \ - li t0, PMP_NAPOT | PMP_R | PMP_W | PMP_X; \ - csrw pmpcfg0, t0; \ - .align 2; \ -1: - -#define INIT_SATP \ - la t0, 1f; \ - csrw mtvec, t0; \ - csrwi satp, 0; \ - .align 2; \ -1: - -#define DELEGATE_NO_TRAPS \ - la t0, 1f; \ - csrw mtvec, t0; \ - csrwi medeleg, 0; \ - csrwi mideleg, 0; \ - csrwi mie, 0; \ - .align 2; \ -1: - -#define RVTEST_ENABLE_SUPERVISOR \ - li a0, MSTATUS_MPP & (MSTATUS_MPP >> 1); \ - csrs mstatus, a0; \ - li a0, SIP_SSIP | SIP_STIP; \ - csrs mideleg, a0; \ - -#define RVTEST_ENABLE_MACHINE \ - li a0, MSTATUS_MPP; \ - csrs mstatus, a0; \ - -#define RVTEST_FP_ENABLE \ - li a0, MSTATUS_FS & (MSTATUS_FS >> 1); \ - csrs mstatus, a0; \ - csrwi fcsr, 0 - -#define RISCV_MULTICORE_DISABLE \ - csrr a0, mhartid; \ - 1: bnez a0, 1b - -#define EXTRA_TVEC_USER -#define EXTRA_TVEC_MACHINE -#define EXTRA_INIT -#define EXTRA_INIT_TIMER - -// -// undefine some unusable CSR Accesses if no PRIV Mode present -// -#if defined(PRIV_MISA_S) -# if (PRIV_MISA_S==0) -# undef INIT_SATP -# define INIT_SATP -# undef INIT_PMP -# define INIT_PMP -# undef DELEGATE_NO_TRAPS -# define DELEGATE_NO_TRAPS -# undef RVTEST_ENABLE_SUPERVISOR -# define RVTEST_ENABLE_SUPERVISOR -# endif -#endif -#if defined(PRIV_MISA_U) -# if (PRIV_MISA_U==0) -# endif -#endif -#if defined(TRAPHANDLER) -#include TRAPHANDLER -#endif - -#define INTERRUPT_HANDLER j other_exception /* No interrupts should occur */ - -#define RVTEST_CODE_BEGIN_OLD \ - .section .text.init; \ - .align 6; \ - .weak stvec_handler; \ - .weak mtvec_handler; \ - .globl _start; \ -_start: \ - /* reset vector */ \ - j reset_vector; \ - .align 2; \ -trap_vector: \ - /* test whether the test came from pass/fail */ \ - csrr t5, mcause; \ - li t6, CAUSE_USER_ECALL; \ - beq t5, t6, write_tohost; \ - li t6, CAUSE_SUPERVISOR_ECALL; \ - beq t5, t6, write_tohost; \ - li t6, CAUSE_MACHINE_ECALL; \ - beq t5, t6, write_tohost; \ - /* if an mtvec_handler is defined, jump to it */ \ - la t5, mtvec_handler; \ - beqz t5, 1f; \ - jr t5; \ - /* was it an interrupt or an exception? */ \ - 1: csrr t5, mcause; \ - bgez t5, handle_exception; \ - INTERRUPT_HANDLER; \ -handle_exception: \ - /* we don't know how to handle whatever the exception was */ \ - other_exception: \ - /* some unhandlable exception occurred */ \ - 1: ori TESTNUM, TESTNUM, 1337; \ - write_tohost: \ - sw TESTNUM, tohost, t5; \ - j write_tohost; \ -reset_vector: \ - RISCV_MULTICORE_DISABLE; \ - INIT_SATP; \ - INIT_PMP; \ - DELEGATE_NO_TRAPS; \ - li TESTNUM, 0; \ - la t0, trap_vector; \ - csrw mtvec, t0; \ - CHECK_XLEN; \ - /* if an stvec_handler is defined, delegate exceptions to it */ \ - la t0, stvec_handler; \ - beqz t0, 1f; \ - csrw stvec, t0; \ - li t0, (1 << CAUSE_LOAD_PAGE_FAULT) | \ - (1 << CAUSE_STORE_PAGE_FAULT) | \ - (1 << CAUSE_FETCH_PAGE_FAULT) | \ - (1 << CAUSE_MISALIGNED_FETCH) | \ - (1 << CAUSE_USER_ECALL) | \ - (1 << CAUSE_BREAKPOINT); \ - csrw medeleg, t0; \ - csrr t1, medeleg; \ - bne t0, t1, other_exception; \ -1: csrwi mstatus, 0; \ - init; \ - EXTRA_INIT; \ - EXTRA_INIT_TIMER; \ - la t0, 1f; \ - csrw mepc, t0; \ - csrr a0, mhartid; \ - mret; \ -1: \ -begin_testcode: - - -//----------------------------------------------------------------------- -// End Macro -//----------------------------------------------------------------------- - -#define RVTEST_CODE_END_OLD \ -end_testcode: \ - ecall; - -//----------------------------------------------------------------------- -// Pass/Fail Macro -//----------------------------------------------------------------------- -#define RVTEST_SYNC fence -//#define RVTEST_SYNC nop - -#define RVTEST_PASS \ - RVTEST_SYNC; \ - li TESTNUM, 1; \ - SWSIG (0, TESTNUM); \ - ecall - -#define TESTNUM gp -#define RVTEST_FAIL \ - RVTEST_SYNC; \ -1: beqz TESTNUM, 1b; \ - sll TESTNUM, TESTNUM, 1; \ - or TESTNUM, TESTNUM, 1; \ - SWSIG (0, TESTNUM); \ - la x1, end_testcode; \ - jr x1; - -//----------------------------------------------------------------------- -// Data Section Macro -//----------------------------------------------------------------------- - -#define EXTRA_DATA - -#define RVTEST_DATA_BEGIN_OLD \ - .align 4; .global begin_signature; begin_signature: - -#define RVTEST_DATA_END_OLD \ - .align 4; .global end_signature; end_signature: \ - EXTRA_DATA \ - .pushsection .tohost,"aw",@progbits; \ - .align 8; .global tohost; tohost: .dword 0; \ - .align 8; .global fromhost; fromhost: .dword 0; \ - .popsection; \ - .align 8; .global begin_regstate; begin_regstate: \ - .word 128; \ - .align 8; .global end_regstate; end_regstate: \ - .word 4; - -#endif diff --git a/tests/wally-riscv-arch-test/riscv-test-env/pm/link.ld b/tests/wally-riscv-arch-test/riscv-test-env/pm/link.ld deleted file mode 100644 index b3e315e7..00000000 --- a/tests/wally-riscv-arch-test/riscv-test-env/pm/link.ld +++ /dev/null @@ -1,17 +0,0 @@ -OUTPUT_ARCH( "riscv" ) -ENTRY(_start) - -SECTIONS -{ - . = 0x80000000; - .text.init : { *(.text.init) } - . = ALIGN(0x1000); - .tohost : { *(.tohost) } - . = ALIGN(0x1000); - .text : { *(.text) } - . = ALIGN(0x1000); - .data : { *(.data) } - .bss : { *(.bss) } - _end = .; -} - diff --git a/tests/wally-riscv-arch-test/riscv-test-env/pm/riscv_test.h b/tests/wally-riscv-arch-test/riscv-test-env/pm/riscv_test.h deleted file mode 100644 index 38a0e86b..00000000 --- a/tests/wally-riscv-arch-test/riscv-test-env/pm/riscv_test.h +++ /dev/null @@ -1,11 +0,0 @@ -// See LICENSE for license details. - -#ifndef _ENV_PHYSICAL_MULTI_CORE_H -#define _ENV_PHYSICAL_MULTI_CORE_H - -#include "../p/riscv_test.h" - -#undef RISCV_MULTICORE_DISABLE -#define RISCV_MULTICORE_DISABLE - -#endif diff --git a/tests/wally-riscv-arch-test/riscv-test-env/pt/link.ld b/tests/wally-riscv-arch-test/riscv-test-env/pt/link.ld deleted file mode 100644 index b3e315e7..00000000 --- a/tests/wally-riscv-arch-test/riscv-test-env/pt/link.ld +++ /dev/null @@ -1,17 +0,0 @@ -OUTPUT_ARCH( "riscv" ) -ENTRY(_start) - -SECTIONS -{ - . = 0x80000000; - .text.init : { *(.text.init) } - . = ALIGN(0x1000); - .tohost : { *(.tohost) } - . = ALIGN(0x1000); - .text : { *(.text) } - . = ALIGN(0x1000); - .data : { *(.data) } - .bss : { *(.bss) } - _end = .; -} - diff --git a/tests/wally-riscv-arch-test/riscv-test-env/pt/riscv_test.h b/tests/wally-riscv-arch-test/riscv-test-env/pt/riscv_test.h deleted file mode 100644 index 34c2a331..00000000 --- a/tests/wally-riscv-arch-test/riscv-test-env/pt/riscv_test.h +++ /dev/null @@ -1,69 +0,0 @@ -// See LICENSE for license details. - -#ifndef _ENV_PHYSICAL_SINGLE_CORE_TIMER_H -#define _ENV_PHYSICAL_SINGLE_CORE_TIMER_H - -#include "../p/riscv_test.h" - -#define TIMER_INTERVAL 2 - -#undef EXTRA_INIT_TIMER -#define EXTRA_INIT_TIMER \ - li a0, MIP_MTIP; \ - csrs mie, a0; \ - csrr a0, mtime; \ - addi a0, a0, TIMER_INTERVAL; \ - csrw mtimecmp, a0; \ - -#if SSTATUS_XS != 0x18000 -# error -#endif -#define XS_SHIFT 15 - -#undef INTERRUPT_HANDLER -#define INTERRUPT_HANDLER \ - slli t5, t5, 1; \ - srli t5, t5, 1; \ - add t5, t5, -IRQ_M_TIMER; \ - bnez t5, other_exception; /* other interrups shouldn't happen */\ - csrr t5, mtime; \ - addi t5, t5, TIMER_INTERVAL; \ - csrw mtimecmp, t5; \ - mret; \ - -//----------------------------------------------------------------------- -// Data Section Macro -//----------------------------------------------------------------------- - -#undef EXTRA_DATA -#define EXTRA_DATA \ - .align 3; \ -regspill: \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ - .dword 0xdeadbeefcafebabe; \ -evac: \ - .skip 32768; \ - -#endif diff --git a/tests/wally-riscv-arch-test/riscv-test-env/v/entry.S b/tests/wally-riscv-arch-test/riscv-test-env/v/entry.S deleted file mode 100644 index 97196620..00000000 --- a/tests/wally-riscv-arch-test/riscv-test-env/v/entry.S +++ /dev/null @@ -1,125 +0,0 @@ -#include "riscv_test.h" - -#if __riscv_xlen == 64 -# define STORE sd -# define LOAD ld -# define REGBYTES 8 -#else -# define STORE sw -# define LOAD lw -# define REGBYTES 4 -#endif - -#define STACK_TOP (_end + 4096) - - .section ".text.init","ax",@progbits - .globl _start -_start: - j handle_reset - - /* NMI vector */ -nmi_vector: - j wtf - -trap_vector: - j wtf - -handle_reset: - la t0, trap_vector - csrw mtvec, t0 - la sp, STACK_TOP - SIZEOF_TRAPFRAME_T - csrr t0, mhartid - slli t0, t0, 12 - add sp, sp, t0 - csrw mscratch, sp - la a0, userstart - j vm_boot - - .globl pop_tf -pop_tf: - LOAD t0,33*REGBYTES(a0) - csrw sepc,t0 - LOAD x1,1*REGBYTES(a0) - LOAD x2,2*REGBYTES(a0) - LOAD x3,3*REGBYTES(a0) - LOAD x4,4*REGBYTES(a0) - LOAD x5,5*REGBYTES(a0) - LOAD x6,6*REGBYTES(a0) - LOAD x7,7*REGBYTES(a0) - LOAD x8,8*REGBYTES(a0) - LOAD x9,9*REGBYTES(a0) - LOAD x11,11*REGBYTES(a0) - LOAD x12,12*REGBYTES(a0) - LOAD x13,13*REGBYTES(a0) - LOAD x14,14*REGBYTES(a0) - LOAD x15,15*REGBYTES(a0) - LOAD x16,16*REGBYTES(a0) - LOAD x17,17*REGBYTES(a0) - LOAD x18,18*REGBYTES(a0) - LOAD x19,19*REGBYTES(a0) - LOAD x20,20*REGBYTES(a0) - LOAD x21,21*REGBYTES(a0) - LOAD x22,22*REGBYTES(a0) - LOAD x23,23*REGBYTES(a0) - LOAD x24,24*REGBYTES(a0) - LOAD x25,25*REGBYTES(a0) - LOAD x26,26*REGBYTES(a0) - LOAD x27,27*REGBYTES(a0) - LOAD x28,28*REGBYTES(a0) - LOAD x29,29*REGBYTES(a0) - LOAD x30,30*REGBYTES(a0) - LOAD x31,31*REGBYTES(a0) - LOAD a0,10*REGBYTES(a0) - sret - - .global trap_entry -trap_entry: - csrrw sp, sscratch, sp - - # save gprs - STORE x1,1*REGBYTES(sp) - STORE x3,3*REGBYTES(sp) - STORE x4,4*REGBYTES(sp) - STORE x5,5*REGBYTES(sp) - STORE x6,6*REGBYTES(sp) - STORE x7,7*REGBYTES(sp) - STORE x8,8*REGBYTES(sp) - STORE x9,9*REGBYTES(sp) - STORE x10,10*REGBYTES(sp) - STORE x11,11*REGBYTES(sp) - STORE x12,12*REGBYTES(sp) - STORE x13,13*REGBYTES(sp) - STORE x14,14*REGBYTES(sp) - STORE x15,15*REGBYTES(sp) - STORE x16,16*REGBYTES(sp) - STORE x17,17*REGBYTES(sp) - STORE x18,18*REGBYTES(sp) - STORE x19,19*REGBYTES(sp) - STORE x20,20*REGBYTES(sp) - STORE x21,21*REGBYTES(sp) - STORE x22,22*REGBYTES(sp) - STORE x23,23*REGBYTES(sp) - STORE x24,24*REGBYTES(sp) - STORE x25,25*REGBYTES(sp) - STORE x26,26*REGBYTES(sp) - STORE x27,27*REGBYTES(sp) - STORE x28,28*REGBYTES(sp) - STORE x29,29*REGBYTES(sp) - STORE x30,30*REGBYTES(sp) - STORE x31,31*REGBYTES(sp) - - csrrw t0,sscratch,sp - STORE t0,2*REGBYTES(sp) - - # get sr, epc, badvaddr, cause - csrr t0,sstatus - STORE t0,32*REGBYTES(sp) - csrr t0,sepc - STORE t0,33*REGBYTES(sp) - csrr t0,sbadaddr - STORE t0,34*REGBYTES(sp) - csrr t0,scause - STORE t0,35*REGBYTES(sp) - - move a0, sp - j handle_trap diff --git a/tests/wally-riscv-arch-test/riscv-test-env/v/link.ld b/tests/wally-riscv-arch-test/riscv-test-env/v/link.ld deleted file mode 100644 index b3e315e7..00000000 --- a/tests/wally-riscv-arch-test/riscv-test-env/v/link.ld +++ /dev/null @@ -1,17 +0,0 @@ -OUTPUT_ARCH( "riscv" ) -ENTRY(_start) - -SECTIONS -{ - . = 0x80000000; - .text.init : { *(.text.init) } - . = ALIGN(0x1000); - .tohost : { *(.tohost) } - . = ALIGN(0x1000); - .text : { *(.text) } - . = ALIGN(0x1000); - .data : { *(.data) } - .bss : { *(.bss) } - _end = .; -} - diff --git a/tests/wally-riscv-arch-test/riscv-test-env/v/riscv_test.h b/tests/wally-riscv-arch-test/riscv-test-env/v/riscv_test.h deleted file mode 100644 index 8ca9ffd7..00000000 --- a/tests/wally-riscv-arch-test/riscv-test-env/v/riscv_test.h +++ /dev/null @@ -1,71 +0,0 @@ -// See LICENSE for license details. - -#ifndef _ENV_VIRTUAL_SINGLE_CORE_H -#define _ENV_VIRTUAL_SINGLE_CORE_H - -#include "../p/riscv_test.h" - -//----------------------------------------------------------------------- -// Begin Macro -//----------------------------------------------------------------------- - -#undef RVTEST_FP_ENABLE -#define RVTEST_FP_ENABLE fssr x0 - -#undef RVTEST_CODE_BEGIN -#define RVTEST_CODE_BEGIN \ - .text; \ - .global userstart; \ -userstart: \ - init - -//----------------------------------------------------------------------- -// Pass/Fail Macro -//----------------------------------------------------------------------- - -#undef RVTEST_PASS -#define RVTEST_PASS li a0, 1; scall - -#undef RVTEST_FAIL -#define RVTEST_FAIL sll a0, TESTNUM, 1; 1:beqz a0, 1b; or a0, a0, 1; scall; - -//----------------------------------------------------------------------- -// Data Section Macro -//----------------------------------------------------------------------- - -#undef RVTEST_DATA_END -#define RVTEST_DATA_END - -//----------------------------------------------------------------------- -// Supervisor mode definitions and macros -//----------------------------------------------------------------------- - -#define MAX_TEST_PAGES 63 // this must be the period of the LFSR below -#define LFSR_NEXT(x) (((((x)^((x)>>1)) & 1) << 5) | ((x) >> 1)) - -#define PGSHIFT 12 -#define PGSIZE (1UL << PGSHIFT) - -#define SIZEOF_TRAPFRAME_T ((__riscv_xlen / 8) * 36) - -#ifndef __ASSEMBLER__ - -typedef unsigned long pte_t; -#define LEVELS (sizeof(pte_t) == sizeof(uint64_t) ? 3 : 2) -#define PTIDXBITS (PGSHIFT - (sizeof(pte_t) == 8 ? 3 : 2)) -#define VPN_BITS (PTIDXBITS * LEVELS) -#define VA_BITS (VPN_BITS + PGSHIFT) -#define PTES_PER_PT (1UL << RISCV_PGLEVEL_BITS) -#define MEGAPAGE_SIZE (PTES_PER_PT * PGSIZE) - -typedef struct -{ - long gpr[32]; - long sr; - long epc; - long badvaddr; - long cause; -} trapframe_t; -#endif - -#endif diff --git a/tests/wally-riscv-arch-test/riscv-test-env/v/string.c b/tests/wally-riscv-arch-test/riscv-test-env/v/string.c deleted file mode 100644 index 4ffedc0a..00000000 --- a/tests/wally-riscv-arch-test/riscv-test-env/v/string.c +++ /dev/null @@ -1,114 +0,0 @@ -#include -#include -#include - -void* memcpy(void* dest, const void* src, size_t len) -{ - if ((((uintptr_t)dest | (uintptr_t)src | len) & (sizeof(uintptr_t)-1)) == 0) { - const uintptr_t* s = src; - uintptr_t *d = dest; - while (d < (uintptr_t*)(dest + len)) - *d++ = *s++; - } else { - const char* s = src; - char *d = dest; - while (d < (char*)(dest + len)) - *d++ = *s++; - } - return dest; -} - -void* memset(void* dest, int byte, size_t len) -{ - if ((((uintptr_t)dest | len) & (sizeof(uintptr_t)-1)) == 0) { - uintptr_t word = byte & 0xFF; - word |= word << 8; - word |= word << 16; - word |= word << 16 << 16; - - uintptr_t *d = dest; - while (d < (uintptr_t*)(dest + len)) - *d++ = word; - } else { - char *d = dest; - while (d < (char*)(dest + len)) - *d++ = byte; - } - return dest; -} - -size_t strlen(const char *s) -{ - const char *p = s; - while (*p) - p++; - return p - s; -} - -int strcmp(const char* s1, const char* s2) -{ - unsigned char c1, c2; - - do { - c1 = *s1++; - c2 = *s2++; - } while (c1 != 0 && c1 == c2); - - return c1 - c2; -} - -int memcmp(const void* s1, const void* s2, size_t n) -{ - if ((((uintptr_t)s1 | (uintptr_t)s2) & (sizeof(uintptr_t)-1)) == 0) { - const uintptr_t* u1 = s1; - const uintptr_t* u2 = s2; - const uintptr_t* end = u1 + (n / sizeof(uintptr_t)); - while (u1 < end) { - if (*u1 != *u2) - break; - u1++; - u2++; - } - n -= (const void*)u1 - s1; - s1 = u1; - s2 = u2; - } - - while (n--) { - unsigned char c1 = *(const unsigned char*)s1++; - unsigned char c2 = *(const unsigned char*)s2++; - if (c1 != c2) - return c1 - c2; - } - - return 0; -} - -char* strcpy(char* dest, const char* src) -{ - char* d = dest; - while ((*d++ = *src++)) - ; - return dest; -} - -long atol(const char* str) -{ - long res = 0; - int sign = 0; - - while (*str == ' ') - str++; - - if (*str == '-' || *str == '+') { - sign = *str == '-'; - str++; - } - - while (*str) { - res *= 10; - res += *str++ - '0'; - } - - return sign ? -res : res; -} diff --git a/tests/wally-riscv-arch-test/riscv-test-env/v/vm.c b/tests/wally-riscv-arch-test/riscv-test-env/v/vm.c deleted file mode 100644 index 8064b7ba..00000000 --- a/tests/wally-riscv-arch-test/riscv-test-env/v/vm.c +++ /dev/null @@ -1,273 +0,0 @@ -// See LICENSE for license details. - -#include -#include -#include - -#include "riscv_test.h" - -void trap_entry(); -void pop_tf(trapframe_t*); - -volatile uint64_t tohost; -volatile uint64_t fromhost; - -static void do_tohost(uint64_t tohost_value) -{ - while (tohost) - fromhost = 0; - tohost = tohost_value; -} - -#define pa2kva(pa) ((void*)(pa) - DRAM_BASE - MEGAPAGE_SIZE) -#define uva2kva(pa) ((void*)(pa) - MEGAPAGE_SIZE) - -#define flush_page(addr) asm volatile ("sfence.vma %0" : : "r" (addr) : "memory") - -static uint64_t lfsr63(uint64_t x) -{ - uint64_t bit = (x ^ (x >> 1)) & 1; - return (x >> 1) | (bit << 62); -} - -static void cputchar(int x) -{ - do_tohost(0x0101000000000000 | (unsigned char)x); -} - -static void cputstring(const char* s) -{ - while (*s) - cputchar(*s++); -} - -static void terminate(int code) -{ - do_tohost(code); - while (1); -} - -void wtf() -{ - terminate(841); -} - -#define stringify1(x) #x -#define stringify(x) stringify1(x) -#define assert(x) do { \ - if (x) break; \ - cputstring("Assertion failed: " stringify(x) "\n"); \ - terminate(3); \ -} while(0) - -#define l1pt pt[0] -#define user_l2pt pt[1] -#if __riscv_xlen == 64 -# define NPT 4 -#define kernel_l2pt pt[2] -# define user_l3pt pt[3] -#else -# define NPT 2 -# define user_l3pt user_l2pt -#endif -pte_t pt[NPT][PTES_PER_PT] __attribute__((aligned(PGSIZE))); - -typedef struct { pte_t addr; void* next; } freelist_t; - -freelist_t user_mapping[MAX_TEST_PAGES]; -freelist_t freelist_nodes[MAX_TEST_PAGES]; -freelist_t *freelist_head, *freelist_tail; - -void printhex(uint64_t x) -{ - char str[17]; - for (int i = 0; i < 16; i++) - { - str[15-i] = (x & 0xF) + ((x & 0xF) < 10 ? '0' : 'a'-10); - x >>= 4; - } - str[16] = 0; - - cputstring(str); -} - -static void evict(unsigned long addr) -{ - assert(addr >= PGSIZE && addr < MAX_TEST_PAGES * PGSIZE); - addr = addr/PGSIZE*PGSIZE; - - freelist_t* node = &user_mapping[addr/PGSIZE]; - if (node->addr) - { - // check accessed and dirty bits - assert(user_l3pt[addr/PGSIZE] & PTE_A); - uintptr_t sstatus = set_csr(sstatus, SSTATUS_SUM); - if (memcmp((void*)addr, uva2kva(addr), PGSIZE)) { - assert(user_l3pt[addr/PGSIZE] & PTE_D); - memcpy((void*)addr, uva2kva(addr), PGSIZE); - } - write_csr(sstatus, sstatus); - - user_mapping[addr/PGSIZE].addr = 0; - - if (freelist_tail == 0) - freelist_head = freelist_tail = node; - else - { - freelist_tail->next = node; - freelist_tail = node; - } - } -} - -void handle_fault(uintptr_t addr, uintptr_t cause) -{ - assert(addr >= PGSIZE && addr < MAX_TEST_PAGES * PGSIZE); - addr = addr/PGSIZE*PGSIZE; - - if (user_l3pt[addr/PGSIZE]) { - if (!(user_l3pt[addr/PGSIZE] & PTE_A)) { - user_l3pt[addr/PGSIZE] |= PTE_A; - } else { - assert(!(user_l3pt[addr/PGSIZE] & PTE_D) && cause == CAUSE_STORE_PAGE_FAULT); - user_l3pt[addr/PGSIZE] |= PTE_D; - } - flush_page(addr); - return; - } - - freelist_t* node = freelist_head; - assert(node); - freelist_head = node->next; - if (freelist_head == freelist_tail) - freelist_tail = 0; - - uintptr_t new_pte = (node->addr >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_W | PTE_X; - user_l3pt[addr/PGSIZE] = new_pte | PTE_A | PTE_D; - flush_page(addr); - - assert(user_mapping[addr/PGSIZE].addr == 0); - user_mapping[addr/PGSIZE] = *node; - - uintptr_t sstatus = set_csr(sstatus, SSTATUS_SUM); - memcpy((void*)addr, uva2kva(addr), PGSIZE); - write_csr(sstatus, sstatus); - - user_l3pt[addr/PGSIZE] = new_pte; - flush_page(addr); - - __builtin___clear_cache(0,0); -} - -void handle_trap(trapframe_t* tf) -{ - if (tf->cause == CAUSE_USER_ECALL) - { - int n = tf->gpr[10]; - - for (long i = 1; i < MAX_TEST_PAGES; i++) - evict(i*PGSIZE); - - terminate(n); - } - else if (tf->cause == CAUSE_ILLEGAL_INSTRUCTION) - { - assert(tf->epc % 4 == 0); - - int* fssr; - asm ("jal %0, 1f; fssr x0; 1:" : "=r"(fssr)); - - if (*(int*)tf->epc == *fssr) - terminate(1); // FP test on non-FP hardware. "succeed." - else - assert(!"illegal instruction"); - tf->epc += 4; - } - else if (tf->cause == CAUSE_FETCH_PAGE_FAULT || tf->cause == CAUSE_LOAD_PAGE_FAULT || tf->cause == CAUSE_STORE_PAGE_FAULT) - handle_fault(tf->badvaddr, tf->cause); - else - assert(!"unexpected exception"); - - pop_tf(tf); -} - -static void coherence_torture() -{ - // cause coherence misses without affecting program semantics - unsigned int random = ENTROPY; - while (1) { - uintptr_t paddr = DRAM_BASE + ((random % (2 * (MAX_TEST_PAGES + 1) * PGSIZE)) & -4); -#ifdef __riscv_atomic - if (random & 1) // perform a no-op write - asm volatile ("amoadd.w zero, zero, (%0)" :: "r"(paddr)); - else // perform a read -#endif - asm volatile ("lw zero, (%0)" :: "r"(paddr)); - random = lfsr63(random); - } -} - -void vm_boot(uintptr_t test_addr) -{ - unsigned int random = ENTROPY; - if (read_csr(mhartid) > 0) - coherence_torture(); - - _Static_assert(SIZEOF_TRAPFRAME_T == sizeof(trapframe_t), "???"); - -#if (MAX_TEST_PAGES > PTES_PER_PT) || (DRAM_BASE % MEGAPAGE_SIZE) != 0 -# error -#endif - // map user to lowermost megapage - l1pt[0] = ((pte_t)user_l2pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V; - // map kernel to uppermost megapage -#if __riscv_xlen == 64 - l1pt[PTES_PER_PT-1] = ((pte_t)kernel_l2pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V; - kernel_l2pt[PTES_PER_PT-1] = (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D; - user_l2pt[0] = ((pte_t)user_l3pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V; - uintptr_t vm_choice = SATP_MODE_SV39; -#else - l1pt[PTES_PER_PT-1] = (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D; - uintptr_t vm_choice = SATP_MODE_SV32; -#endif - write_csr(satp, ((uintptr_t)l1pt >> PGSHIFT) | - (vm_choice * (SATP_MODE & ~(SATP_MODE<<1)))); - - // Set up PMPs if present, ignoring illegal instruction trap if not. - uintptr_t pmpc = PMP_NAPOT | PMP_R | PMP_W | PMP_X; - asm volatile ("la t0, 1f\n\t" - "csrrw t0, mtvec, t0\n\t" - "csrw pmpaddr0, %1\n\t" - "csrw pmpcfg0, %0\n\t" - ".align 2\n\t" - "1:" - : : "r" (pmpc), "r" (-1UL) : "t0"); - - // set up supervisor trap handling - write_csr(stvec, pa2kva(trap_entry)); - write_csr(sscratch, pa2kva(read_csr(mscratch))); - write_csr(medeleg, - (1 << CAUSE_USER_ECALL) | - (1 << CAUSE_FETCH_PAGE_FAULT) | - (1 << CAUSE_LOAD_PAGE_FAULT) | - (1 << CAUSE_STORE_PAGE_FAULT)); - // FPU on; accelerator on; allow supervisor access to user memory access - write_csr(mstatus, MSTATUS_FS | MSTATUS_XS); - write_csr(mie, 0); - - random = 1 + (random % MAX_TEST_PAGES); - freelist_head = pa2kva((void*)&freelist_nodes[0]); - freelist_tail = pa2kva(&freelist_nodes[MAX_TEST_PAGES-1]); - for (long i = 0; i < MAX_TEST_PAGES; i++) - { - freelist_nodes[i].addr = DRAM_BASE + (MAX_TEST_PAGES + random)*PGSIZE; - freelist_nodes[i].next = pa2kva(&freelist_nodes[i+1]); - random = LFSR_NEXT(random); - } - freelist_nodes[MAX_TEST_PAGES-1].next = 0; - - trapframe_t tf; - memset(&tf, 0, sizeof(tf)); - tf.epc = test_addr - DRAM_BASE; - pop_tf(&tf); -} diff --git a/tests/wally-riscv-arch-test/riscv-test-env/verify.sh b/tests/wally-riscv-arch-test/riscv-test-env/verify.sh index f69a4c63..54385498 100755 --- a/tests/wally-riscv-arch-test/riscv-test-env/verify.sh +++ b/tests/wally-riscv-arch-test/riscv-test-env/verify.sh @@ -28,7 +28,8 @@ do echo -e "Check $(printf %-24s ${stub}) \e[33m ... IGNORE \e[39m" continue fi - diff --ignore-case --strip-trailing-cr ${ref} ${sig} &> /dev/null + # KMG: changed diff snippet to a grep that will strip comments with '//' and '#' out of the reference file + diff --ignore-case --ignore-trailing-space --strip-trailing-cr <(grep -o '^[^//#]*' ${ref}) ${sig} &> /dev/null if [ $? == 0 ] then echo -e "\e[32m ... OK \e[39m" diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/Makefile.include b/tests/wally-riscv-arch-test/riscv-test-suite/Makefile.include index 35ca5418..ae84be74 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/Makefile.include +++ b/tests/wally-riscv-arch-test/riscv-test-suite/Makefile.include @@ -63,8 +63,9 @@ copy: $(info !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!) $(info <<<<<<<<<<<<<<<<<<<<<<<<<<<< COPYING REFERENCES WITHOUT SIMULATING >>>>>>>>>>>>>>>>>>>>>>>>>>>>) $(info !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!) - $(V) echo "Copying References without simulating" - $(V) for test in $(target_tests_nosim); do cp $(ref_dir)/$$test.reference_output $(work_dir_isa)/$$test.signature.output; done + $(V) echo "Copying References without simulating for the following tests:" + $(V) echo $(target_tests_nosim) + $(V) for test in $(target_tests_nosim); do grep -o '^[^//#]*' $(ref_dir)/$$test.reference_output > $(work_dir_isa)/$$test.signature.output; done compile: $(combined_elf) run: $(target_log) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/Makefile b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/Makefile deleted file mode 100644 index b9410d41..00000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -include ../../Makefile.include - -$(eval $(call compile_template,-march=rv32e -mabi=ilp32e -DXLEN=$(XLEN))) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/Makefrag deleted file mode 100644 index b7c5692a..00000000 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/Makefrag +++ /dev/null @@ -1,73 +0,0 @@ -# RISC-V Architecture Test RV32E Makefrag -# -# Copyright (c) 2017, Codasip Ltd. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# * Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd. nor the -# names of its contributors may be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY -# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Description: Makefrag for RV32E architectural tests - -rv32e_sc_tests = \ - add-01 \ - addi-01 \ - and-01 \ - andi-01 \ - auipc-01 \ - beq-01 \ - bge-01 \ - bgeu-01 \ - blt-01 \ - bltu-01 \ - bne-01 \ - jal-01 \ - jalr-01 \ - lb-align-01 \ - lbu-align-01 \ - lh-align-01 \ - lhu-align-01 \ - lui-01 \ - lw-align-01 \ - or-01 \ - ori-01 \ - sb-align-01 \ - sh-align-01 \ - sll-01 \ - slli-01 \ - slt-01 \ - slti-01 \ - sltiu-01 \ - sltu-01 \ - sra-01 \ - srai-01 \ - srl-01 \ - srli-01 \ - sub-01 \ - sw-align-01 \ - xor-01 \ - xori-01 - - - -rv32e_tests = $(addsuffix .elf, $(rv32e_sc_tests)) - -target_tests += $(rv32e_tests) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefrag index fbd60d30..eda62507 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefrag +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefrag @@ -29,10 +29,10 @@ rv32i_sc_tests = \ WALLY-ADD \ - WALLY-SUB \ - WALLY-SLT \ + WALLY-SLT \ WALLY-SLTU \ - WALLY-XOR + WALLY-SUB \ + WALLY-XOR rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests)) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/add-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-add-01.reference_output similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/add-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-add-01.reference_output index 4d18d6a9..b364d3f1 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/add-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-add-01.reference_output @@ -581,3 +581,4 @@ ddddddde 3333e836 e000001f f0000003 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/addi-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-addi-01.reference_output similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/addi-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-addi-01.reference_output index 752d5262..1052749c 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/addi-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-addi-01.reference_output @@ -559,3 +559,6 @@ aaaaadde aaaaaab0 c000003f fdffffff +00000000 +00000000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/and-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-and-01.reference_output similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/and-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-and-01.reference_output diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/andi-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-andi-01.reference_output similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/andi-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-andi-01.reference_output index 1863cd1f..aefc28d9 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/andi-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-andi-01.reference_output @@ -552,3 +552,5 @@ aaaaaa80 00000002 00000002 00000555 +00000000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/auipc-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-auipc-01.reference_output similarity index 98% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/auipc-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-auipc-01.reference_output index ebf77d35..5f432d03 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/auipc-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-auipc-01.reference_output @@ -61,3 +61,4 @@ aaaa9000 33333000 00005000 ff7ff000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/beq-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-beq-01.reference_output similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/beq-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-beq-01.reference_output index 92f1ee6d..becb2fbf 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/beq-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-beq-01.reference_output @@ -588,3 +588,5 @@ 00000002 00000002 00000002 +00000000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/bge-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bge-01.reference_output similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/bge-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bge-01.reference_output index cf462405..fe7d8af3 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/bge-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bge-01.reference_output @@ -584,3 +584,5 @@ 00000002 00000003 00000001 +00000000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/bgeu-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bgeu-01.reference_output similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/bgeu-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bgeu-01.reference_output diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/blt-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-blt-01.reference_output similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/blt-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-blt-01.reference_output index f0e22e7c..cdd9263f 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/blt-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-blt-01.reference_output @@ -584,3 +584,5 @@ 00000002 00000002 00000002 +00000000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/bltu-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bltu-01.reference_output similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/bltu-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bltu-01.reference_output index 4498f93a..8776eb6a 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/bltu-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bltu-01.reference_output @@ -725,3 +725,4 @@ 00000001 00000003 00000003 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/bne-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bne-01.reference_output similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/bne-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bne-01.reference_output index 7f8a8e6c..b537bf36 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/bne-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-bne-01.reference_output @@ -583,3 +583,6 @@ 00000003 00000001 00000001 +00000000 +00000000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/jal-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-jal-01.reference_output similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/jal-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-jal-01.reference_output diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/jalr-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-jalr-01.reference_output similarity index 96% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/jalr-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-jalr-01.reference_output index a05f0b1d..0793fe3a 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/jalr-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-jalr-01.reference_output @@ -25,3 +25,4 @@ 00000017 00000017 00000017 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/lb-align-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lb-align-01.reference_output similarity index 90% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/lb-align-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lb-align-01.reference_output index 246a4492..4f84c048 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/lb-align-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lb-align-01.reference_output @@ -16,3 +16,5 @@ ffffffba ffffffba ffffffba ffffffba +00000000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/lbu-align-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lbu-align-01.reference_output similarity index 85% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/lbu-align-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lbu-align-01.reference_output index ddd4233b..74d8f091 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/lbu-align-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lbu-align-01.reference_output @@ -15,3 +15,6 @@ 000000ba 000000ba 000000ba +00000000 +00000000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/lh-align-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lh-align-01.reference_output similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/lh-align-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lh-align-01.reference_output diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/lhu-align-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lhu-align-01.reference_output similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/lhu-align-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lhu-align-01.reference_output diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/lui-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lui-01.reference_output similarity index 98% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/lui-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lui-01.reference_output index def19117..0e37658c 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/lui-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lui-01.reference_output @@ -61,3 +61,4 @@ aaaa9000 33333000 00005000 fff7f000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/lw-align-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lw-align-01.reference_output similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/lw-align-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-lw-align-01.reference_output diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/or-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-or-01.reference_output similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/or-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-or-01.reference_output index ea67773d..ee838bce 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/or-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-or-01.reference_output @@ -587,3 +587,6 @@ efffffff feffffff ff7fffff ffffffff +00000000 +00000000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/ori-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-ori-01.reference_output similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/ori-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-ori-01.reference_output index f97d2339..e092fd1a 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/ori-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-ori-01.reference_output @@ -555,3 +555,6 @@ aaaaaeef aaaaabbe aaaaaaae 7fffffff +00000000 +00000000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/sb-align-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sb-align-01.reference_output similarity index 97% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/sb-align-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sb-align-01.reference_output index cd1d694f..9c4bc821 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/sb-align-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sb-align-01.reference_output @@ -76,3 +76,5 @@ deadbe80 deadbe20 deadbe04 deadbe02 +00000000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/sh-align-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sh-align-01.reference_output similarity index 98% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/sh-align-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sh-align-01.reference_output index fcfc68ec..7e989c34 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/sh-align-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sh-align-01.reference_output @@ -69,3 +69,4 @@ dead0008 dead0004 dead0002 deadffff +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/sll-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sll-01.reference_output similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/sll-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sll-01.reference_output diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/slli-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-slli-01.reference_output similarity index 96% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/slli-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-slli-01.reference_output index 242ca070..88365468 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/slli-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-slli-01.reference_output @@ -87,3 +87,6 @@ cccccc00 28000000 ffffff80 ffff0000 +00000000 +00000000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/slt-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-slt-01.reference_output similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/slt-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-slt-01.reference_output index 211acb80..eb7f0442 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/slt-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-slt-01.reference_output @@ -579,3 +579,6 @@ 00000000 00000001 00000000 +00000000 +00000000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/slti-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-slti-01.reference_output similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/slti-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-slti-01.reference_output index 65bf06a2..a0b62cb2 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/slti-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-slti-01.reference_output @@ -559,3 +559,6 @@ 00000001 00000001 00000001 +00000000 +00000000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/sltiu-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sltiu-01.reference_output similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/sltiu-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sltiu-01.reference_output index 8bef9035..be272395 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/sltiu-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sltiu-01.reference_output @@ -695,3 +695,6 @@ 00000001 00000000 00000000 +00000000 +00000000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/sltu-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sltu-01.reference_output similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/sltu-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sltu-01.reference_output index 95fdde41..a0e45d5a 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/sltu-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sltu-01.reference_output @@ -720,3 +720,5 @@ 00000000 00000001 00000001 +00000000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/sra-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sra-01.reference_output similarity index 97% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/sra-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sra-01.reference_output index 76d4a21d..40928fa2 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/sra-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sra-01.reference_output @@ -88,3 +88,5 @@ fffffffd 00000000 fffeffff fffeffff +00000000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/srai-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-srai-01.reference_output similarity index 98% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/srai-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-srai-01.reference_output index d0482c92..23cef333 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/srai-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-srai-01.reference_output @@ -85,3 +85,4 @@ ffffffff 00000ccc ffffffff ffffffbf +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/srl-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-srl-01.reference_output similarity index 96% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/srl-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-srl-01.reference_output index 1ff02aae..6cdc318c 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/srl-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-srl-01.reference_output @@ -87,3 +87,6 @@ fffffffb 00000007 0003bfff 0ffdffff +00000000 +00000000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/srli-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-srli-01.reference_output similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/srli-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-srli-01.reference_output diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/sub-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sub-01.reference_output similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/sub-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sub-01.reference_output diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/sw-align-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sw-align-01.reference_output similarity index 100% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/sw-align-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-sw-align-01.reference_output diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/xor-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-xor-01.reference_output similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/xor-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-xor-01.reference_output index dcd028b8..848bc88e 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/xor-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-xor-01.reference_output @@ -581,3 +581,4 @@ bffffbff dfffdfff effffffe 00050000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/xori-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-xori-01.reference_output similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/xori-01.reference_output rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-xori-01.reference_output index 72862a59..a17012ec 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/references/xori-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/E-xori-01.reference_output @@ -557,3 +557,4 @@ aaaaa99e aaaaaaac fffefdff ffff7fff +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/add-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-add-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/add-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-add-01.S index 9336eccf..4abf30fd 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/add-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-add-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the add instruction of the RISC-V E extension for the add covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/addi-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-addi-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/addi-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-addi-01.S index 83974840..87ce8463 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/addi-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-addi-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the addi instruction of the RISC-V E extension for the addi covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/and-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-and-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/and-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-and-01.S index 41d5e406..dca83d0f 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/and-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-and-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the and instruction of the RISC-V E extension for the and covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/andi-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-andi-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/andi-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-andi-01.S index 3dcd009d..2114d6ae 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/andi-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-andi-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the andi instruction of the RISC-V E extension for the andi covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/auipc-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-auipc-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/auipc-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-auipc-01.S index 87eed4cd..517a4b8d 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/auipc-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-auipc-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the auipc instruction of the RISC-V E extension for the auipc covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/beq-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-beq-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/beq-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-beq-01.S index a8a75c63..94640246 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/beq-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-beq-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the beq instruction of the RISC-V E extension for the beq covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/bge-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bge-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/bge-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bge-01.S index e468772c..d8cd0047 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/bge-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bge-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the bge instruction of the RISC-V E extension for the bge covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/bgeu-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bgeu-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/bgeu-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bgeu-01.S index 2b9d3876..43bf2ec7 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/bgeu-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bgeu-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the bgeu instruction of the RISC-V E extension for the bgeu covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/blt-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-blt-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/blt-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-blt-01.S index 886a17eb..a23350a4 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/blt-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-blt-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the blt instruction of the RISC-V E extension for the blt covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/bltu-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bltu-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/bltu-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bltu-01.S index f8042b14..e6e5b69a 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/bltu-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bltu-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the bltu instruction of the RISC-V E extension for the bltu covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/bne-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bne-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/bne-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bne-01.S index 58a333c0..92ccd2b4 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/bne-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-bne-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the bne instruction of the RISC-V E extension for the bne covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/jal-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-jal-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/jal-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-jal-01.S index b3870318..2fd3e9e2 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/jal-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-jal-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the jal instruction of the RISC-V E extension for the jal covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/jalr-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-jalr-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/jalr-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-jalr-01.S index 2b58baf1..c8ac3476 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/jalr-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-jalr-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the jalr instruction of the RISC-V E extension for the jalr covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/lb-align-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lb-align-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/lb-align-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lb-align-01.S index 2b50abf2..d42f83cc 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/lb-align-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lb-align-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the lb instruction of the RISC-V E extension for the lb-align covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/lbu-align-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lbu-align-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/lbu-align-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lbu-align-01.S index 0e73a681..bc2c0527 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/lbu-align-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lbu-align-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the lbu instruction of the RISC-V E extension for the lbu-align covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/lh-align-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lh-align-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/lh-align-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lh-align-01.S index 51627333..e16cb695 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/lh-align-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lh-align-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the lh instruction of the RISC-V E extension for the lh-align covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/lhu-align-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lhu-align-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/lhu-align-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lhu-align-01.S index 8d4c28e7..9e4427ca 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/lhu-align-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lhu-align-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the lhu instruction of the RISC-V E extension for the lhu-align covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/lui-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lui-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/lui-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lui-01.S index 81fbc741..f1257005 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/lui-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lui-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the lui instruction of the RISC-V E extension for the lui covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/lw-align-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lw-align-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/lw-align-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lw-align-01.S index a8dafa82..e1f368a9 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/lw-align-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-lw-align-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the lw instruction of the RISC-V E extension for the lw-align covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/or-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-or-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/or-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-or-01.S index e5032b05..19378500 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/or-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-or-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the or instruction of the RISC-V E extension for the or covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/ori-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-ori-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/ori-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-ori-01.S index fa55b6bf..3c807886 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/ori-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-ori-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the ori instruction of the RISC-V E extension for the ori covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sb-align-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sb-align-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sb-align-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sb-align-01.S index 2684e12d..3eaf9072 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sb-align-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sb-align-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the sb instruction of the RISC-V E extension for the sb-align covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sh-align-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sh-align-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sh-align-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sh-align-01.S index 6dd42781..86d7c278 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sh-align-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sh-align-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the sh instruction of the RISC-V E extension for the sh-align covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sll-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sll-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sll-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sll-01.S index af03abc7..f219b7af 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sll-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sll-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the sll instruction of the RISC-V E extension for the sll covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/slli-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slli-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/slli-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slli-01.S index 13226b35..754c14a5 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/slli-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slli-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the slli instruction of the RISC-V E extension for the slli covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/slt-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slt-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/slt-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slt-01.S index 9a17362b..f7c57a55 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/slt-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slt-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the slt instruction of the RISC-V E extension for the slt covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/slti-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slti-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/slti-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slti-01.S index 8c53c538..c0a3fecc 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/slti-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-slti-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the slti instruction of the RISC-V E extension for the slti covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sltiu-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sltiu-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sltiu-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sltiu-01.S index 65b2c2a8..79336c4f 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sltiu-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sltiu-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the sltiu instruction of the RISC-V E extension for the sltiu covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sltu-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sltu-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sltu-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sltu-01.S index 999007f7..b28398c3 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sltu-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sltu-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the sltu instruction of the RISC-V E extension for the sltu covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sra-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sra-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sra-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sra-01.S index 98801fb4..7e3e8c25 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sra-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sra-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the sra instruction of the RISC-V E extension for the sra covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/srai-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srai-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/srai-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srai-01.S index 7e5a571a..e87f2b74 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/srai-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srai-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the srai instruction of the RISC-V E extension for the srai covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/srl-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srl-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/srl-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srl-01.S index b392ecba..80f27c5f 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/srl-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srl-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the srl instruction of the RISC-V E extension for the srl covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/srli-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srli-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/srli-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srli-01.S index d47f805a..8ecc2f5d 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/srli-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-srli-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the srli instruction of the RISC-V E extension for the srli covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sub-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sub-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sub-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sub-01.S index e09411fd..60ce1b73 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sub-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sub-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the sub instruction of the RISC-V E extension for the sub covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sw-align-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sw-align-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sw-align-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sw-align-01.S index aae0ca47..71dd41b8 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/sw-align-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-sw-align-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the sw instruction of the RISC-V E extension for the sw-align covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/xor-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-xor-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/xor-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-xor-01.S index cb30a261..41fa0ac9 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/xor-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-xor-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the xor instruction of the RISC-V E extension for the xor covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/xori-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-xori-01.S similarity index 99% rename from tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/xori-01.S rename to tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-xori-01.S index 00d85cb1..cc3f509f 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/E/src/xori-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/E-xori-01.S @@ -16,6 +16,7 @@ // // This assembly file tests the xori instruction of the RISC-V E extension for the xori covergroup. // +#define RVTEST_E #include "model_test.h" #include "arch_test.h" RVTEST_ISA("RV32E") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag index aa30cdc7..e8c00028 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag @@ -31,7 +31,9 @@ rv64i_sc_tests = \ WALLY-MMU-SV39 \ WALLY-MMU-SV48 \ WALLY-PMP \ - WALLY-minfo-01 + WALLY-minfo-01 \ + WALLY-CSR-permission-s-01 \ + WALLY-CSR-permission-u-01 target_tests_nosim = WALLY-PMA \ diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-CSR-permission-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-CSR-permission-s-01.reference_output new file mode 100644 index 00000000..811bfe7c --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-CSR-permission-s-01.reference_output @@ -0,0 +1,1024 @@ +0000000b # Test 5.2.3.6: ecall from going to S mode from M mode +00000000 +00000002 # S mode write to mvendorid with illegal instruction +00000000 +00000002 # S mode read from mvendorid with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to marchid with illegal instruction +00000000 +00000002 # S mode read from marchid with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mimpid with illegal instruction +00000000 +00000002 # S mode read from mimpid with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhartid with illegal instruction +00000000 +00000002 # S mode read from mhartid with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mstatus with illegal instruction +00000000 +00000002 # S mode read from mstatus with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to misa with illegal instruction +00000000 +00000002 # S mode read from misa with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to medeleg with illegal instruction +00000000 +00000002 # S mode read from medeleg with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mideleg with illegal instruction +00000000 +00000002 # S mode read from mideleg with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mie with illegal instruction +00000000 +00000002 # S mode read from mie with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mtvec with illegal instruction +00000000 +00000002 # S mode read from mtvec with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mcounteren with illegal instruction +00000000 +00000002 # S mode read from mcounteren with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mscratch with illegal instruction +00000000 +00000002 # S mode read from mscratch with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mepc with illegal instruction +00000000 +00000002 # S mode read from mepc with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mcause with illegal instruction +00000000 +00000002 # S mode read from mcause with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mtval with illegal instruction +00000000 +00000002 # S mode read from mtval with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mip with illegal instruction +00000000 +00000002 # S mode read from mip with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpcfg0 with illegal instruction +00000000 +00000002 # S mode read from pmpcfg0 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpcfg2 with illegal instruction +00000000 +00000002 # S mode read from pmpcfg2 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr0 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr0 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr1 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr1 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr2 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr2 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr3 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr3 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr4 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr4 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr5 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr5 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr6 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr6 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr7 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr7 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr8 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr8 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr9 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr9 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr10 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr10 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr11 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr11 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr12 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr12 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr13 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr13 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr14 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr14 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to pmpaddr15 with illegal instruction +00000000 +00000002 # S mode read from pmpaddr15 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mcycle with illegal instruction +00000000 +00000002 # S mode read from mcycle with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to minstret with illegal instruction +00000000 +00000002 # S mode read from minstret with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter3 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter3 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter4 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter4 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter5 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter5 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter6 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter6 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter7 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter7 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter8 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter8 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter9 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter9 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter10 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter10 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter11 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter11 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter12 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter12 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter13 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter13 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter14 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter14 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter15 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter15 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter16 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter16 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter17 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter17 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter18 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter18 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter19 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter19 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter20 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter20 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter21 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter21 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter22 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter22 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter23 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter23 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter24 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter24 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter25 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter25 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter26 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter26 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter27 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter27 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter28 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter28 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter29 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter29 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter30 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter30 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmcounter31 with illegal instruction +00000000 +00000002 # S mode read from mhpmcounter31 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mcountinhibit with illegal instruction +00000000 +00000002 # S mode read from mcountinhibit with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent3 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent3 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent4 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent4 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent5 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent5 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent6 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent6 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent7 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent7 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent8 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent8 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent9 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent9 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent10 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent10 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent11 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent11 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent12 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent12 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent13 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent13 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent14 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent14 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent15 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent15 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent16 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent16 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent17 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent17 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent18 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent18 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent19 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent19 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent20 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent20 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent21 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent21 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent22 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent22 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent23 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent23 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent24 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent24 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent25 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent25 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent26 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent26 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent27 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent27 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent28 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent28 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent29 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent29 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent30 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent30 with illegal instruction +00000000 +00000bad +00000000 +00000002 # S mode write to mhpmevent31 with illegal instruction +00000000 +00000002 # S mode read from mhpmevent31 with illegal instruction +00000000 +00000bad +00000000 +00000009 # ecall from terminating tess from S mode +00000000 +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-CSR-permission-u-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-CSR-permission-u-01.reference_output new file mode 100644 index 00000000..c8cd62ab --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-CSR-permission-u-01.reference_output @@ -0,0 +1,1024 @@ +0000000b # Test 5.2.3.6: ecall from going to U mode from M mode +00000000 +00000002 # U mode write to sstatus with illegal instruction +00000000 +00000002 # U mode read from sstatus with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to sie with illegal instruction +00000000 +00000002 # U mode read from sie with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to stvec with illegal instruction +00000000 +00000002 # U mode read from stvec with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to scounteren with illegal instruction +00000000 +00000002 # U mode read from scounteren with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to sscratch with illegal instruction +00000000 +00000002 # U mode read from sscratch with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to sepc with illegal instruction +00000000 +00000002 # U mode read from sepc with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to scause with illegal instruction +00000000 +00000002 # U mode read from scause with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to stval with illegal instruction +00000000 +00000002 # U mode read from stval with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to sip with illegal instruction +00000000 +00000002 # U mode read from sip with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to satp with illegal instruction +00000000 +00000002 # U mode read from satp with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mvendorid with illegal instruction +00000000 +00000002 # U mode read from mvendorid with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to marchid with illegal instruction +00000000 +00000002 # U mode read from marchid with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mimpid with illegal instruction +00000000 +00000002 # U mode read from mimpid with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhartid with illegal instruction +00000000 +00000002 # U mode read from mhartid with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mstatus with illegal instruction +00000000 +00000002 # U mode read from mstatus with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to misa with illegal instruction +00000000 +00000002 # U mode read from misa with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to medeleg with illegal instruction +00000000 +00000002 # U mode read from medeleg with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mideleg with illegal instruction +00000000 +00000002 # U mode read from mideleg with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mie with illegal instruction +00000000 +00000002 # U mode read from mie with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mtvec with illegal instruction +00000000 +00000002 # U mode read from mtvec with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mcounteren with illegal instruction +00000000 +00000002 # U mode read from mcounteren with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mscratch with illegal instruction +00000000 +00000002 # U mode read from mscratch with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mepc with illegal instruction +00000000 +00000002 # U mode read from mepc with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mcause with illegal instruction +00000000 +00000002 # U mode read from mcause with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mtval with illegal instruction +00000000 +00000002 # U mode read from mtval with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mip with illegal instruction +00000000 +00000002 # U mode read from mip with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpcfg0 with illegal instruction +00000000 +00000002 # U mode read from pmpcfg0 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpcfg2 with illegal instruction +00000000 +00000002 # U mode read from pmpcfg2 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr0 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr0 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr1 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr1 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr2 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr2 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr3 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr3 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr4 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr4 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr5 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr5 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr6 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr6 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr7 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr7 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr8 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr8 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr9 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr9 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr10 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr10 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr11 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr11 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr12 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr12 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr13 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr13 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr14 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr14 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to pmpaddr15 with illegal instruction +00000000 +00000002 # U mode read from pmpaddr15 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mcycle with illegal instruction +00000000 +00000002 # U mode read from mcycle with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to minstret with illegal instruction +00000000 +00000002 # U mode read from minstret with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter3 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter3 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter4 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter4 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter5 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter5 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter6 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter6 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter7 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter7 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter8 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter8 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter9 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter9 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter10 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter10 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter11 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter11 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter12 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter12 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter13 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter13 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter14 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter14 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter15 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter15 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter16 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter16 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter17 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter17 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter18 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter18 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter19 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter19 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter20 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter20 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter21 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter21 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter22 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter22 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter23 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter23 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter24 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter24 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter25 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter25 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter26 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter26 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter27 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter27 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter28 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter28 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter29 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter29 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter30 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter30 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmcounter31 with illegal instruction +00000000 +00000002 # U mode read from mhpmcounter31 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mcountinhibit with illegal instruction +00000000 +00000002 # U mode read from mcountinhibit with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent3 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent3 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent4 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent4 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent5 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent5 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent6 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent6 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent7 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent7 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent8 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent8 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent9 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent9 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent10 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent10 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent11 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent11 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent12 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent12 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent13 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent13 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent14 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent14 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent15 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent15 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent16 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent16 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent17 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent17 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent18 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent18 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent19 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent19 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent20 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent20 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent21 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent21 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent22 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent22 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent23 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent23 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent24 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent24 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent25 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent25 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent26 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent26 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent27 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent27 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent28 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent28 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent29 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent29 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent30 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent30 with illegal instruction +00000000 +00000bad +00000000 +00000002 # U mode write to mhpmevent31 with illegal instruction +00000000 +00000002 # U mode read from mhpmevent31 with illegal instruction +00000000 +00000bad +00000000 +00000008 # ecall from terminating tests in U mode +00000000 +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MMU-SV39.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MMU-SV39.reference_output index 492379de..b0f6ca4c 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MMU-SV39.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MMU-SV39.reference_output @@ -1,104 +1,104 @@ -0000000b +0000000b # Test 12.3.1.1.3: ecall from going to S mode from M mode 00000000 -beef0000 +beef0000 # 7 read test successes 0000dead -beef0055 +beef0055 # read 2 0880dead -beef0033 +beef0033 # read 3 0990dead -beef0077 +beef0077 # read 4 0110dead -beef0099 +beef0099 # read 5 0220dead -beef0440 +beef0440 # read 6 0330dead -beef0bb0 +beef0bb0 # read 7 0440dead -beef0000 +beef0000 # Test 12.3.1.1.4: 3 read test successes 0000dead -beef0055 +beef0055 # read 2 0880dead -beef0099 +beef0099 # read 3 0220dead -0000000d +0000000d # Test 12.3.1.2.1: 2 read tests with page fault 00000000 00000bad 00000000 -0000000d +0000000d # read 2 00000000 00000bad 00000000 -0000000d +0000000d # Test 12.3.1.2.2: read test with page fault 00000000 00000bad 00000000 -0000000f +0000000f # Test 12.3.1.2.3: write test with page fault 00000000 -0000000d +0000000d # Test 12.3.1.2.4: read test with page fault 00000000 00000bad 00000000 -0000000d +0000000d # Test 12.3.1.2.5: 2 read tests with page faults 00000000 00000bad 00000000 -0000000d +0000000d # read 2 00000000 00000bad 00000000 -00000111 +00000111 # Test 12.3.1.3.1: execute test success 00000000 -00000009 +00000009 # ecall from going to U mode from S mode 00000000 -0000000d +0000000d # read test with page fault 00000000 00000bad 00000000 -0000000c +0000000c # execute test with page fault 00000000 00000bad 00000000 -beef0033 +beef0033 # Test 12.3.1.3.2: read test success 0990dead -00000008 +00000008 # ecall from going to S mode from U mode 00000000 -beef0077 +beef0077 # read test success 0110dead -0000000c +0000000c # execute test with page fault 00000000 00000bad 00000000 -0000000d +0000000d # read test with page fault 00000000 00000bad 00000000 -0000000d +0000000d # Test 12.3.1.3.3: read test with page fault 00000000 00000bad 00000000 -beef0440 +beef0440 # read test success 0330dead -beef0110 +beef0110 # Test 12.3.1.3.4: read test success 0440dead -0000000f +0000000f # write test with page fault 00000000 -0000000c +0000000c # Test 12.3.1.3.5: execute test with page fault 00000000 00000bad 00000000 -0000000f +0000000f # Test 12.3.1.3.6: write test with page fault 00000000 -0000000d +0000000d # read test with page fault 00000000 00000bad 00000000 -0000000f +0000000f # Test 12.3.1.3.7: write test with page fault 00000000 -beef0bb0 +beef0bb0 # read test success 0440dead -00000009 +00000009 # ecall from test termination from S mode 00000000 -deadbeef +deadbeef # rest of the output space deadbeef deadbeef deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MMU-SV48.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MMU-SV48.reference_output index 68a13c25..1d4ff8e3 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MMU-SV48.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MMU-SV48.reference_output @@ -1,112 +1,112 @@ -0000000b +0000000b # Test 12.3.1.1.3: ecall from going to S mode from M mode 00000000 -beef0cc0 +beef0cc0 # 8 read test successes 0ee0dead -beef0000 +beef0000 # read 2 0000dead -beef0055 +beef0055 # read 3 0880dead -beef0033 +beef0033 # read 4 0990dead -beef0077 +beef0077 # read 5 0110dead -beef0099 +beef0099 # read 6 0220dead -beef0440 +beef0440 # read 7 0330dead -beef0bb0 +beef0bb0 # read 8 0440dead -beef0cc0 +beef0cc0 # Test 12.3.1.1.4: 4 read test successes 0ee0dead -beef0000 +beef0000 # read 2 0000dead -beef0055 +beef0055 # read 3 0880dead -beef0099 +beef0099 # read 4 0220dead -0000000d +0000000d # Test 12.3.1.2.1: 2 read tests with page fault 00000000 00000bad 00000000 -0000000d +0000000d # read 2 00000000 00000bad 00000000 -0000000d +0000000d # Test 12.3.1.2.2: read test with page fault 00000000 00000bad 00000000 -0000000f +0000000f # Test 12.3.1.2.3: write test with page fault 00000000 -0000000d +0000000d # Test 12.3.1.2.4: read test with page fault 00000000 00000bad 00000000 -0000000d +0000000d # Test 12.3.1.2.5: 3 read tests with page fault 00000000 00000bad 00000000 -0000000d +0000000d # read 2 00000000 00000bad 00000000 -0000000d +0000000d # read 3 00000000 00000bad 00000000 -00000111 +00000111 # Test 12.3.1.3.1: Execute test success 00000000 -00000009 +00000009 # ecall from going to U mode from S mode 00000000 -0000000d +0000000d # read test with page fault 00000000 00000bad 00000000 -0000000c +0000000c # execute test with page fault 00000000 00000bad 00000000 -beef0033 +beef0033 # Test 12.3.1.3.2: read test success 0990dead -00000008 +00000008 # ecall from going to S mode from U mode 00000000 -beef0077 +beef0077 # read test success 0110dead -0000000c +0000000c # execute test with page fault 00000000 00000bad 00000000 -0000000d +0000000d # read test with page fault` 00000000 00000bad 00000000 -0000000d +0000000d # Test 12.3.1.3.3: read test with page fault 00000000 00000bad 00000000 -beef0440 +beef0440 # read test success 0330dead -beef0110 +beef0110 # Test 12.3.1.3.4: read test success 0440dead -0000000f +0000000f # write test with page fault 00000000 -0000000c +0000000c # Test 12.3.1.3.5: executable test with page fault 00000000 00000bad 00000000 -0000000f +0000000f # Test 12.3.1.3.6: write test with page fault 00000000 -0000000d +0000000d # read test with page fault 00000000 00000bad 00000000 -0000000f +0000000f # Test 12.3.1.3.7: write test with page fault 00000000 -beef0bb0 +beef0bb0 # read test success 0440dead -00000009 +00000009 # ecall from test termination in S mode. 00000000 -deadbeef +deadbeef # rest of the output space deadbeef deadbeef deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMA.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMA.reference_output index 7ba4cff9..c8a68e8e 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMA.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMA.reference_output @@ -1,148 +1,148 @@ -beef00b4 -0000dead -beef00b5 +beef00b4 # Test 12.3.2.1: read 64 bits success in CLINT +0000dead # all of these read successes are also confirming successful writes +beef00b5 # read 32 bits success in CLINT (sign extended) ffffffff -000000b6 +000000b6 # read 16 bits success in CLINT 00000000 -ffffffb7 +ffffffb7 # read 8 bits success in CLINT (sign extended) ffffffff -00000001 +00000001 # execute test with access fault in CLINT 00000000 00000bad 00000000 -00000007 +00000007 # write 64 bits with access fault in PLIC 00000000 -00000005 +00000005 # read 64 bits with access fault in PLIC 00000000 00000bad 00000000 -00000002 +00000002 # read 32 bits success in PLIC (confriming 32 bit write) 00000000 -00000007 +00000007 # write 16 bits with access fault in PLIC 00000000 -00000005 +00000005 # read 16 bits with access fault in PLIC 00000000 00000bad 00000000 -00000007 +00000007 # write 8 bits with access fault in PLIC 00000000 -00000005 +00000005 # read 8 bits with access fault in PLIC 00000000 00000bad 00000000 -00000001 +00000001 # execute test with access fault in PLIC 00000000 00000bad 00000000 -00000007 +00000007 # write 64 bits with access fault in UART 00000000 -00000005 +00000005 # read 64 bits with access fault in UART 00000000 00000bad 00000000 -00000007 +00000007 # write 32 bits with access fault in UART 00000000 -00000005 +00000005 # read 32 bits with access fault in UART 00000000 00000bad 00000000 -00000007 +00000007 # write 16 bits with access fault in UART 00000000 -00000005 +00000005 # read 16 bits with access fault in UART 00000000 00000bad 00000000 -ffffffbf +ffffffbf # read 8 bits success in UART (confirming 8 bit write) ffffffff -00000001 +00000001 # execute test with access fault in UART 00000000 00000bad 00000000 -00000007 +00000007 # write 64 bits with access fault in GPIO 00000000 -00000005 +00000005 # read 64 bits with access fault in GPIO 00000000 00000bad 00000000 -beef00c1 +beef00c1 # read 32 bits success in GPIO (confirming 32 bit write) ffffffff -00000007 +00000007 # write 16 bits with access fault in GPIO 00000000 -00000005 +00000005 # read 16 bits with access fault in GPIO 00000000 00000bad 00000000 -00000007 +00000007 # write 8 bits with access fault in GPIO 00000000 -00000005 +00000005 # read 8 bits with access fault in GPIO 00000000 00000bad 00000000 -00000001 +00000001 # execute test with access fault in GPIO 00000000 00000bad 00000000 -00000007 +00000007 # write test with access fault in random memory location 00000000 -00000005 +00000005 # read test with access fault in random memory location 00000000 00000bad 00000000 -00000001 +00000001 # execute test with access fault in random memory location 00000000 00000bad 00000000 -00000007 +00000007 # write test with access fault just after BOOTROM 00000000 -00000005 +00000005 # read test with access fault just after BOOTROM 00000000 00000bad 00000000 -00000001 +00000001 # execute test with access fault just after BOOTROM 00000000 00000bad 00000000 -00000007 +00000007 # write test with access fault just after CLINT 00000000 -00000005 +00000005 # read test with access fault just after CLINT 00000000 00000bad 00000000 -00000001 +00000001 # execute test with access fault just after CLINT 00000000 00000bad 00000000 -00000007 +00000007 # write test with access fault just after PLIC 00000000 -00000005 +00000005 # read test with access fault just after PLIC 00000000 00000bad 00000000 -00000001 +00000001 # execute test with access fault just after PLIC 00000000 00000bad 00000000 -00000007 +00000007 # write test with access fault just after UART 00000000 -00000005 +00000005 # read test with access fault just after UART 00000000 00000bad 00000000 -00000001 +00000001 # execute test with access fault just after UART 00000000 00000bad 00000000 -00000007 +00000007 # write test with access fault just after GPIO 00000000 -00000005 +00000005 # read test with access fault just after GPIO 00000000 00000bad 00000000 -00000001 +00000001 # execute test with access fault just after GPIO 00000000 00000bad 00000000 -0000000b +0000000b # ecall from terminating tests in M mode 00000000 deadbeef deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMP.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMP.reference_output index 931f8a16..ea5a0cb1 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMP.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PMP.reference_output @@ -1,58 +1,58 @@ -0fffffff +0fffffff # Test 12.3.2.2.1: writeback of value written to PMPADDR0 +00000000 +20040000 # writeback of value written to PMPADDR1 00000000 -20040000 +2004003f # writeback of value written to PMPADDR2 00000000 -2004003f +20040080 # writeback of value written to PMPADDR3 00000000 -20040080 +20040084 # writeback of value written to PMPADDR4 00000000 -20040084 +200400c0 # writeback of value written to PMPADDR5 00000000 -200400c0 +2004013f # writeback of value written to PMPADDR6 00000000 -2004013f +2fffffff # writeback of value written to PMPADDR15 00000000 -2fffffff -00000000 -0009001f +0009001f # writeback of value written to PMPCFG0 0018900c -00000000 +00000000 # writeback of value written to PMPCFG2 1f000000 -0009001f +0009001f # old value of PMPCFG0 after failed write to locked out region 0018900c -200400c0 +200400c0 # old value of PMPADDR5 after failed write to locked out region 00000000 -00000005 +00000005 # Test 12.3.2.2.2: read test with access fault to region with L=1, R=0 00000000 00000bad 00000000 -00600dbb +00600dbb # read test success from region with L=X=W=R=0 00000000 -0000000b +0000000b # Test 12.3.2.2.3: ecall from going to S mode from M mode 00000000 -00600d15 +00600d15 # read test success from RW range (confirming previous write) 00000000 -00600d02 +00600d02 # read test success from outside the edge of a read only range 00000000 -00600d12 +00600d12 # read test success from outside the other edge of a read only range 00000000 -00000007 +00000007 # write test with access fault in read only range 00000000 -00600daa +00600daa # read success from read only range 00000000 -00000007 +00000007 # write test with access fault in no-access range 00000000 -00000005 +00000005 # read test with access fault in no-access range 00000000 00000bad 00000000 -00000001 +00000001 # execute test with access fault in no-execute range 00000000 00000bad 00000000 -00000111 +00000111 # execute sucess when X=1 00000000 -00000009 +00000009 # ecall from terminating tests in S mode 00000000 deadbeef deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-minfo-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-minfo-01.reference_output index 880d5dc8..e37c3762 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-minfo-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-minfo-01.reference_output @@ -1,20 +1,20 @@ -00000002 +00000002 # Test 5.2.3.1: write to read-only CSR failed with illegal instruction 00000000 -00000011 +00000011 # confirm read-only permissions of mvendorid 00000000 -00000002 +00000002 # write to read-only CSR failed with illegal instruction 00000000 -00000011 +00000011 # confirm read-only permissions of marchid 00000000 -00000002 +00000002 # write to read-only CSR failed with illegal instruction 00000000 -00000011 +00000011 # confirm read-only permissions of mimpid 00000000 -00000002 +00000002 # write to read-only CSR failed with illegal instruction 00000000 -00000011 +00000011 # confirm read-only permissions of mhartid 00000000 -0000000b +0000000b # ecall from terminating tests in M mode 00000000 deadbeef deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-s-01.S new file mode 100644 index 00000000..ce106983 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-s-01.S @@ -0,0 +1,153 @@ +/////////////////////////////////////////// +// +// WALLY-CSR-permissions +// +// Author: Kip Macsai-Goren +// +// Created 2022-02-05 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-MACROS-64.h" + +INIT_TESTS + +# Test 5.2.3.6: Test that all the machine mode CSR's are innaccessible for reads and writes in S mode. + +# *** several of these appear not to be implemented in the assembler? +# I get "assembler messages: error: unkown CSR" with many of them. + +goto_s_mode 0x0, 0x0 + +# Attempt to write 0xbad to each of these CSRs and read the value back +# should result in an illegal instruction for the write and read, respectively + +# Machine information Registers +write_read_csr mvendorid, 0xbad +write_read_csr marchid, 0xbad +write_read_csr mimpid, 0xbad +write_read_csr mhartid, 0xbad +# write_read_csr mconfigptr, 0xbad # mconfigptr unimplemented in spike as of 31 Jan 22 + +# Machine Trap Setup +write_read_csr mstatus, 0xbad +write_read_csr misa, 0xbad +write_read_csr medeleg, 0xbad +write_read_csr mideleg, 0xbad +write_read_csr mie, 0xbad +write_read_csr mtvec, 0xbad +write_read_csr mcounteren, 0xbad + +# Machine Trap Handling +write_read_csr mscratch, 0xbad +write_read_csr mepc, 0xbad +write_read_csr mcause, 0xbad +write_read_csr mtval, 0xbad +write_read_csr mip, 0xbad +# write_read_csr mtinst, 0xbad # *** these appear not to be implemented in the compile step of make??? +# write_read_csr mtval2, 0xbad + +# Machine Configuration +# write_read_csr menvcfg, 0xbad # *** these appear not to be implemented in the compile step of make??? +# write_read_csr mseccgf, 0xbad + +# Machine Memory Protection +write_read_csr pmpcfg0, 0xbad +write_read_csr pmpcfg2, 0xbad # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs + +write_read_csr pmpaddr0, 0xbad +write_read_csr pmpaddr1, 0xbad +write_read_csr pmpaddr2, 0xbad +write_read_csr pmpaddr3, 0xbad +write_read_csr pmpaddr4, 0xbad +write_read_csr pmpaddr5, 0xbad +write_read_csr pmpaddr6, 0xbad +write_read_csr pmpaddr7, 0xbad +write_read_csr pmpaddr8, 0xbad +write_read_csr pmpaddr9, 0xbad +write_read_csr pmpaddr10, 0xbad +write_read_csr pmpaddr11, 0xbad +write_read_csr pmpaddr12, 0xbad +write_read_csr pmpaddr13, 0xbad +write_read_csr pmpaddr14, 0xbad +write_read_csr pmpaddr15, 0xbad # only pmpcfg0...15 are enabled in our config + +# Machine Counter/Timers +write_read_csr mcycle, 0xbad +write_read_csr minstret, 0xbad +write_read_csr mhpmcounter3, 0xbad +write_read_csr mhpmcounter4, 0xbad +write_read_csr mhpmcounter5, 0xbad +write_read_csr mhpmcounter6, 0xbad +write_read_csr mhpmcounter7, 0xbad +write_read_csr mhpmcounter8, 0xbad +write_read_csr mhpmcounter9, 0xbad +write_read_csr mhpmcounter10, 0xbad +write_read_csr mhpmcounter11, 0xbad +write_read_csr mhpmcounter12, 0xbad +write_read_csr mhpmcounter13, 0xbad +write_read_csr mhpmcounter14, 0xbad +write_read_csr mhpmcounter15, 0xbad +write_read_csr mhpmcounter16, 0xbad +write_read_csr mhpmcounter17, 0xbad +write_read_csr mhpmcounter18, 0xbad +write_read_csr mhpmcounter19, 0xbad +write_read_csr mhpmcounter20, 0xbad +write_read_csr mhpmcounter21, 0xbad +write_read_csr mhpmcounter22, 0xbad +write_read_csr mhpmcounter23, 0xbad +write_read_csr mhpmcounter24, 0xbad +write_read_csr mhpmcounter25, 0xbad +write_read_csr mhpmcounter26, 0xbad +write_read_csr mhpmcounter27, 0xbad +write_read_csr mhpmcounter28, 0xbad +write_read_csr mhpmcounter29, 0xbad +write_read_csr mhpmcounter30, 0xbad +write_read_csr mhpmcounter31, 0xbad + +# Machine Counter Setup +write_read_csr mcountinhibit, 0xbad +write_read_csr mhpmevent3, 0xbad +write_read_csr mhpmevent4, 0xbad +write_read_csr mhpmevent5, 0xbad +write_read_csr mhpmevent6, 0xbad +write_read_csr mhpmevent7, 0xbad +write_read_csr mhpmevent8, 0xbad +write_read_csr mhpmevent9, 0xbad +write_read_csr mhpmevent10, 0xbad +write_read_csr mhpmevent11, 0xbad +write_read_csr mhpmevent12, 0xbad +write_read_csr mhpmevent13, 0xbad +write_read_csr mhpmevent14, 0xbad +write_read_csr mhpmevent15, 0xbad +write_read_csr mhpmevent16, 0xbad +write_read_csr mhpmevent17, 0xbad +write_read_csr mhpmevent18, 0xbad +write_read_csr mhpmevent19, 0xbad +write_read_csr mhpmevent20, 0xbad +write_read_csr mhpmevent21, 0xbad +write_read_csr mhpmevent22, 0xbad +write_read_csr mhpmevent23, 0xbad +write_read_csr mhpmevent24, 0xbad +write_read_csr mhpmevent25, 0xbad +write_read_csr mhpmevent26, 0xbad +write_read_csr mhpmevent27, 0xbad +write_read_csr mhpmevent28, 0xbad +write_read_csr mhpmevent29, 0xbad +write_read_csr mhpmevent30, 0xbad +write_read_csr mhpmevent31, 0xbad + +END_TESTS \ No newline at end of file diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-u-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-u-01.S new file mode 100644 index 00000000..d7984d7f --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-u-01.S @@ -0,0 +1,169 @@ +/////////////////////////////////////////// +// +// WALLY-CSR-permissions +// +// Author: Kip Macsai-Goren +// +// Created 2022-02-05 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-MACROS-64.h" + +INIT_TESTS + +# Test 5.2.3.6: Test that all the machine mode CSR's are innaccessible for reads and writes in R mode. + +goto_u_mode 0x0, 0x0 + +# Attempt to write 0xbad to each of these CSRs and read the value back +# should result in an illegal instruction for the write and read, respectively + +# Supervisor Trap Setup +write_read_csr sstatus, 0xbad +write_read_csr sie, 0xbad +write_read_csr stvec, 0xbad +write_read_csr scounteren, 0xbad + +# Supervisor Configuration +# write_read_csr senvcfg, 0xbad # *** these appear not to be implemented in the compile step of make??? + +# Supervisor Trap Handling +write_read_csr sscratch, 0xbad +write_read_csr sepc, 0xbad +write_read_csr scause, 0xbad +write_read_csr stval, 0xbad +write_read_csr sip, 0xbad + +# Supervisor Protection and Translation +write_read_csr satp, 0xbad + +# Machine information Registers +write_read_csr mvendorid, 0xbad +write_read_csr marchid, 0xbad +write_read_csr mimpid, 0xbad +write_read_csr mhartid, 0xbad +# write_read_csr mconfigptr, 0xbad # mconfigptr unimplemented in spike as of 31 Jan 22 + +# Machine Trap Setup +write_read_csr mstatus, 0xbad +write_read_csr misa, 0xbad +write_read_csr medeleg, 0xbad +write_read_csr mideleg, 0xbad +write_read_csr mie, 0xbad +write_read_csr mtvec, 0xbad +write_read_csr mcounteren, 0xbad + +# Machine Trap Handling +write_read_csr mscratch, 0xbad +write_read_csr mepc, 0xbad +write_read_csr mcause, 0xbad +write_read_csr mtval, 0xbad +write_read_csr mip, 0xbad +# write_read_csr mtinst, 0xbad # *** these appear not to be implemented in the compile step of make??? +# write_read_csr mtval2, 0xbad + +# Machine Configuration +# write_read_csr menvcfg, 0xbad # *** these appear not to be implemented in the compile step of make??? +# write_read_csr mseccgf, 0xbad + +# Machine Memory Protection +write_read_csr pmpcfg0, 0xbad +write_read_csr pmpcfg2, 0xbad # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs + +write_read_csr pmpaddr0, 0xbad +write_read_csr pmpaddr1, 0xbad +write_read_csr pmpaddr2, 0xbad +write_read_csr pmpaddr3, 0xbad +write_read_csr pmpaddr4, 0xbad +write_read_csr pmpaddr5, 0xbad +write_read_csr pmpaddr6, 0xbad +write_read_csr pmpaddr7, 0xbad +write_read_csr pmpaddr8, 0xbad +write_read_csr pmpaddr9, 0xbad +write_read_csr pmpaddr10, 0xbad +write_read_csr pmpaddr11, 0xbad +write_read_csr pmpaddr12, 0xbad +write_read_csr pmpaddr13, 0xbad +write_read_csr pmpaddr14, 0xbad +write_read_csr pmpaddr15, 0xbad # only pmpcfg0...15 are enabled in our config + +# Machine Counter/Timers +write_read_csr mcycle, 0xbad +write_read_csr minstret, 0xbad +write_read_csr mhpmcounter3, 0xbad +write_read_csr mhpmcounter4, 0xbad +write_read_csr mhpmcounter5, 0xbad +write_read_csr mhpmcounter6, 0xbad +write_read_csr mhpmcounter7, 0xbad +write_read_csr mhpmcounter8, 0xbad +write_read_csr mhpmcounter9, 0xbad +write_read_csr mhpmcounter10, 0xbad +write_read_csr mhpmcounter11, 0xbad +write_read_csr mhpmcounter12, 0xbad +write_read_csr mhpmcounter13, 0xbad +write_read_csr mhpmcounter14, 0xbad +write_read_csr mhpmcounter15, 0xbad +write_read_csr mhpmcounter16, 0xbad +write_read_csr mhpmcounter17, 0xbad +write_read_csr mhpmcounter18, 0xbad +write_read_csr mhpmcounter19, 0xbad +write_read_csr mhpmcounter20, 0xbad +write_read_csr mhpmcounter21, 0xbad +write_read_csr mhpmcounter22, 0xbad +write_read_csr mhpmcounter23, 0xbad +write_read_csr mhpmcounter24, 0xbad +write_read_csr mhpmcounter25, 0xbad +write_read_csr mhpmcounter26, 0xbad +write_read_csr mhpmcounter27, 0xbad +write_read_csr mhpmcounter28, 0xbad +write_read_csr mhpmcounter29, 0xbad +write_read_csr mhpmcounter30, 0xbad +write_read_csr mhpmcounter31, 0xbad + +# Machine Counter Setup +write_read_csr mcountinhibit, 0xbad +write_read_csr mhpmevent3, 0xbad +write_read_csr mhpmevent4, 0xbad +write_read_csr mhpmevent5, 0xbad +write_read_csr mhpmevent6, 0xbad +write_read_csr mhpmevent7, 0xbad +write_read_csr mhpmevent8, 0xbad +write_read_csr mhpmevent9, 0xbad +write_read_csr mhpmevent10, 0xbad +write_read_csr mhpmevent11, 0xbad +write_read_csr mhpmevent12, 0xbad +write_read_csr mhpmevent13, 0xbad +write_read_csr mhpmevent14, 0xbad +write_read_csr mhpmevent15, 0xbad +write_read_csr mhpmevent16, 0xbad +write_read_csr mhpmevent17, 0xbad +write_read_csr mhpmevent18, 0xbad +write_read_csr mhpmevent19, 0xbad +write_read_csr mhpmevent20, 0xbad +write_read_csr mhpmevent21, 0xbad +write_read_csr mhpmevent22, 0xbad +write_read_csr mhpmevent23, 0xbad +write_read_csr mhpmevent24, 0xbad +write_read_csr mhpmevent25, 0xbad +write_read_csr mhpmevent26, 0xbad +write_read_csr mhpmevent27, 0xbad +write_read_csr mhpmevent28, 0xbad +write_read_csr mhpmevent29, 0xbad +write_read_csr mhpmevent30, 0xbad +write_read_csr mhpmevent31, 0xbad + +END_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMP.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMP.S index 226c9398..5c894081 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMP.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMP.S @@ -72,7 +72,7 @@ .8byte 0x0, 0x0018FF0C0009001F, write_pmpcfg_0 # attempt to edit only pmp5cfg (pmpcfg0[47:40]) after lockout. # instruction ignored, output is 0x0018900C0009001F, NOT 0x0018FF0C0009001F .8byte 0x5, 0xFFFFFFFF, write_pmpaddr_5 # attempt to edit pmpaddr5 after lockout. -# instruction ignored, output is 0x80100300, NOT 0xFFFFFFFF +# instruction ignored, output is 0x200400c0, NOT 0xFFFFFFFF # Test 12.3.2.2.2 Machine mode access diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-MACROS-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-MACROS-64.h index a044f737..de54815e 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-MACROS-64.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-MACROS-64.h @@ -279,29 +279,28 @@ begin_test: // label here to jump to so we dont go through the trap handler befo // Test Summary table! -// Test Name : Description : Fault output value : Normal output values -// ---------------------:-------------------------------------------:-------------------------------:------------------------------------------------------ -// write64_test : Write 64 bits to address : 0x6, 0x7, or 0xf : None -// write32_test : Write 32 bits to address : 0x6, 0x7, or 0xf : None -// write16_test : Write 16 bits to address : 0x6, 0x7, or 0xf : None -// write08_test : Write 8 bits to address : 0x6, 0x7, or 0xf : None -// read64_test : Read 64 bits from address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex -// read32_test : Read 32 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex -// read16_test : Read 16 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex -// read08_test : Read 8 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex -// executable_test : test executable on virtual page : 0x0, 0x1, or 0xc, then 0xbad : value of x7 modified by exectuion code (usually 0x111) -// terminate_test : terminate tests : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 -// goto_baremetal : satp.MODE = bare metal : None : None -// goto_sv39 : satp.MODE = sv39 : None : None -// goto_sv48 : satp.MODE = sv48 : None : None -// goto_m_mode : go to mahcine mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 -// goto_s_mode : go to supervisor mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 -// goto_u_mode : go to user mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 -// write_csr : write to specified CSR : CSR value before test attempt : value written to CSR -// read_csr : read from specified CSR : *** None? Mcause or fault? : value read back from CSR +// Test Name : Description : Fault output value : Normal output values +// ---------------------:-------------------------------------------:-------------------------------------------:------------------------------------------------------ +// write64_test : Write 64 bits to address : 0x6, 0x7, or 0xf : None +// write32_test : Write 32 bits to address : 0x6, 0x7, or 0xf : None +// write16_test : Write 16 bits to address : 0x6, 0x7, or 0xf : None +// write08_test : Write 8 bits to address : 0x6, 0x7, or 0xf : None +// read64_test : Read 64 bits from address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex +// read32_test : Read 32 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex +// read16_test : Read 16 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex +// read08_test : Read 8 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex +// executable_test : test executable on virtual page : 0x0, 0x1, or 0xc, then 0xbad : value of x7 modified by exectuion code (usually 0x111) +// terminate_test : terminate tests : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 +// goto_baremetal : satp.MODE = bare metal : None : None +// goto_sv39 : satp.MODE = sv39 : None : None +// goto_sv48 : satp.MODE = sv48 : None : None +// goto_m_mode : go to mahcine mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 +// goto_s_mode : go to supervisor mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 +// goto_u_mode : go to user mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 +// write_read_csr : write to specified CSR : old CSR value, 0x2, depending on perms : value written to CSR +// csr_r_access : test read-only permissions on CSR : 0xbad : 0x2, then 0x11 - -// *** TESTS TO ADD: execute inline, read unknown value out, read CSR unknown value +// *** TESTS TO ADD: execute inline, read unknown value out, read CSR unknown value, just read CSR value .macro write64_test ADDR VAL // attempt to write VAL to ADDR @@ -452,13 +451,14 @@ begin_test: // label here to jump to so we dont go through the trap handler befo sfence.vma x0, x0 // *** flushes global pte's as well .endm -.macro write_csr CSR VAL - // attempt to write CSR with VAL *** ASSUMES RW access to CSR in whatever privilege mode is running +.macro write_read_csr CSR VAL + // attempt to write CSR with VAL. Note: this also tests read access to CSR // Success outputs: // value read back out from CSR after writing // Fault outputs: // The previous CSR value before write attempt - // *** Is there an associated mstatus? maybe 0x2??? + // *** Most likely 0x2, the mcause for illegal instruction if we don't have write or read access + li x30, 0xbad // load bad value to be overwritten by csrr li x29, \VAL csrw \CSR\(), x29 csrr x30, \CSR @@ -478,9 +478,9 @@ begin_test: // label here to jump to so we dont go through the trap handler befo csrwi \CSR\(), 0xA // Attempt to write a 'random' value to the CSR csrr x30, \CSR bne x30, x29, 1f // 1f represents write_access - li x30, 0x11 // Write succeeded, violating read only permissions. + li x30, 0x11 // Write failed, confirming read only permissions. j 2f // j r_access_end -1: // w_access (test failed) +1: // w_access (write succeeded, violating read-only) li x30, 0xBAD 2: // r_access end sd x30, 0(x6) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S index 2367a32b..695c7522 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S @@ -25,7 +25,7 @@ INIT_TESTS -// Test 5.2.3.1: tersting Read-only access to Machine info CSRs +// Test 5.2.3.1: testing Read-only access to Machine info CSRs csr_r_access mvendorid csr_r_access marchid