From 8a277f6b7503fef4b7b6834a3d930d6390d98122 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 28 Jan 2023 16:14:19 -0600 Subject: [PATCH] Possible fix for speculative gshare. --- pipelined/regression/wave.do | 78 ++++++++++--------- pipelined/src/ifu/brpred/bpred.sv | 2 +- pipelined/src/ifu/brpred/speculativegshare.sv | 43 +++++----- 3 files changed, 68 insertions(+), 55 deletions(-) diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index bfa161da..b2d2cfd2 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -61,10 +61,10 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/Inst add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName -add wave -noupdate -group {Memory Stage} /testbench/dut/core/PCM -add wave -noupdate -group {Memory Stage} /testbench/dut/core/InstrM -add wave -noupdate -group {Memory Stage} /testbench/InstrMName -add wave -noupdate -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM +add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM add wave -noupdate -group {WriteBack stage} /testbench/PCW add wave -noupdate -group {WriteBack stage} /testbench/InstrW add wave -noupdate -group {WriteBack stage} /testbench/InstrWName @@ -99,6 +99,7 @@ add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F +add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/PCNext0F add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNext1F add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/BPPredWrongE add wave -noupdate -group RegFile -expand /testbench/dut/core/ieu/dp/regf/rf @@ -573,12 +574,6 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/InstrClassE add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredInstrClassE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/DirectClassDecode/CompressedOpcF -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/DirectClassDecode/InstrClassF -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/DirectClassDecode/cjal -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/DirectClassDecode/cj -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/DirectClassDecode/cjr -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/DirectClassDecode/cjalr add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/rd add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PostSpillInstrRawF add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BTBPredPCWrongM @@ -588,34 +583,47 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredInstrClassD add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/InstrClassD add wave -noupdate -color Firebrick /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCSrcE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionE +add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF +add wave -noupdate -expand -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCSrcE +add wave -noupdate -expand -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionE +add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/TableDirPredictionF +add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchXF +add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionWrongE +add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE +add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM +add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushE +add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF +add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRD +add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRE +add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM +add wave -noupdate -expand -group {branch direction} -expand -group ghr -color Orange /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRW +add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE +add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRE +add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrF +add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD +add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextM +add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE +add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF +add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextD +add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextE +add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextM +add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextW +add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE +add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionE +add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexE +add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/StallM +add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/TableDirPredictionF -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchXF -add wave -noupdate -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF -add wave -noupdate -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRD -add wave -noupdate -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRE -add wave -noupdate -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM -add wave -noupdate -expand -group ghr -color Orange /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRW -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRD -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/PCNextF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/TableBTBPredictionF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BPPredPCF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/SelBPPredF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredValidF add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrF add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextM -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE -add wave -noupdate -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF -add wave -noupdate -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextD -add wave -noupdate -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextE -add wave -noupdate -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextM -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/StallM -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRF TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {5919 ns} 1} {{Cursor 5} {2337 ns} 0} +WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {5919 ns} 1} {{Cursor 5} {5845 ns} 0} quietly wave cursor active 5 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 @@ -631,4 +639,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {2195 ns} {2479 ns} +WaveRestoreZoom {5721 ns} {5893 ns} diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv index 3fd02157..6af31464 100644 --- a/pipelined/src/ifu/brpred/bpred.sv +++ b/pipelined/src/ifu/brpred/bpred.sv @@ -28,7 +28,7 @@ `include "wally-config.vh" -`define INSTR_CLASS_PRED 1 +`define INSTR_CLASS_PRED 0 module bpred ( input logic clk, reset, diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv index 85cb3654..64980097 100644 --- a/pipelined/src/ifu/brpred/speculativegshare.sv +++ b/pipelined/src/ifu/brpred/speculativegshare.sv @@ -53,10 +53,10 @@ module speculativegshare logic [k-1:0] GHRF, OldGHRF; logic OldGHRExtraF; - logic [k:0] GHRD, OldGHRE, GHRE, GHRM, GHRW; - logic [k-1:0] GHRNextF; - logic [k:0] GHRNextD; - logic [k:0] GHRNextE, GHRNextM, GHRNextW; + logic [k-1:0] GHRD, OldGHRE, GHRE, GHRM, GHRW; + logic [k-1:0] GHRNextF; + logic [k-1:0] GHRNextD; + logic [k-1:0] GHRNextE, GHRNextM, GHRNextW; logic [k-1:0] IndexNextF, IndexF; logic [k-1:0] IndexD, IndexE; @@ -113,31 +113,36 @@ module speculativegshare always_comb begin if(FlushD) begin - if(BranchInstrE) GHRNextF = GHRNextD[k:1]; - else GHRNextF = GHRNextD[k-1:0]; + //if(BranchInstrE) GHRNextF = {PCSrcE, GHRNextD[k-1:1]}; + //else GHRNextF = GHRNextD[k-1:0]; + GHRNextF = GHRNextD[k-1:0]; end else if(BranchInstrF) GHRNextF = {DirPredictionF[1], GHRF[k-1:1]}; else GHRNextF = GHRF; end - - flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, OldGHRF); - flopenr #(1) GHRFExtraReg(clk, reset, (~StallF) | FlushD, GHRNextF[0], OldGHRExtraF); - assign GHRF = WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], OldGHRF[k-1:1]} : // shift right - WrongPredInstrClassD[0] & ~BranchInstrD ? {OldGHRF[k-2:0], OldGHRExtraF}: // shift left - OldGHRF[k-1:0]; + + flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF); + //flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, OldGHRF); + //flopenr #(1) GHRFExtraReg(clk, reset, (~StallF) | FlushD, GHRNextF[0], OldGHRExtraF); +// assign GHRF = WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], OldGHRF[k-1:1]} : // shift right +// WrongPredInstrClassD[0] & ~BranchInstrD ? {OldGHRF[k-2:0], OldGHRExtraF}: // shift left +// OldGHRF[k-1:0]; - assign GHRNextD = FlushD ? {GHRNextE} : {DirPredictionF[1], GHRF}; + //assign GHRNextD = FlushD ? {GHRNextE} : {DirPredictionF[1], GHRF[k-1:1]}; + assign GHRNextD = FlushD ? GHRNextE[k-1:0] : GHRF[k-1:0]; - flopenr #(k+1) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD); + flopenr #(k) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD); - assign GHRNextE = FlushE ? GHRNextM : GHRD; - flopenr #(k+1) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, OldGHRE); - assign GHRE = BranchInstrE ? {PCSrcE, OldGHRE[k-1:0]} : OldGHRE; + assign GHRNextE = DirPredictionWrongE & BranchInstrE & ~FlushM ? {PCSrcE, GHRD[k-2:0]} : // if the branch is not flushed and was mispredicted + FlushE ? GHRNextM : // branch is flushed + GHRD; + flopenr #(k) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, GHRE); + //assign GHRE = BranchInstrE ? {PCSrcE, OldGHRE[k-1:0]} : OldGHRE; assign GHRNextM = FlushM ? GHRNextW : GHRE; - flopenr #(k+1) GHRMReg(clk, reset, (~StallM) | FlushM, GHRNextM, GHRM); + flopenr #(k) GHRMReg(clk, reset, (~StallM) | FlushM, GHRNextM, GHRM); assign GHRNextW = FlushW ? GHRW : GHRM; - flopenr #(k+1) GHRWReg(clk, reset, (BranchInstrM & ~StallW) | FlushW, GHRNextW, GHRW); + flopenr #(k) GHRWReg(clk, reset, (BranchInstrW & ~StallW) | FlushW, GHRNextW, GHRW); assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;