From 89e17b6f3c7c74abde6157f7cd0ca9a4547d4895 Mon Sep 17 00:00:00 2001
From: cturek <cturek@hmc.edu>
Date: Thu, 7 Jul 2022 21:23:30 +0000
Subject: [PATCH] Preprocessing for square root

---
 pipelined/srt/srt.sv       | 21 ++++++++++++---------
 pipelined/srt/testbench.sv | 18 ++++++++++++------
 2 files changed, 24 insertions(+), 15 deletions(-)

diff --git a/pipelined/srt/srt.sv b/pipelined/srt/srt.sv
index 583a0586..7dc8ba8b 100644
--- a/pipelined/srt/srt.sv
+++ b/pipelined/srt/srt.sv
@@ -57,22 +57,22 @@ module srt (
   logic           qp, qz, qm; // quotient is +1, 0, or -1
   logic [`NE-1:0] calcExp;
   logic           calcSign;
-  logic [`DIVLEN-1:0]  X, Dpreproc;
+  logic [`DIVLEN+3:0]  X, Dpreproc;
   logic [`DIVLEN+3:0]  WS, WSA, WSN, WC, WCA, WCN, D, Db, Dsel;
   logic [$clog2(`XLEN+1)-1:0] intExp, dur, calcDur;
   logic           intSign;
  
-  srtpreproc preproc(SrcA, SrcB, SrcXFrac, SrcYFrac, Fmt, W64, Signed, Int, Sqrt, X, Dpreproc, intExp, calcDur, intSign);
+  srtpreproc preproc(SrcA, SrcB, SrcXFrac, SrcYFrac, XExp, Fmt, W64, Signed, Int, Sqrt, X, Dpreproc, intExp, calcDur, intSign);
 
   // Top Muxes and Registers
   // When start is asserted, the inputs are loaded into the divider.
   // Otherwise, the divisor is retained and the partial remainder
   // is fed back for the next iteration.
-  mux2   #(`DIVLEN+4) wsmux({WSA[`DIVLEN+2:0], 1'b0}, {4'b0001, X}, Start, WSN);
+  mux2   #(`DIVLEN+4) wsmux({WSA[`DIVLEN+2:0], 1'b0}, X, Start, WSN);
   flop   #(`DIVLEN+4) wsflop(clk, WSN, WS);
   mux2   #(`DIVLEN+4) wcmux({WCA[`DIVLEN+2:0], 1'b0}, {(`DIVLEN+4){1'b0}}, Start, WCN);
   flop   #(`DIVLEN+4) wcflop(clk, WCN, WC);
-  flopen #(`DIVLEN+4) dflop(clk, Start, {4'b0001, Dpreproc}, D);
+  flopen #(`DIVLEN+4) dflop(clk, Start, Dpreproc, D);
 
   // Quotient Selection logic
   // Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm)
@@ -108,19 +108,20 @@ endmodule
 module srtpreproc (
   input  logic [`XLEN-1:0] SrcA, SrcB,
   input  logic [`NF-1:0] SrcXFrac, SrcYFrac,
+  input  logic [`NE-1:0] XExp,
   input  logic [1:0] Fmt, // Floats: 00 = 16 bit, 01 = 32 bit, 10 = 64 bit, 11 = 128 bit
   input  logic       W64, // 32-bit ints on XLEN=64
   input  logic       Signed, // Interpret integers as signed 2's complement
   input  logic       Int, // Choose integer inputs
   input  logic       Sqrt, // perform square root, not divide
-  output logic [`DIVLEN-1:0] X, D,
+  output logic [`DIVLEN+3:0] X, D,
   output logic [$clog2(`XLEN+1)-1:0] intExp, dur, // Quotient integer exponent
   output logic       intSign // Quotient integer sign
 );
 
   logic  [$clog2(`XLEN+1)-1:0] zeroCntA, zeroCntB;
   logic  [`XLEN-1:0] PosA, PosB;
-  logic  [`DIVLEN-1:0] ExtraA, ExtraB, PreprocA, PreprocB, PreprocX, PreprocY;
+  logic  [`DIVLEN-1:0] ExtraA, ExtraB, PreprocA, PreprocB, PreprocX, PreprocY, DivX, SqrtX;
 
   assign PosA = (Signed & SrcA[`XLEN - 1]) ? -SrcA : SrcA;
   assign PosB = (Signed & SrcB[`XLEN - 1]) ? -SrcB : SrcB;
@@ -136,9 +137,11 @@ module srtpreproc (
   assign PreprocX = {SrcXFrac, {`EXTRAFRACBITS{1'b0}}};
   assign PreprocY = {SrcYFrac, {`EXTRAFRACBITS{1'b0}}};
 
-  
-  assign X = Int ? PreprocA : PreprocX;
-  assign D = Int ? PreprocB : PreprocY;
+  assign DivX = Int ? PreprocA : PreprocX;
+  assign SqrtX = {XExp[0] ? 4'b0000 : 4'b1111, SrcXFrac};
+
+  assign X = Sqrt ? SqrtX : {4'b0001, DivX};
+  assign D = {4'b0001, Int ? PreprocB : PreprocY};
   assign intExp = zeroCntB - zeroCntA + 1;
   assign intSign = Signed & (SrcA[`XLEN - 1] ^ SrcB[`XLEN - 1]);
 
diff --git a/pipelined/srt/testbench.sv b/pipelined/srt/testbench.sv
index b2de913c..6af2174b 100644
--- a/pipelined/srt/testbench.sv
+++ b/pipelined/srt/testbench.sv
@@ -55,10 +55,16 @@ module testbench;
   parameter MEM_SIZE = 40000;
   parameter MEM_WIDTH = 64+64+64+64;
  
-  `define memrem  63:0
-  `define memr  127:64
-  `define memb  191:128
-  `define mema  255:192
+  // INT TEST SIZES
+  // `define memrem  63:0 
+  // `define memr  127:64
+  // `define memb  191:128
+  // `define mema  255:192
+
+  // FLOAT TEST SIZES
+  `define memr  63:0 
+  `define memb  127:64
+  `define mema  191:128
 
   // Test logicisters
   logic [MEM_WIDTH-1:0] Tests [0:MEM_SIZE];  // Space for input file
@@ -69,7 +75,7 @@ module testbench;
   logic        rsign;
   integer testnum, errors;
 
-  assign Int = 1'b1;
+  assign Int = 1'b0;
 
   // Divider
   srt srt(.clk, .Start(req), 
@@ -98,7 +104,7 @@ module testbench;
     begin
       testnum = 0; 
       errors = 0;
-      $readmemh ("inttestvectors", Tests);
+      $readmemh ("testvectors", Tests);
       Vec = Tests[testnum];
       a = Vec[`mema];
       {asign, aExp, afrac} = a;