diff --git a/pipelined/src/ebu/ahblite.sv b/pipelined/src/ebu/ahblite.sv index 0bf81f62..6c3d0c33 100644 --- a/pipelined/src/ebu/ahblite.sv +++ b/pipelined/src/ebu/ahblite.sv @@ -51,14 +51,14 @@ module ahblite ( input logic IFUTransComplete, // Signals from Data Cache - input logic [`PA_BITS-1:0] LSUBusAdr, + input logic [`PA_BITS-1:0] LSUHADDR, input logic LSUBusRead, input logic LSUBusWrite, input logic [`XLEN-1:0] LSUBusHWDATA, - output logic [`XLEN-1:0] LSUBusHRDATA, - input logic [2:0] LSUBusSize, - input logic [2:0] LSUBurstType, - input logic [1:0] LSUTransType, + output logic [`XLEN-1:0] LSUHRDATA, + input logic [2:0] LSUHSIZE, + input logic [2:0] LSUHBURST, + input logic [1:0] LSUHTRANS, input logic LSUTransComplete, output logic LSUBusAck, output logic LSUBusInit, @@ -133,11 +133,11 @@ module ahblite ( // bus outputs assign #1 LSUGrant = (NextBusState == MEMREAD) | (NextBusState == MEMWRITE); - assign AccessAddress = (LSUGrant) ? LSUBusAdr[31:0] : IFUBusAdr[31:0]; + assign AccessAddress = (LSUGrant) ? LSUHADDR[31:0] : IFUBusAdr[31:0]; assign HADDR = AccessAddress; assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway - assign HSIZE = (LSUGrant) ? {1'b0, LSUBusSize[1:0]} : ISize; - assign HBURST = (LSUGrant) ? LSUBurstType : IFUBurstType; // If doing memory accesses, use LSUburst, else use Instruction burst. + assign HSIZE = (LSUGrant) ? {1'b0, LSUHSIZE[1:0]} : ISize; + assign HBURST = (LSUGrant) ? LSUHBURST : IFUBurstType; // If doing memory accesses, use LSUburst, else use Instruction burst. /* Cache burst read/writes case statement (hopefully) WRAPS only have access to 4 wraps. X changes position based on HSIZE. 000: Single (SINGLE) @@ -153,7 +153,7 @@ module ahblite ( assign HPROT = 4'b0011; // not used; see Section 3.7 - assign HTRANS = (LSUGrant) ? LSUTransType : IFUTransType; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise + assign HTRANS = (LSUGrant) ? LSUHTRANS : IFUTransType; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise assign HMASTLOCK = 0; // no locking supported assign HWRITE = (NextBusState == MEMWRITE); // Byte mask for HWSTRB @@ -169,7 +169,7 @@ module ahblite ( // Route signals to Instruction and Data Caches // *** assumes AHBW = XLEN assign IFUBusHRDATA = HRDATA; - assign LSUBusHRDATA = HRDATA; + assign LSUHRDATA = HRDATA; assign IFUBusInit = (BusState != INSTRREAD) & (NextBusState == INSTRREAD); assign LSUBusInit = (((BusState != MEMREAD) & (NextBusState == MEMREAD)) | (BusState != MEMWRITE) & (NextBusState == MEMWRITE)); assign IFUBusAck = HREADY & (BusState == INSTRREAD); diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index c0bce157..1f3bda8c 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -203,9 +203,9 @@ module ifu ( busdp #(WORDSPERLINE, LINELEN, LOGBWPL, `ICACHE) busdp(.clk, .reset, - .LSUBusHRDATA(IFUBusHRDATA), .LSUBusAck(IFUBusAck), .LSUBusInit(IFUBusInit), .LSUBusWrite(), .SelLSUBusWord(), - .LSUBusRead(IFUBusRead), .LSUBusSize(), .LSUBurstType(IFUBurstType), .LSUTransType(IFUTransType), .LSUTransComplete(IFUTransComplete), - .LSUFunct3M(3'b010), .LSUBusAdr(IFUBusAdr), .CacheBusAdr(ICacheBusAdr), + .HRDATA(IFUBusHRDATA), .BusAck(IFUBusAck), .BusInit(IFUBusInit), .BusWrite(), .SelLSUBusWord(), + .BusRead(IFUBusRead), .HSIZE(), .HBURST(IFUBurstType), .HTRANS(IFUTransType), .BusTransComplete(IFUTransComplete), + .LSUFunct3M(3'b010), .HADDR(IFUBusAdr), .CacheBusAdr(ICacheBusAdr), .WordCount(), .CacheFetchLine(ICacheFetchLine), .CacheWriteLine(1'b0), .CacheBusAck(ICacheBusAck), @@ -214,6 +214,7 @@ module ifu ( .IgnoreRequest(ITLBMissF), .LSURWM(2'b10), .CPUBusy, .CacheableM(CacheableF), .BusStall, .BusCommittedM()); + mux2 #(32) UnCachedDataMux(.d0(FinalInstrRawF), .d1(ILSUBusBuffer[32-1:0]), .s(SelUncachedAdr), .y(AllInstrRawF[31:0])); diff --git a/pipelined/src/lsu/busdp.sv b/pipelined/src/lsu/busdp.sv index 3889b070..0f0e2b47 100644 --- a/pipelined/src/lsu/busdp.sv +++ b/pipelined/src/lsu/busdp.sv @@ -39,20 +39,19 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) input logic clk, reset, // bus interface - input logic [`XLEN-1:0] LSUBusHRDATA, - input logic LSUBusAck, - input logic LSUBusInit, - output logic LSUBusWrite, - output logic LSUBusRead, - output logic [2:0] LSUBusSize, - output logic [2:0] LSUBurstType, - output logic [1:0] LSUTransType, // For AHBLite - output logic LSUTransComplete, - input logic [2:0] LSUFunct3M, - output logic [`PA_BITS-1:0] LSUBusAdr, // ** change name to HADDR to make ahb lite. + input logic [`XLEN-1:0] HRDATA, + input logic BusAck, + input logic BusInit, + output logic BusWrite, + output logic BusRead, + output logic [2:0] HSIZE, + output logic [2:0] HBURST, + output logic [1:0] HTRANS, // For AHBLite + output logic BusTransComplete, + output logic [`PA_BITS-1:0] HADDR, output logic [LOGWPL-1:0] WordCount, - // cache interface. + // cache interface input logic [`PA_BITS-1:0] CacheBusAdr, input logic CacheFetchLine, input logic CacheWriteLine, @@ -66,12 +65,13 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) input logic [1:0] LSURWM, input logic CPUBusy, input logic CacheableM, + input logic [2:0] LSUFunct3M, output logic SelLSUBusWord, output logic BusStall, output logic BusCommittedM); localparam integer WordCountThreshold = CACHE_ENABLED ? WORDSPERLINE - 1 : 0; - logic [`PA_BITS-1:0] LocalLSUBusAdr; + logic [`PA_BITS-1:0] LocalHADDR; logic [LOGWPL-1:0] WordCountDelayed; logic BufferCaptureEn; @@ -79,17 +79,17 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer logic [WORDSPERLINE-1:0] CaptureWord; assign CaptureWord[index] = BufferCaptureEn & (index == WordCountDelayed); - flopen #(`XLEN) fb(.clk, .en(CaptureWord[index]), .d(LSUBusHRDATA), + flopen #(`XLEN) fb(.clk, .en(CaptureWord[index]), .d(HRDATA), .q(DLSUBusBuffer[(index+1)*`XLEN-1:index*`XLEN])); end - mux2 #(`PA_BITS) localadrmux(CacheBusAdr, LSUPAdrM, SelUncachedAdr, LocalLSUBusAdr); - assign LSUBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalLSUBusAdr; - mux2 #(3) lsubussizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(LSUFunct3M), - .s(SelUncachedAdr), .y(LSUBusSize)); + mux2 #(`PA_BITS) localadrmux(CacheBusAdr, LSUPAdrM, SelUncachedAdr, LocalHADDR); + assign HADDR = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalHADDR; + mux2 #(3) sizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(LSUFunct3M), + .s(SelUncachedAdr), .y(HSIZE)); busfsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) busfsm( .clk, .reset, .IgnoreRequest, .LSURWM, .CacheFetchLine, .CacheWriteLine, - .LSUBusAck, .LSUBusInit, .CPUBusy, .CacheableM, .BusStall, .LSUBusWrite, .SelLSUBusWord, .LSUBusRead, + .BusAck, .BusInit, .CPUBusy, .CacheableM, .BusStall, .BusWrite, .SelLSUBusWord, .BusRead, .BufferCaptureEn, - .LSUBurstType, .LSUTransType, .LSUTransComplete, .CacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount, .WordCountDelayed); + .HBURST, .HTRANS, .BusTransComplete, .CacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount, .WordCountDelayed); endmodule diff --git a/pipelined/src/lsu/busfsm.sv b/pipelined/src/lsu/busfsm.sv index f0204f3e..e86f7678 100644 --- a/pipelined/src/lsu/busfsm.sv +++ b/pipelined/src/lsu/busfsm.sv @@ -40,18 +40,18 @@ module busfsm #(parameter integer WordCountThreshold, input logic [1:0] LSURWM, input logic CacheFetchLine, input logic CacheWriteLine, - input logic LSUBusAck, - input logic LSUBusInit, // This might be better as LSUBusLock, or to send this using LSUBusAck. + input logic BusAck, + input logic BusInit, // This might be better as LSUBusLock, or to send this using BusAck. input logic CPUBusy, input logic CacheableM, output logic BusStall, - output logic LSUBusWrite, + output logic BusWrite, output logic SelLSUBusWord, - output logic LSUBusRead, - output logic [2:0] LSUBurstType, - output logic LSUTransComplete, - output logic [1:0] LSUTransType, + output logic BusRead, + output logic [2:0] HBURST, + output logic BusTransComplete, + output logic [1:0] HTRANS, output logic CacheBusAck, output logic BusCommittedM, output logic SelUncachedAdr, @@ -60,8 +60,8 @@ module busfsm #(parameter integer WordCountThreshold, - logic UnCachedLSUBusRead; - logic UnCachedLSUBusWrite; + logic UnCachedBusRead; + logic UnCachedBusWrite; logic CntEn, PreCntEn; logic CntReset; logic WordCountFlag; @@ -103,7 +103,7 @@ module busfsm #(parameter integer WordCountThreshold, assign PreCntEn = (BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_WRITE); assign WordCountFlag = (WordCountDelayed == WordCountThreshold[LOGWPL-1:0]); // Detect when we are waiting on the final access. - assign CntEn = (PreCntEn & LSUBusAck | (LSUBusInit)) & ~WordCountFlag & ~UnCachedRW; // Want to count when doing cache accesses and we aren't wrapping up. + assign CntEn = (PreCntEn & BusAck | (BusInit)) & ~WordCountFlag & ~UnCachedRW; // Want to count when doing cache accesses and we aren't wrapping up. assign UnCachedAccess = ~CACHE_ENABLED | ~CacheableM; @@ -119,9 +119,9 @@ module busfsm #(parameter integer WordCountThreshold, else if(CacheFetchLine) BusNextState = STATE_BUS_FETCH; else if(CacheWriteLine) BusNextState = STATE_BUS_WRITE; else BusNextState = STATE_BUS_READY; - STATE_BUS_UNCACHED_WRITE: if(LSUBusAck) BusNextState = STATE_BUS_UNCACHED_WRITE_DONE; + STATE_BUS_UNCACHED_WRITE: if(BusAck) BusNextState = STATE_BUS_UNCACHED_WRITE_DONE; else BusNextState = STATE_BUS_UNCACHED_WRITE; - STATE_BUS_UNCACHED_READ: if(LSUBusAck) BusNextState = STATE_BUS_UNCACHED_READ_DONE; + STATE_BUS_UNCACHED_READ: if(BusAck) BusNextState = STATE_BUS_UNCACHED_READ_DONE; else BusNextState = STATE_BUS_UNCACHED_READ; STATE_BUS_UNCACHED_WRITE_DONE: if(CPUBusy) BusNextState = STATE_BUS_CPU_BUSY; else BusNextState = STATE_BUS_READY; @@ -129,12 +129,12 @@ module busfsm #(parameter integer WordCountThreshold, else BusNextState = STATE_BUS_READY; STATE_BUS_CPU_BUSY: if(CPUBusy) BusNextState = STATE_BUS_CPU_BUSY; else BusNextState = STATE_BUS_READY; - STATE_BUS_FETCH: if (WordCountFlag & LSUBusAck) begin + STATE_BUS_FETCH: if (WordCountFlag & BusAck) begin if (CacheFetchLine) BusNextState = STATE_BUS_FETCH; else if (CacheWriteLine) BusNextState = STATE_BUS_WRITE; else BusNextState = STATE_BUS_READY; end else BusNextState = STATE_BUS_FETCH; - STATE_BUS_WRITE: if(WordCountFlag & LSUBusAck) begin + STATE_BUS_WRITE: if(WordCountFlag & BusAck) begin if (CacheFetchLine) BusNextState = STATE_BUS_FETCH; else if (CacheWriteLine) BusNextState = STATE_BUS_WRITE; else BusNextState = STATE_BUS_READY; @@ -153,35 +153,35 @@ module busfsm #(parameter integer WordCountThreshold, endcase end - assign LSUBurstType = (UnCachedRW) ? 3'b0 : LocalBurstType; // Don't want to use burst when doing an Uncached Access. - assign LSUTransComplete = (UnCachedRW) ? LSUBusAck : WordCountFlag & LSUBusAck; + assign HBURST = (UnCachedRW) ? 3'b0 : LocalBurstType; // Don't want to use burst when doing an Uncached Access. + assign BusTransComplete = (UnCachedRW) ? BusAck : WordCountFlag & BusAck; // Use SEQ if not doing first word, NONSEQ if doing the first read/write, and IDLE if finishing up. - assign LSUTransType = (|WordCount) & ~UnCachedRW ? AHB_SEQ : (LSUBusRead | LSUBusWrite) & (~LSUTransComplete) ? AHB_NONSEQ : AHB_IDLE; + assign HTRANS = (|WordCount) & ~UnCachedRW ? AHB_SEQ : (BusRead | BusWrite) & (~BusTransComplete) ? AHB_NONSEQ : AHB_IDLE; // Reset if we aren't initiating a transaction or if we are finishing a transaction. - assign CntReset = BusCurrState == STATE_BUS_READY & ~(CacheFetchLine | CacheWriteLine) | LSUTransComplete; + assign CntReset = BusCurrState == STATE_BUS_READY & ~(CacheFetchLine | CacheWriteLine) | BusTransComplete; assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|LSURWM)) | CacheFetchLine | CacheWriteLine)) | (BusCurrState == STATE_BUS_UNCACHED_WRITE) | (BusCurrState == STATE_BUS_UNCACHED_READ) | (BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_WRITE); - assign UnCachedLSUBusWrite = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[0] & ~IgnoreRequest) | + assign UnCachedBusWrite = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[0] & ~IgnoreRequest) | (BusCurrState == STATE_BUS_UNCACHED_WRITE); - assign LSUBusWrite = UnCachedLSUBusWrite | (BusCurrState == STATE_BUS_WRITE & ~WordCountFlag); + assign BusWrite = UnCachedBusWrite | (BusCurrState == STATE_BUS_WRITE & ~WordCountFlag); assign SelLSUBusWord = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[0]) | (BusCurrState == STATE_BUS_UNCACHED_WRITE) | (BusCurrState == STATE_BUS_WRITE); - assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & ~IgnoreRequest) | + assign UnCachedBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & ~IgnoreRequest) | (BusCurrState == STATE_BUS_UNCACHED_READ); - assign LSUBusRead = UnCachedLSUBusRead | (BusCurrState == STATE_BUS_FETCH & ~(WordCountFlag)) | (BusCurrState == STATE_BUS_READY & CacheFetchLine); - assign BufferCaptureEn = UnCachedLSUBusRead | BusCurrState == STATE_BUS_FETCH; + assign BusRead = UnCachedBusRead | (BusCurrState == STATE_BUS_FETCH & ~(WordCountFlag)) | (BusCurrState == STATE_BUS_READY & CacheFetchLine); + assign BufferCaptureEn = UnCachedBusRead | BusCurrState == STATE_BUS_FETCH; // Makes bus only do uncached reads/writes when we actually do uncached reads/writes. Needed because CacheableM is 0 when flushing cache. - assign UnCachedRW = UnCachedLSUBusWrite | UnCachedLSUBusRead; + assign UnCachedRW = UnCachedBusWrite | UnCachedBusRead; - assign CacheBusAck = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & LSUBusAck) | - (BusCurrState == STATE_BUS_WRITE & WordCountFlag & LSUBusAck); + assign CacheBusAck = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & BusAck) | + (BusCurrState == STATE_BUS_WRITE & WordCountFlag & BusAck); assign BusCommittedM = BusCurrState != STATE_BUS_READY; assign SelUncachedAdr = (BusCurrState == STATE_BUS_READY & (|LSURWM & UnCachedAccess)) | (BusCurrState == STATE_BUS_UNCACHED_READ | diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 10f8060b..514b165e 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -65,16 +65,16 @@ module lsu ( // cpu hazard unit (trap) output logic StoreAmoMisalignedFaultM, StoreAmoAccessFaultM, // connect to ahb - (* mark_debug = "true" *) output logic [`PA_BITS-1:0] LSUBusAdr, + (* mark_debug = "true" *) output logic [`PA_BITS-1:0] LSUHADDR, (* mark_debug = "true" *) output logic LSUBusRead, (* mark_debug = "true" *) output logic LSUBusWrite, (* mark_debug = "true" *) input logic LSUBusAck, (* mark_debug = "true" *) input logic LSUBusInit, - (* mark_debug = "true" *) input logic [`XLEN-1:0] LSUBusHRDATA, + (* mark_debug = "true" *) input logic [`XLEN-1:0] LSUHRDATA, (* mark_debug = "true" *) output logic [`XLEN-1:0] LSUBusHWDATA, - (* mark_debug = "true" *) output logic [2:0] LSUBusSize, - (* mark_debug = "true" *) output logic [2:0] LSUBurstType, - (* mark_debug = "true" *) output logic [1:0] LSUTransType, + (* mark_debug = "true" *) output logic [2:0] LSUHSIZE, + (* mark_debug = "true" *) output logic [2:0] LSUHBURST, + (* mark_debug = "true" *) output logic [1:0] LSUHTRANS, (* mark_debug = "true" *) output logic LSUTransComplete, // page table walker input logic [`XLEN-1:0] SATP_REGW, // from csr @@ -198,9 +198,10 @@ module lsu ( // The LSU allows both a DTIM and bus with cache. However, the PMA decoding presently // use the same UNCORE_RAM_BASE addresss for both the DTIM and any RAM in the Uncore. + // *** becomes DTIM_RAM_BASE if (`DMEM) begin : dtim - dtim dtim(.clk, .reset, .LSURWM, .IEUAdrE, .TrapM, .WriteDataM(LSUWriteDataM), //*** fix the dtim FinalWriteData - is this done already? + dtim dtim(.clk, .reset, .LSURWM, .IEUAdrE, .TrapM, .WriteDataM(LSUWriteDataM), .ReadDataWordM(ReadDataWordM[`XLEN-1:0]), .ByteMaskM(ByteMaskM[`XLEN/8-1:0]), .Cacheable(CacheableM)); // since we have a local memory the bus connections are all disabled. @@ -223,9 +224,10 @@ module lsu ( busdp #(WORDSPERLINE, LINELEN, LOGBWPL, `DCACHE) busdp( .clk, .reset, - .LSUBusHRDATA, .LSUBusAck, .LSUBusInit, .LSUBusWrite, .LSUBusRead, .LSUBusSize, .LSUBurstType, .LSUTransType, .LSUTransComplete, + .HRDATA(LSUHRDATA), .BusAck(LSUBusAck), .BusInit(LSUBusInit), .BusWrite(LSUBusWrite), + .BusRead(LSUBusRead), .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .BusTransComplete(LSUTransComplete), .WordCount, .SelLSUBusWord, - .LSUFunct3M, .LSUBusAdr, .CacheBusAdr(DCacheBusAdr), .CacheFetchLine(DCacheFetchLine), + .LSUFunct3M, .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheFetchLine(DCacheFetchLine), .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .DLSUBusBuffer, .LSUPAdrM, .SelUncachedAdr, .IgnoreRequest, .LSURWM, .CPUBusy, .CacheableM, .BusStall, .BusCommittedM); diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index db6da30b..affcd5af 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -145,11 +145,11 @@ module wallypipelinedcore ( logic IFUTransComplete; // AHB LSU interface - logic [`PA_BITS-1:0] LSUBusAdr; + logic [`PA_BITS-1:0] LSUHADDR; logic LSUBusRead; logic LSUBusWrite; logic LSUBusAck, LSUBusInit; - logic [`XLEN-1:0] LSUBusHRDATA; + logic [`XLEN-1:0] LSUHRDATA; logic [`XLEN-1:0] LSUBusHWDATA; logic BPPredWrongE; @@ -159,9 +159,9 @@ module wallypipelinedcore ( logic BPPredClassNonCFIWrongM; logic [4:0] InstrClassM; logic InstrAccessFaultF; - logic [2:0] LSUBusSize; - logic [2:0] LSUBurstType; - logic [1:0] LSUTransType; + logic [2:0] LSUHSIZE; + logic [2:0] LSUHBURST; + logic [1:0] LSUHTRANS; logic LSUTransComplete; logic DCacheMiss; @@ -263,8 +263,8 @@ module wallypipelinedcore ( .IEUAdrE, .IEUAdrM, .WriteDataM, .ReadDataW, .FlushDCacheM, // connected to ahb (all stay the same) - .LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusAck, .LSUBusInit, - .LSUBusHRDATA, .LSUBusHWDATA, .LSUBusSize, .LSUBurstType, .LSUTransType, .LSUTransComplete, + .LSUHADDR, .LSUBusRead, .LSUBusWrite, .LSUBusAck, .LSUBusInit, + .LSUHRDATA, .LSUBusHWDATA, .LSUHSIZE, .LSUHBURST, .LSUHTRANS, .LSUTransComplete, // connect to csr or privilege and stay the same. .PrivilegeModeW, .BigEndianM, // connects to csr @@ -303,11 +303,11 @@ module wallypipelinedcore ( .IFUBusAck, .IFUBusInit, // Signals from Data Cache - .LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusHWDATA, - .LSUBusHRDATA, - .LSUBusSize, - .LSUBurstType, - .LSUTransType, + .LSUHADDR, .LSUBusRead, .LSUBusWrite, .LSUBusHWDATA, + .LSUHRDATA, + .LSUHSIZE, + .LSUHBURST, + .LSUHTRANS, .LSUTransComplete, .LSUBusAck, .LSUBusInit,