From 891ec82d815eafaaa9bf2ae465182ed44e95b589 Mon Sep 17 00:00:00 2001 From: bbracker Date: Sat, 5 Mar 2022 17:26:30 -0800 Subject: [PATCH] remove linux-testgen dir because it is now completely obsolete --- .../linux-testvectors/convert2bin.py | 13 - .../linux-testvectors/tvCopier.py | 62 -- .../linux-testvectors/tvLinker.sh | 3 - .../linux-testvectors/tvUnlinker.sh | 9 - .../linux-testgen/qemu-build-instructions.md | 10 - tests/linux-testgen/qemu-patches/README | 2 - tests/linux-testgen/qemu-patches/cpu.c | 722 ------------------ tests/linux-testgen/qemu-patches/virt.c | 451 ----------- tests/linux-testgen/wallyVirtIO.patch | 542 ------------- 9 files changed, 1814 deletions(-) delete mode 100755 tests/linux-testgen/linux-testvectors/convert2bin.py delete mode 100755 tests/linux-testgen/linux-testvectors/tvCopier.py delete mode 100755 tests/linux-testgen/linux-testvectors/tvLinker.sh delete mode 100755 tests/linux-testgen/linux-testvectors/tvUnlinker.sh delete mode 100644 tests/linux-testgen/qemu-build-instructions.md delete mode 100644 tests/linux-testgen/qemu-patches/README delete mode 100644 tests/linux-testgen/qemu-patches/cpu.c delete mode 100644 tests/linux-testgen/qemu-patches/virt.c delete mode 100644 tests/linux-testgen/wallyVirtIO.patch diff --git a/tests/linux-testgen/linux-testvectors/convert2bin.py b/tests/linux-testgen/linux-testvectors/convert2bin.py deleted file mode 100755 index 78349a5d..00000000 --- a/tests/linux-testgen/linux-testvectors/convert2bin.py +++ /dev/null @@ -1,13 +0,0 @@ -#!/usr/bin/python3 - -asciiBinFile = 'ram.txt' -binFile = 'ram.bin' - -asciiBinFP = open(asciiBinFile, 'r') -binFP = open (binFile, 'wb') - -for line in asciiBinFP.readlines(): - binFP.write(int(line, 16).to_bytes(8, byteorder='little', signed=False)) - -asciiBinFP.close() -binFP.close() diff --git a/tests/linux-testgen/linux-testvectors/tvCopier.py b/tests/linux-testgen/linux-testvectors/tvCopier.py deleted file mode 100755 index d272e98c..00000000 --- a/tests/linux-testgen/linux-testvectors/tvCopier.py +++ /dev/null @@ -1,62 +0,0 @@ -#!/usr/bin/python3 -# Copies Linux testvector files from Tera to ./ (which ought to be /riscv-wally/pipelined/linux-testgen/linux-testvectors/) -import os -from datetime import datetime - - -if not os.path.isfile('sshUname.txt'): - print("GREETINGS FRIEND") - print("Please supply your tera username in ./sshUname.txt") - exit(1) -sshUnameFile = open('sshUname.txt','r') -uname = sshUnameFile.readline().strip('\n') -tera = uname+'@tera.eng.hmc.edu' - -logFile = open('tvCopier.log', 'w') -def pyTee(line): - global logFile - print(line) - logFile.write(line+"\n") - -pyTee('Copying tvDateReporter.py from Tera') -os.system('scp '+tera+':/courses/e190ax/buildroot_boot/tvDateReporter.py ./') -pyTee('Running tvDateReporter.py Locally') -os.system('./tvDateReporter.py && mv tvDates.txt tvDatesLocal.txt') -pyTee('Running tvDateReporter.py on Tera') -os.system('ssh '+tera+' \"cd /courses/e190ax/buildroot_boot && ./tvDateReporter.py\"') -pyTee('Copying tvDates.txt from Tera') -os.system('scp '+tera+':/courses/e190ax/buildroot_boot/tvDates.txt ./') - -copyList = [] - -pyTee('_____________________________________________________________________') -pyTee('| File Name | Local_Date | Tera_Date | Update? |') -with open('tvDatesLocal.txt') as tvDatesLocal, open('tvDates.txt') as tvDatesTera_: - for tvDateLocal, tvDateTera_ in zip(tvDatesLocal,tvDatesTera_): - outString = '| ' - - tvDateLocal = tvDateLocal.strip('\n').split(' ') - tvDateTera_ = tvDateTera_.strip('\n').split(' ') - - tvFile = tvDateLocal[0] - outString += '{:<24}'.format(tvFile) - outString += '| '+tvDateLocal[1]+' | '+tvDateTera_[1] - - tvDateLocal = tvDateLocal[1].split('-') - tvDateTera_ = tvDateTera_[1].split('-') - - tvDateLocal = datetime(int(tvDateLocal[0]),int(tvDateLocal[1]),int(tvDateLocal[2])) - tvDateTera_ = datetime(int(tvDateTera_[0]),int(tvDateTera_[1]),int(tvDateTera_[2])) - - update = tvDateTera_ >= tvDateLocal - outString += ' | '+('yes' if update else 'no ') + ' |' - pyTee(outString) - if update: - copyList.append(tvFile) -pyTee('_____________________________________________________________________') - -for tvFile in copyList: - pyTee('Copying '+tvFile+' from Tera') - os.system('scp -r'+tera+':/courses/e190ax/buildroot_boot/'+tvFile+' ./') -pyTee('Done!') -logFile.close() diff --git a/tests/linux-testgen/linux-testvectors/tvLinker.sh b/tests/linux-testgen/linux-testvectors/tvLinker.sh deleted file mode 100755 index ff7dc3e5..00000000 --- a/tests/linux-testgen/linux-testvectors/tvLinker.sh +++ /dev/null @@ -1,3 +0,0 @@ -echo "Warning: this script will only work if your repo is on Tera" -ln -s /courses/e190ax/linux-testvectors-shared/* ./ -echo "Done!" diff --git a/tests/linux-testgen/linux-testvectors/tvUnlinker.sh b/tests/linux-testgen/linux-testvectors/tvUnlinker.sh deleted file mode 100755 index acf155c0..00000000 --- a/tests/linux-testgen/linux-testvectors/tvUnlinker.sh +++ /dev/null @@ -1,9 +0,0 @@ -# This could be nice to use if you want to mess with the testvectors -# without corrupting the stable copies on Tera. -unlink all.txt -unlink bootmem.txt -unlink ram.txt -unlink vmlinux.objdump -unlink vmlinux.objdump.addr -unlink vmlinux.objdump.lab -echo "Done!" diff --git a/tests/linux-testgen/qemu-build-instructions.md b/tests/linux-testgen/qemu-build-instructions.md deleted file mode 100644 index fc866660..00000000 --- a/tests/linux-testgen/qemu-build-instructions.md +++ /dev/null @@ -1,10 +0,0 @@ -cd -git clone https://github.com/qemu/qemu -cd qemu -git checkout dbdc621be937d9efe3e4dff994e54e8eea051f7a -git apply wallyVirtIO.patch # located in riscv-wally/pipelined/linux-testgen/wallyVirtIO.patch -sudo apt install ninja-build # or your equivalent -sudo apt install libglib2.0-dev # or your equivalent -sudo apt install libpixman-1-dev libcairo2-dev libpango1.0-dev libjpeg8-dev libgif-dev -./configure --target-list=riscv64-softmmu -make --jobs diff --git a/tests/linux-testgen/qemu-patches/README b/tests/linux-testgen/qemu-patches/README deleted file mode 100644 index 02f7e076..00000000 --- a/tests/linux-testgen/qemu-patches/README +++ /dev/null @@ -1,2 +0,0 @@ -replace /qemu/target/riscv/cpu.c with the provided cpu.c -replace /qemu/hw/riscv/virt.c with the provided virt.c diff --git a/tests/linux-testgen/qemu-patches/cpu.c b/tests/linux-testgen/qemu-patches/cpu.c deleted file mode 100644 index 82aad33a..00000000 --- a/tests/linux-testgen/qemu-patches/cpu.c +++ /dev/null @@ -1,722 +0,0 @@ -/* - * QEMU RISC-V CPU - * - * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu - * Copyright (c) 2017-2018 SiFive, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2 or later, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ - -#include "qemu/osdep.h" -#include "qemu/qemu-print.h" -#include "qemu/ctype.h" -#include "qemu/log.h" -#include "cpu.h" -#include "internals.h" -#include "exec/exec-all.h" -#include "qapi/error.h" -#include "qemu/error-report.h" -#include "hw/qdev-properties.h" -#include "migration/vmstate.h" -#include "fpu/softfloat-helpers.h" - -/* RISC-V CPU definitions */ - -static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG"; - -const char * const riscv_int_regnames[] = { - "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", - "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", - "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", - "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", - "x28/t3", "x29/t4", "x30/t5", "x31/t6" -}; - -const char * const riscv_fpr_regnames[] = { - "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", - "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", - "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", - "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", - "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", - "f30/ft10", "f31/ft11" -}; - -const char * const riscv_excp_names[] = { - "misaligned_fetch", - "fault_fetch", - "illegal_instruction", - "breakpoint", - "misaligned_load", - "fault_load", - "misaligned_store", - "fault_store", - "user_ecall", - "supervisor_ecall", - "hypervisor_ecall", - "machine_ecall", - "exec_page_fault", - "load_page_fault", - "reserved", - "store_page_fault", - "reserved", - "reserved", - "reserved", - "reserved", - "guest_exec_page_fault", - "guest_load_page_fault", - "reserved", - "guest_store_page_fault", -}; - -const char * const riscv_intr_names[] = { - "u_software", - "s_software", - "vs_software", - "m_software", - "u_timer", - "s_timer", - "vs_timer", - "m_timer", - "u_external", - "vs_external", - "h_external", - "m_external", - "reserved", - "reserved", - "reserved", - "reserved" -}; - -const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) -{ - if (async) { - return (cause < ARRAY_SIZE(riscv_intr_names)) ? - riscv_intr_names[cause] : "(unknown)"; - } else { - return (cause < ARRAY_SIZE(riscv_excp_names)) ? - riscv_excp_names[cause] : "(unknown)"; - } -} - -bool riscv_cpu_is_32bit(CPURISCVState *env) -{ - if (env->misa & RV64) { - return false; - } - - return true; -} - -static void set_misa(CPURISCVState *env, target_ulong misa) -{ - env->misa_mask = env->misa = misa; -} - -static void set_priv_version(CPURISCVState *env, int priv_ver) -{ - env->priv_ver = priv_ver; -} - -static void set_vext_version(CPURISCVState *env, int vext_ver) -{ - env->vext_ver = vext_ver; -} - -static void set_feature(CPURISCVState *env, int feature) -{ - env->features |= (1ULL << feature); -} - -static void set_resetvec(CPURISCVState *env, int resetvec) -{ -#ifndef CONFIG_USER_ONLY - env->resetvec = resetvec; -#endif -} - -static void riscv_any_cpu_init(Object *obj) -{ - CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU); - set_priv_version(env, PRIV_VERSION_1_11_0); -} - -#if defined(TARGET_RISCV64) -static void rv64_base_cpu_init(Object *obj) -{ - CPURISCVState *env = &RISCV_CPU(obj)->env; - /* We set this in the realise function */ - set_misa(env, RV64); -} - -static void rv64_sifive_u_cpu_init(Object *obj) -{ - CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); - set_priv_version(env, PRIV_VERSION_1_10_0); -} - -static void rv64_sifive_e_cpu_init(Object *obj) -{ - CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU); - set_priv_version(env, PRIV_VERSION_1_10_0); - qdev_prop_set_bit(DEVICE(obj), "mmu", false); -} -#else -static void rv32_base_cpu_init(Object *obj) -{ - CPURISCVState *env = &RISCV_CPU(obj)->env; - /* We set this in the realise function */ - set_misa(env, RV32); -} - -static void rv32_sifive_u_cpu_init(Object *obj) -{ - CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); - set_priv_version(env, PRIV_VERSION_1_10_0); -} - -static void rv32_sifive_e_cpu_init(Object *obj) -{ - CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU); - set_priv_version(env, PRIV_VERSION_1_10_0); - qdev_prop_set_bit(DEVICE(obj), "mmu", false); -} - -static void rv32_ibex_cpu_init(Object *obj) -{ - CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RV32 | RVI | RVM | RVC | RVU); - set_priv_version(env, PRIV_VERSION_1_10_0); - qdev_prop_set_bit(DEVICE(obj), "mmu", false); -} - -static void rv32_imafcu_nommu_cpu_init(Object *obj) -{ - CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU); - set_priv_version(env, PRIV_VERSION_1_10_0); - set_resetvec(env, DEFAULT_RSTVEC); - qdev_prop_set_bit(DEVICE(obj), "mmu", false); -} -#endif - -static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) -{ - ObjectClass *oc; - char *typename; - char **cpuname; - - cpuname = g_strsplit(cpu_model, ",", 1); - typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); - oc = object_class_by_name(typename); - g_strfreev(cpuname); - g_free(typename); - if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || - object_class_is_abstract(oc)) { - return NULL; - } - return oc; -} - -static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) -{ - RISCVCPU *cpu = RISCV_CPU(cs); - CPURISCVState *env = &cpu->env; - int i; - -#if !defined(CONFIG_USER_ONLY) - if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); - } -#endif - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); -#ifndef CONFIG_USER_ONLY - - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcounteren ", env->mcounteren); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "misa ", env->misa); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mscratch ", env->mscratch); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "satp ", env->satp); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scounteren ", env->scounteren); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sscratch ", env->sscratch); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec ", env->stvec); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus); - if (riscv_cpu_is_32bit(env)) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", - (target_ulong)(env->mstatus >> 32)); - } - if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", - (target_ulong)env->vsstatus); - } - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", env->mip); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg); - if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg); - } - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg); - if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hedeleg ", env->hedeleg); - } - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec ", env->mtvec); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec ", env->stvec); - if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vstvec ", env->vstvec); - } - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc ", env->mepc); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc ", env->sepc); - if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsepc ", env->vsepc); - } - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause ", env->mcause); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scause ", env->scause); - if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause); - } - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->sbadaddr); - if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2); - } -#endif - - for (i = 0; i < 32; i++) { - qemu_fprintf(f, " %s " TARGET_FMT_lx, - riscv_int_regnames[i], env->gpr[i]); - if ((i & 3) == 3) { - qemu_fprintf(f, "\n"); - } - } - if (flags & CPU_DUMP_FPU) { - for (i = 0; i < 32; i++) { - qemu_fprintf(f, " %s %016" PRIx64, - riscv_fpr_regnames[i], env->fpr[i]); - if ((i & 3) == 3) { - qemu_fprintf(f, "\n"); - } - } - } -} - -static void riscv_cpu_set_pc(CPUState *cs, vaddr value) -{ - RISCVCPU *cpu = RISCV_CPU(cs); - CPURISCVState *env = &cpu->env; - env->pc = value; -} - -static void riscv_cpu_synchronize_from_tb(CPUState *cs, - const TranslationBlock *tb) -{ - RISCVCPU *cpu = RISCV_CPU(cs); - CPURISCVState *env = &cpu->env; - env->pc = tb->pc; -} - -static bool riscv_cpu_has_work(CPUState *cs) -{ -#ifndef CONFIG_USER_ONLY - RISCVCPU *cpu = RISCV_CPU(cs); - CPURISCVState *env = &cpu->env; - /* - * Definition of the WFI instruction requires it to ignore the privilege - * mode and delegation registers, but respect individual enables - */ - return (env->mip & env->mie) != 0; -#else - return true; -#endif -} - -void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, - target_ulong *data) -{ - env->pc = data[0]; -} - -static void riscv_cpu_reset(DeviceState *dev) -{ - CPUState *cs = CPU(dev); - RISCVCPU *cpu = RISCV_CPU(cs); - RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); - CPURISCVState *env = &cpu->env; - - mcc->parent_reset(dev); -#ifndef CONFIG_USER_ONLY - env->priv = PRV_M; - env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); - env->mcause = 0; - env->pc = env->resetvec; - env->two_stage_lookup = false; -#endif - cs->exception_index = EXCP_NONE; - env->load_res = -1; - set_default_nan_mode(1, &env->fp_status); -} - -static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) -{ - RISCVCPU *cpu = RISCV_CPU(s); - if (riscv_cpu_is_32bit(&cpu->env)) { - info->print_insn = print_insn_riscv32; - } else { - info->print_insn = print_insn_riscv64; - } -} - -static void riscv_cpu_realize(DeviceState *dev, Error **errp) -{ - CPUState *cs = CPU(dev); - RISCVCPU *cpu = RISCV_CPU(dev); - CPURISCVState *env = &cpu->env; - RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); - int priv_version = PRIV_VERSION_1_11_0; - int vext_version = VEXT_VERSION_0_07_1; - target_ulong target_misa = env->misa; - Error *local_err = NULL; - - cpu_exec_realizefn(cs, &local_err); - if (local_err != NULL) { - error_propagate(errp, local_err); - return; - } - - if (cpu->cfg.priv_spec) { - if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { - priv_version = PRIV_VERSION_1_11_0; - } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { - priv_version = PRIV_VERSION_1_10_0; - } else { - error_setg(errp, - "Unsupported privilege spec version '%s'", - cpu->cfg.priv_spec); - return; - } - } - - set_priv_version(env, priv_version); - set_vext_version(env, vext_version); - - if (cpu->cfg.mmu) { - set_feature(env, RISCV_FEATURE_MMU); - } - - if (cpu->cfg.pmp) { - set_feature(env, RISCV_FEATURE_PMP); - } - - set_resetvec(env, cpu->cfg.resetvec); - - /* If only XLEN is set for misa, then set misa from properties */ - if (env->misa == RV32 || env->misa == RV64) { - /* Do some ISA extension error checking */ - if (cpu->cfg.ext_i && cpu->cfg.ext_e) { - error_setg(errp, - "I and E extensions are incompatible"); - return; - } - - if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { - error_setg(errp, - "Either I or E extension must be set"); - return; - } - - if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m & - cpu->cfg.ext_a & cpu->cfg.ext_f & - cpu->cfg.ext_d)) { - warn_report("Setting G will also set IMAFD"); - cpu->cfg.ext_i = true; - cpu->cfg.ext_m = true; - cpu->cfg.ext_a = true; - cpu->cfg.ext_f = true; - cpu->cfg.ext_d = true; - } - - /* Set the ISA extensions, checks should have happened above */ - if (cpu->cfg.ext_i) { - target_misa |= RVI; - } - if (cpu->cfg.ext_e) { - target_misa |= RVE; - } - if (cpu->cfg.ext_m) { - target_misa |= RVM; - } - if (cpu->cfg.ext_a) { - target_misa |= RVA; - } - if (cpu->cfg.ext_f) { - target_misa |= RVF; - } - if (cpu->cfg.ext_d) { - target_misa |= RVD; - } - if (cpu->cfg.ext_c) { - target_misa |= RVC; - } - if (cpu->cfg.ext_s) { - target_misa |= RVS; - } - if (cpu->cfg.ext_u) { - target_misa |= RVU; - } - if (cpu->cfg.ext_h) { - target_misa |= RVH; - } - if (cpu->cfg.ext_v) { - target_misa |= RVV; - if (!is_power_of_2(cpu->cfg.vlen)) { - error_setg(errp, - "Vector extension VLEN must be power of 2"); - return; - } - if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { - error_setg(errp, - "Vector extension implementation only supports VLEN " - "in the range [128, %d]", RV_VLEN_MAX); - return; - } - if (!is_power_of_2(cpu->cfg.elen)) { - error_setg(errp, - "Vector extension ELEN must be power of 2"); - return; - } - if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) { - error_setg(errp, - "Vector extension implementation only supports ELEN " - "in the range [8, 64]"); - return; - } - if (cpu->cfg.vext_spec) { - if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) { - vext_version = VEXT_VERSION_0_07_1; - } else { - error_setg(errp, - "Unsupported vector spec version '%s'", - cpu->cfg.vext_spec); - return; - } - } else { - qemu_log("vector version is not specified, " - "use the default value v0.7.1\n"); - } - set_vext_version(env, vext_version); - } - - set_misa(env, target_misa); - } - - riscv_cpu_register_gdb_regs_for_features(cs); - - qemu_init_vcpu(cs); - cpu_reset(cs); - - mcc->parent_realize(dev, errp); -} - -static void riscv_cpu_init(Object *obj) -{ - RISCVCPU *cpu = RISCV_CPU(obj); - - cpu_set_cpustate_pointers(cpu); -} - -static Property riscv_cpu_properties[] = { - DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), - DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), - DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true), - DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), - DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), - DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), - DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), - DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), - DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), - DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), - /* This is experimental so mark with 'x-' */ - DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), - DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), - DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), - DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), - DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), - DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), - DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), - DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), - DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), - DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), - DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), - DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), - DEFINE_PROP_END_OF_LIST(), -}; - -static gchar *riscv_gdb_arch_name(CPUState *cs) -{ - RISCVCPU *cpu = RISCV_CPU(cs); - CPURISCVState *env = &cpu->env; - - if (riscv_cpu_is_32bit(env)) { - return g_strdup("riscv:rv32"); - } else { - return g_strdup("riscv:rv64"); - } -} - -static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) -{ - RISCVCPU *cpu = RISCV_CPU(cs); - - if (strcmp(xmlname, "riscv-csr.xml") == 0) { - return cpu->dyn_csr_xml; - } - - return NULL; -} - -#include "hw/core/tcg-cpu-ops.h" - -static struct TCGCPUOps riscv_tcg_ops = { - .initialize = riscv_translate_init, - .synchronize_from_tb = riscv_cpu_synchronize_from_tb, - .cpu_exec_interrupt = riscv_cpu_exec_interrupt, - .tlb_fill = riscv_cpu_tlb_fill, - -#ifndef CONFIG_USER_ONLY - .do_interrupt = riscv_cpu_do_interrupt, - .do_transaction_failed = riscv_cpu_do_transaction_failed, - .do_unaligned_access = riscv_cpu_do_unaligned_access, -#endif /* !CONFIG_USER_ONLY */ -}; - -static void riscv_cpu_class_init(ObjectClass *c, void *data) -{ - RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); - CPUClass *cc = CPU_CLASS(c); - DeviceClass *dc = DEVICE_CLASS(c); - - device_class_set_parent_realize(dc, riscv_cpu_realize, - &mcc->parent_realize); - - device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset); - - cc->class_by_name = riscv_cpu_class_by_name; - cc->has_work = riscv_cpu_has_work; - cc->dump_state = riscv_cpu_dump_state; - cc->set_pc = riscv_cpu_set_pc; - cc->gdb_read_register = riscv_cpu_gdb_read_register; - cc->gdb_write_register = riscv_cpu_gdb_write_register; - cc->gdb_num_core_regs = 33; -#if defined(TARGET_RISCV32) - cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; -#elif defined(TARGET_RISCV64) - cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; -#endif - cc->gdb_stop_before_watchpoint = true; - cc->disas_set_info = riscv_cpu_disas_set_info; -#ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug; - /* For now, mark unmigratable: */ - cc->vmsd = &vmstate_riscv_cpu; - cc->write_elf64_note = riscv_cpu_write_elf64_note; - cc->write_elf32_note = riscv_cpu_write_elf32_note; -#endif - cc->gdb_arch_name = riscv_gdb_arch_name; - cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; - cc->tcg_ops = &riscv_tcg_ops; - - device_class_set_props(dc, riscv_cpu_properties); -} - -char *riscv_isa_string(RISCVCPU *cpu) -{ - int i; - const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1; - char *isa_str = g_new(char, maxlen); - char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); - for (i = 0; i < sizeof(riscv_exts); i++) { - if (cpu->env.misa & RV(riscv_exts[i])) { - *p++ = qemu_tolower(riscv_exts[i]); - } - } - *p = '\0'; - return isa_str; -} - -static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) -{ - ObjectClass *class_a = (ObjectClass *)a; - ObjectClass *class_b = (ObjectClass *)b; - const char *name_a, *name_b; - - name_a = object_class_get_name(class_a); - name_b = object_class_get_name(class_b); - return strcmp(name_a, name_b); -} - -static void riscv_cpu_list_entry(gpointer data, gpointer user_data) -{ - const char *typename = object_class_get_name(OBJECT_CLASS(data)); - int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); - - qemu_printf("%.*s\n", len, typename); -} - -void riscv_cpu_list(void) -{ - GSList *list; - - list = object_class_get_list(TYPE_RISCV_CPU, false); - list = g_slist_sort(list, riscv_cpu_list_compare); - g_slist_foreach(list, riscv_cpu_list_entry, NULL); - g_slist_free(list); -} - -#define DEFINE_CPU(type_name, initfn) \ - { \ - .name = type_name, \ - .parent = TYPE_RISCV_CPU, \ - .instance_init = initfn \ - } - -static const TypeInfo riscv_cpu_type_infos[] = { - { - .name = TYPE_RISCV_CPU, - .parent = TYPE_CPU, - .instance_size = sizeof(RISCVCPU), - .instance_align = __alignof__(RISCVCPU), - .instance_init = riscv_cpu_init, - .abstract = true, - .class_size = sizeof(RISCVCPUClass), - .class_init = riscv_cpu_class_init, - }, - DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), -#if defined(TARGET_RISCV32) - DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), -#elif defined(TARGET_RISCV64) - DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), -#endif -}; - -DEFINE_TYPES(riscv_cpu_type_infos) diff --git a/tests/linux-testgen/qemu-patches/virt.c b/tests/linux-testgen/qemu-patches/virt.c deleted file mode 100644 index 358208d1..00000000 --- a/tests/linux-testgen/qemu-patches/virt.c +++ /dev/null @@ -1,451 +0,0 @@ -/* - * QEMU RISC-V VirtIO Board - * - * Copyright (c) 2017 SiFive, Inc. - * - * RISC-V machine with 16550a UART and VirtIO MMIO - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2 or later, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ - -#include "qemu/osdep.h" -#include "qemu/units.h" -#include "qemu/log.h" -#include "qemu/error-report.h" -#include "qapi/error.h" -#include "hw/boards.h" -#include "hw/loader.h" -#include "hw/sysbus.h" -#include "hw/qdev-properties.h" -#include "hw/char/serial.h" -#include "target/riscv/cpu.h" -#include "hw/riscv/riscv_hart.h" -#include "hw/riscv/virt.h" -#include "hw/riscv/boot.h" -#include "hw/riscv/numa.h" -#include "hw/intc/sifive_clint.h" -#include "hw/intc/sifive_plic.h" -#include "hw/misc/sifive_test.h" -#include "chardev/char.h" -#include "sysemu/arch_init.h" -#include "sysemu/device_tree.h" -#include "sysemu/sysemu.h" -#include "hw/pci/pci.h" -#include "hw/pci-host/gpex.h" -#include "hw/display/ramfb.h" - -static const MemMapEntry virt_memmap[] = { - [VIRT_MROM] = { 0x1000, 0xf000 }, - [VIRT_CLINT] = { 0x2000000, 0x10000 }, - [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, - [VIRT_UART0] = { 0x10000000, 0x100 }, - [VIRT_DRAM] = { 0x80000000, 0x0 }, -}; - -/* PCIe high mmio is fixed for RV32 */ -#define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL -#define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB) - -/* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ -#define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) - -#define VIRT_FLASH_SECTOR_SIZE (256 * KiB) - -static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, - uint64_t mem_size, const char *cmdline, bool is_32_bit) -{ - void *fdt; - //int i, cpu, socket; - int cpu, socket; - MachineState *mc = MACHINE(s); - uint64_t addr, size; - uint32_t *clint_cells, *plic_cells; - unsigned long clint_addr, plic_addr; - uint32_t plic_phandle[MAX_NODES]; - uint32_t cpu_phandle, intc_phandle; - uint32_t phandle = 1, plic_mmio_phandle = 1; - char *mem_name, *cpu_name, *core_name, *intc_name; - char *name, *clint_name, *plic_name, *clust_name; - - if (mc->dtb) { - fdt = mc->fdt = load_device_tree(mc->dtb, &s->fdt_size); - if (!fdt) { - error_report("load_device_tree() failed"); - exit(1); - } - goto update_bootargs; - } else { - fdt = mc->fdt = create_device_tree(&s->fdt_size); - if (!fdt) { - error_report("create_device_tree() failed"); - exit(1); - } - } - - qemu_fdt_setprop_string(fdt, "/", "model", "riscv-virtio,qemu"); - qemu_fdt_setprop_string(fdt, "/", "compatible", "riscv-virtio"); - qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); - qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); - - qemu_fdt_add_subnode(fdt, "/soc"); - qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); - qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); - qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); - qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); - - qemu_fdt_add_subnode(fdt, "/cpus"); - qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", - SIFIVE_CLINT_TIMEBASE_FREQ); - qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); - qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); - qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); - - for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { - clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); - qemu_fdt_add_subnode(fdt, clust_name); - - plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); - clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); - - for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { - cpu_phandle = phandle++; - - cpu_name = g_strdup_printf("/cpus/cpu@%d", - s->soc[socket].hartid_base + cpu); - qemu_fdt_add_subnode(fdt, cpu_name); - if (is_32_bit) { - qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32"); - } else { - qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48"); - } - name = riscv_isa_string(&s->soc[socket].harts[cpu]); - qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name); - g_free(name); - qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv"); - qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); - qemu_fdt_setprop_cell(fdt, cpu_name, "reg", - s->soc[socket].hartid_base + cpu); - qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); - riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket); - qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle); - - intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); - qemu_fdt_add_subnode(fdt, intc_name); - intc_phandle = phandle++; - qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle); - qemu_fdt_setprop_string(fdt, intc_name, "compatible", - "riscv,cpu-intc"); - qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1); - - clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); - clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); - clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); - clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); - - plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); - plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); - plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); - plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); - - core_name = g_strdup_printf("%s/core%d", clust_name, cpu); - qemu_fdt_add_subnode(fdt, core_name); - qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle); - - g_free(core_name); - g_free(intc_name); - g_free(cpu_name); - } - - addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket); - size = riscv_socket_mem_size(mc, socket); - mem_name = g_strdup_printf("/memory@%lx", (long)addr); - qemu_fdt_add_subnode(fdt, mem_name); - qemu_fdt_setprop_cells(fdt, mem_name, "reg", - addr >> 32, addr, size >> 32, size); - qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory"); - riscv_socket_fdt_write_id(mc, fdt, mem_name, socket); - g_free(mem_name); - - clint_addr = memmap[VIRT_CLINT].base + - (memmap[VIRT_CLINT].size * socket); - clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); - qemu_fdt_add_subnode(fdt, clint_name); - qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0"); - qemu_fdt_setprop_cells(fdt, clint_name, "reg", - 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); - qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", - clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); - riscv_socket_fdt_write_id(mc, fdt, clint_name, socket); - g_free(clint_name); - - plic_phandle[socket] = phandle++; - plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); - plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); - qemu_fdt_add_subnode(fdt, plic_name); - qemu_fdt_setprop_cell(fdt, plic_name, - "#address-cells", FDT_PLIC_ADDR_CELLS); - qemu_fdt_setprop_cell(fdt, plic_name, - "#interrupt-cells", FDT_PLIC_INT_CELLS); - qemu_fdt_setprop_string(fdt, plic_name, "compatible", "riscv,plic0"); - qemu_fdt_setprop(fdt, plic_name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop(fdt, plic_name, "interrupts-extended", - plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); - qemu_fdt_setprop_cells(fdt, plic_name, "reg", - 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); - qemu_fdt_setprop_cell(fdt, plic_name, "riscv,ndev", VIRTIO_NDEV); - riscv_socket_fdt_write_id(mc, fdt, plic_name, socket); - qemu_fdt_setprop_cell(fdt, plic_name, "phandle", plic_phandle[socket]); - g_free(plic_name); - - g_free(clint_cells); - g_free(plic_cells); - g_free(clust_name); - } - - for (socket = 0; socket < riscv_socket_count(mc); socket++) { - if (socket == 0) { - plic_mmio_phandle = plic_phandle[socket]; - } - } - - riscv_socket_fdt_write_distance_matrix(mc, fdt); - - name = g_strdup_printf("/soc/uart@%lx", (long)memmap[VIRT_UART0].base); - qemu_fdt_add_subnode(fdt, name); - qemu_fdt_setprop_string(fdt, name, "compatible", "ns16550a"); - qemu_fdt_setprop_cells(fdt, name, "reg", - 0x0, memmap[VIRT_UART0].base, - 0x0, memmap[VIRT_UART0].size); - qemu_fdt_setprop_cell(fdt, name, "clock-frequency", 3686400); - qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle); - qemu_fdt_setprop_cell(fdt, name, "interrupts", UART0_IRQ); - - qemu_fdt_add_subnode(fdt, "/chosen"); - qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", name); - g_free(name); - -update_bootargs: - if (cmdline) { - qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); - } -} - -static void virt_machine_init(MachineState *machine) -{ - const MemMapEntry *memmap = virt_memmap; - RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); - MemoryRegion *system_memory = get_system_memory(); - MemoryRegion *main_mem = g_new(MemoryRegion, 1); - MemoryRegion *mask_rom = g_new(MemoryRegion, 1); - char *plic_hart_config, *soc_name; - size_t plic_hart_config_len; - target_ulong start_addr = memmap[VIRT_DRAM].base; - target_ulong firmware_end_addr, kernel_start_addr; - uint32_t fdt_load_addr; - uint64_t kernel_entry; - DeviceState *mmio_plic; - int i, j, base_hartid, hart_count; - - /* Check socket count limit */ - if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) { - error_report("number of sockets/nodes should be less than %d", - VIRT_SOCKETS_MAX); - exit(1); - } - - /* Initialize sockets */ - mmio_plic = NULL; - for (i = 0; i < riscv_socket_count(machine); i++) { - if (!riscv_socket_check_hartids(machine, i)) { - error_report("discontinuous hartids in socket%d", i); - exit(1); - } - - base_hartid = riscv_socket_first_hartid(machine, i); - if (base_hartid < 0) { - error_report("can't find hartid base for socket%d", i); - exit(1); - } - - hart_count = riscv_socket_hart_count(machine, i); - if (hart_count < 0) { - error_report("can't find hart count for socket%d", i); - exit(1); - } - - soc_name = g_strdup_printf("soc%d", i); - object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], - TYPE_RISCV_HART_ARRAY); - g_free(soc_name); - object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", - machine->cpu_type, &error_abort); - object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", - base_hartid, &error_abort); - object_property_set_int(OBJECT(&s->soc[i]), "num-harts", - hart_count, &error_abort); - sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort); - - /* Per-socket CLINT */ - sifive_clint_create( - memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, - memmap[VIRT_CLINT].size, base_hartid, hart_count, - SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, - SIFIVE_CLINT_TIMEBASE_FREQ, true); - - /* Per-socket PLIC hart topology configuration string */ - plic_hart_config_len = - (strlen(VIRT_PLIC_HART_CONFIG) + 1) * hart_count; - plic_hart_config = g_malloc0(plic_hart_config_len); - for (j = 0; j < hart_count; j++) { - if (j != 0) { - strncat(plic_hart_config, ",", plic_hart_config_len); - } - strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG, - plic_hart_config_len); - plic_hart_config_len -= (strlen(VIRT_PLIC_HART_CONFIG) + 1); - } - - /* Per-socket PLIC */ - s->plic[i] = sifive_plic_create( - memmap[VIRT_PLIC].base + i * memmap[VIRT_PLIC].size, - plic_hart_config, base_hartid, - VIRT_PLIC_NUM_SOURCES, - VIRT_PLIC_NUM_PRIORITIES, - VIRT_PLIC_PRIORITY_BASE, - VIRT_PLIC_PENDING_BASE, - VIRT_PLIC_ENABLE_BASE, - VIRT_PLIC_ENABLE_STRIDE, - VIRT_PLIC_CONTEXT_BASE, - VIRT_PLIC_CONTEXT_STRIDE, - memmap[VIRT_PLIC].size); - g_free(plic_hart_config); - - /* Try to use different PLIC instance based device type */ - if (i == 0) { - mmio_plic = s->plic[i]; - } - } - - if (riscv_is_32bit(&s->soc[0])) { -#if HOST_LONG_BITS == 64 - /* limit RAM size in a 32-bit system */ - if (machine->ram_size > 10 * GiB) { - machine->ram_size = 10 * GiB; - error_report("Limiting RAM size to 10 GiB"); - } -#endif - } - - /* register system main memory (actual RAM) */ - memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram", - machine->ram_size, &error_fatal); - memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base, - main_mem); - - /* create device tree */ - create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, - riscv_is_32bit(&s->soc[0])); - - /* boot rom */ - memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", - memmap[VIRT_MROM].size, &error_fatal); - memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, - mask_rom); - - if (riscv_is_32bit(&s->soc[0])) { - firmware_end_addr = riscv_find_and_load_firmware(machine, - "opensbi-riscv32-generic-fw_dynamic.bin", - start_addr, NULL); - } else { - firmware_end_addr = riscv_find_and_load_firmware(machine, - "opensbi-riscv64-generic-fw_dynamic.bin", - start_addr, NULL); - } - - if (machine->kernel_filename) { - kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], - firmware_end_addr); - - kernel_entry = riscv_load_kernel(machine->kernel_filename, - kernel_start_addr, NULL); - - if (machine->initrd_filename) { - hwaddr start; - hwaddr end = riscv_load_initrd(machine->initrd_filename, - machine->ram_size, kernel_entry, - &start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", - "linux,initrd-start", start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", - end); - } - } else { - /* - * If dynamic firmware is used, it doesn't know where is the next mode - * if kernel argument is not set. - */ - kernel_entry = 0; - } - - /* Compute the fdt load address in dram */ - fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base, - machine->ram_size, machine->fdt); - /* load the reset vector */ - riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, - virt_memmap[VIRT_MROM].base, - virt_memmap[VIRT_MROM].size, kernel_entry, - fdt_load_addr, machine->fdt); - - serial_mm_init(system_memory, memmap[VIRT_UART0].base, - 0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193, - serial_hd(0), DEVICE_LITTLE_ENDIAN); - -} - -static void virt_machine_instance_init(Object *obj) -{ -} - -static void virt_machine_class_init(ObjectClass *oc, void *data) -{ - MachineClass *mc = MACHINE_CLASS(oc); - - mc->desc = "RISC-V VirtIO board"; - mc->init = virt_machine_init; - mc->max_cpus = VIRT_CPUS_MAX; - mc->default_cpu_type = TYPE_RISCV_CPU_BASE; - mc->pci_allow_0_address = true; - mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; - mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; - mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; - mc->numa_mem_supported = true; - - machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); -} - -static const TypeInfo virt_machine_typeinfo = { - .name = MACHINE_TYPE_NAME("virt"), - .parent = TYPE_MACHINE, - .class_init = virt_machine_class_init, - .instance_init = virt_machine_instance_init, - .instance_size = sizeof(RISCVVirtState), -}; - -static void virt_machine_init_register_types(void) -{ - type_register_static(&virt_machine_typeinfo); -} - -type_init(virt_machine_init_register_types) - diff --git a/tests/linux-testgen/wallyVirtIO.patch b/tests/linux-testgen/wallyVirtIO.patch deleted file mode 100644 index 76a1d240..00000000 --- a/tests/linux-testgen/wallyVirtIO.patch +++ /dev/null @@ -1,542 +0,0 @@ -diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c -index 4a3cd2599a..39b46e3122 100644 ---- a/hw/riscv/virt.c -+++ b/hw/riscv/virt.c -@@ -20,6 +20,7 @@ - - #include "qemu/osdep.h" - #include "qemu/units.h" -+#include "qemu/log.h" - #include "qemu/error-report.h" - #include "qapi/error.h" - #include "hw/boards.h" -@@ -44,19 +45,10 @@ - #include "hw/display/ramfb.h" - - static const MemMapEntry virt_memmap[] = { -- [VIRT_DEBUG] = { 0x0, 0x100 }, - [VIRT_MROM] = { 0x1000, 0xf000 }, -- [VIRT_TEST] = { 0x100000, 0x1000 }, -- [VIRT_RTC] = { 0x101000, 0x1000 }, - [VIRT_CLINT] = { 0x2000000, 0x10000 }, -- [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 }, - [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, - [VIRT_UART0] = { 0x10000000, 0x100 }, -- [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, -- [VIRT_FW_CFG] = { 0x10100000, 0x18 }, -- [VIRT_FLASH] = { 0x20000000, 0x4000000 }, -- [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, -- [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, - [VIRT_DRAM] = { 0x80000000, 0x0 }, - }; - -@@ -67,139 +59,23 @@ static const MemMapEntry virt_memmap[] = { - /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ - #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) - --static MemMapEntry virt_high_pcie_memmap; -- - #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) - --static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, -- const char *name, -- const char *alias_prop_name) --{ -- /* -- * Create a single flash device. We use the same parameters as -- * the flash devices on the ARM virt board. -- */ -- DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); -- -- qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); -- qdev_prop_set_uint8(dev, "width", 4); -- qdev_prop_set_uint8(dev, "device-width", 2); -- qdev_prop_set_bit(dev, "big-endian", false); -- qdev_prop_set_uint16(dev, "id0", 0x89); -- qdev_prop_set_uint16(dev, "id1", 0x18); -- qdev_prop_set_uint16(dev, "id2", 0x00); -- qdev_prop_set_uint16(dev, "id3", 0x00); -- qdev_prop_set_string(dev, "name", name); -- -- object_property_add_child(OBJECT(s), name, OBJECT(dev)); -- object_property_add_alias(OBJECT(s), alias_prop_name, -- OBJECT(dev), "drive"); -- -- return PFLASH_CFI01(dev); --} -- --static void virt_flash_create(RISCVVirtState *s) --{ -- s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0"); -- s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1"); --} -- --static void virt_flash_map1(PFlashCFI01 *flash, -- hwaddr base, hwaddr size, -- MemoryRegion *sysmem) --{ -- DeviceState *dev = DEVICE(flash); -- -- assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); -- assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); -- qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); -- sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); -- -- memory_region_add_subregion(sysmem, base, -- sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), -- 0)); --} -- --static void virt_flash_map(RISCVVirtState *s, -- MemoryRegion *sysmem) --{ -- hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; -- hwaddr flashbase = virt_memmap[VIRT_FLASH].base; -- -- virt_flash_map1(s->flash[0], flashbase, flashsize, -- sysmem); -- virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, -- sysmem); --} -- --static void create_pcie_irq_map(void *fdt, char *nodename, -- uint32_t plic_phandle) --{ -- int pin, dev; -- uint32_t -- full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * FDT_INT_MAP_WIDTH] = {}; -- uint32_t *irq_map = full_irq_map; -- -- /* This code creates a standard swizzle of interrupts such that -- * each device's first interrupt is based on it's PCI_SLOT number. -- * (See pci_swizzle_map_irq_fn()) -- * -- * We only need one entry per interrupt in the table (not one per -- * possible slot) seeing the interrupt-map-mask will allow the table -- * to wrap to any number of devices. -- */ -- for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { -- int devfn = dev * 0x8; -- -- for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { -- int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); -- int i = 0; -- -- irq_map[i] = cpu_to_be32(devfn << 8); -- -- i += FDT_PCI_ADDR_CELLS; -- irq_map[i] = cpu_to_be32(pin + 1); -- -- i += FDT_PCI_INT_CELLS; -- irq_map[i++] = cpu_to_be32(plic_phandle); -- -- i += FDT_PLIC_ADDR_CELLS; -- irq_map[i] = cpu_to_be32(irq_nr); -- -- irq_map += FDT_INT_MAP_WIDTH; -- } -- } -- -- qemu_fdt_setprop(fdt, nodename, "interrupt-map", -- full_irq_map, sizeof(full_irq_map)); -- -- qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", -- 0x1800, 0, 0, 0x7); --} -- - static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, - uint64_t mem_size, const char *cmdline, bool is_32_bit) - { - void *fdt; -- int i, cpu, socket; -+ //int i, cpu, socket; -+ int cpu, socket; - MachineState *mc = MACHINE(s); - uint64_t addr, size; - uint32_t *clint_cells, *plic_cells; - unsigned long clint_addr, plic_addr; - uint32_t plic_phandle[MAX_NODES]; -- uint32_t cpu_phandle, intc_phandle, test_phandle; -+ uint32_t cpu_phandle, intc_phandle; - uint32_t phandle = 1, plic_mmio_phandle = 1; -- uint32_t plic_pcie_phandle = 1, plic_virtio_phandle = 1; - char *mem_name, *cpu_name, *core_name, *intc_name; - char *name, *clint_name, *plic_name, *clust_name; -- hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; -- hwaddr flashbase = virt_memmap[VIRT_FLASH].base; -- static const char * const clint_compat[2] = { -- "sifive,clint0", "riscv,clint0" -- }; -- static const char * const plic_compat[2] = { -- "sifive,plic-1.0.0", "riscv,plic0" -- }; - - if (mc->dtb) { - fdt = mc->fdt = load_device_tree(mc->dtb, &s->fdt_size); -@@ -305,8 +181,7 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, - (memmap[VIRT_CLINT].size * socket); - clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); - qemu_fdt_add_subnode(fdt, clint_name); -- qemu_fdt_setprop_string_array(fdt, clint_name, "compatible", -- (char **)&clint_compat, ARRAY_SIZE(clint_compat)); -+ qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0"); - qemu_fdt_setprop_cells(fdt, clint_name, "reg", - 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); - qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", -@@ -322,8 +197,7 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, - "#address-cells", FDT_PLIC_ADDR_CELLS); - qemu_fdt_setprop_cell(fdt, plic_name, - "#interrupt-cells", FDT_PLIC_INT_CELLS); -- qemu_fdt_setprop_string_array(fdt, plic_name, "compatible", -- (char **)&plic_compat, ARRAY_SIZE(plic_compat)); -+ qemu_fdt_setprop_string(fdt, plic_name, "compatible", "riscv,plic0"); - qemu_fdt_setprop(fdt, plic_name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop(fdt, plic_name, "interrupts-extended", - plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); -@@ -342,95 +216,11 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, - for (socket = 0; socket < riscv_socket_count(mc); socket++) { - if (socket == 0) { - plic_mmio_phandle = plic_phandle[socket]; -- plic_virtio_phandle = plic_phandle[socket]; -- plic_pcie_phandle = plic_phandle[socket]; -- } -- if (socket == 1) { -- plic_virtio_phandle = plic_phandle[socket]; -- plic_pcie_phandle = plic_phandle[socket]; -- } -- if (socket == 2) { -- plic_pcie_phandle = plic_phandle[socket]; - } - } - - riscv_socket_fdt_write_distance_matrix(mc, fdt); - -- for (i = 0; i < VIRTIO_COUNT; i++) { -- name = g_strdup_printf("/soc/virtio_mmio@%lx", -- (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); -- qemu_fdt_add_subnode(fdt, name); -- qemu_fdt_setprop_string(fdt, name, "compatible", "virtio,mmio"); -- qemu_fdt_setprop_cells(fdt, name, "reg", -- 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, -- 0x0, memmap[VIRT_VIRTIO].size); -- qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", -- plic_virtio_phandle); -- qemu_fdt_setprop_cell(fdt, name, "interrupts", VIRTIO_IRQ + i); -- g_free(name); -- } -- -- name = g_strdup_printf("/soc/pci@%lx", -- (long) memmap[VIRT_PCIE_ECAM].base); -- qemu_fdt_add_subnode(fdt, name); -- qemu_fdt_setprop_cell(fdt, name, "#address-cells", FDT_PCI_ADDR_CELLS); -- qemu_fdt_setprop_cell(fdt, name, "#interrupt-cells", FDT_PCI_INT_CELLS); -- qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0x2); -- qemu_fdt_setprop_string(fdt, name, "compatible", "pci-host-ecam-generic"); -- qemu_fdt_setprop_string(fdt, name, "device_type", "pci"); -- qemu_fdt_setprop_cell(fdt, name, "linux,pci-domain", 0); -- qemu_fdt_setprop_cells(fdt, name, "bus-range", 0, -- memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); -- qemu_fdt_setprop(fdt, name, "dma-coherent", NULL, 0); -- qemu_fdt_setprop_cells(fdt, name, "reg", 0, -- memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); -- qemu_fdt_setprop_sized_cells(fdt, name, "ranges", -- 1, FDT_PCI_RANGE_IOPORT, 2, 0, -- 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, -- 1, FDT_PCI_RANGE_MMIO, -- 2, memmap[VIRT_PCIE_MMIO].base, -- 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size, -- 1, FDT_PCI_RANGE_MMIO_64BIT, -- 2, virt_high_pcie_memmap.base, -- 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); -- -- create_pcie_irq_map(fdt, name, plic_pcie_phandle); -- g_free(name); -- -- test_phandle = phandle++; -- name = g_strdup_printf("/soc/test@%lx", -- (long)memmap[VIRT_TEST].base); -- qemu_fdt_add_subnode(fdt, name); -- { -- static const char * const compat[3] = { -- "sifive,test1", "sifive,test0", "syscon" -- }; -- qemu_fdt_setprop_string_array(fdt, name, "compatible", (char **)&compat, -- ARRAY_SIZE(compat)); -- } -- qemu_fdt_setprop_cells(fdt, name, "reg", -- 0x0, memmap[VIRT_TEST].base, -- 0x0, memmap[VIRT_TEST].size); -- qemu_fdt_setprop_cell(fdt, name, "phandle", test_phandle); -- test_phandle = qemu_fdt_get_phandle(fdt, name); -- g_free(name); -- -- name = g_strdup_printf("/soc/reboot"); -- qemu_fdt_add_subnode(fdt, name); -- qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-reboot"); -- qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle); -- qemu_fdt_setprop_cell(fdt, name, "offset", 0x0); -- qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_RESET); -- g_free(name); -- -- name = g_strdup_printf("/soc/poweroff"); -- qemu_fdt_add_subnode(fdt, name); -- qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-poweroff"); -- qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle); -- qemu_fdt_setprop_cell(fdt, name, "offset", 0x0); -- qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_PASS); -- g_free(name); -- - name = g_strdup_printf("/soc/uart@%lx", (long)memmap[VIRT_UART0].base); - qemu_fdt_add_subnode(fdt, name); - qemu_fdt_setprop_string(fdt, name, "compatible", "ns16550a"); -@@ -445,102 +235,12 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, - qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", name); - g_free(name); - -- name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); -- qemu_fdt_add_subnode(fdt, name); -- qemu_fdt_setprop_string(fdt, name, "compatible", "google,goldfish-rtc"); -- qemu_fdt_setprop_cells(fdt, name, "reg", -- 0x0, memmap[VIRT_RTC].base, -- 0x0, memmap[VIRT_RTC].size); -- qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle); -- qemu_fdt_setprop_cell(fdt, name, "interrupts", RTC_IRQ); -- g_free(name); -- -- name = g_strdup_printf("/soc/flash@%" PRIx64, flashbase); -- qemu_fdt_add_subnode(mc->fdt, name); -- qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash"); -- qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg", -- 2, flashbase, 2, flashsize, -- 2, flashbase + flashsize, 2, flashsize); -- qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4); -- g_free(name); -- - update_bootargs: - if (cmdline) { - qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); - } - } - --static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, -- hwaddr ecam_base, hwaddr ecam_size, -- hwaddr mmio_base, hwaddr mmio_size, -- hwaddr high_mmio_base, -- hwaddr high_mmio_size, -- hwaddr pio_base, -- DeviceState *plic) --{ -- DeviceState *dev; -- MemoryRegion *ecam_alias, *ecam_reg; -- MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; -- qemu_irq irq; -- int i; -- -- dev = qdev_new(TYPE_GPEX_HOST); -- -- sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); -- -- ecam_alias = g_new0(MemoryRegion, 1); -- ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); -- memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", -- ecam_reg, 0, ecam_size); -- memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); -- -- mmio_alias = g_new0(MemoryRegion, 1); -- mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); -- memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", -- mmio_reg, mmio_base, mmio_size); -- memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); -- -- /* Map high MMIO space */ -- high_mmio_alias = g_new0(MemoryRegion, 1); -- memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", -- mmio_reg, high_mmio_base, high_mmio_size); -- memory_region_add_subregion(get_system_memory(), high_mmio_base, -- high_mmio_alias); -- -- sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); -- -- for (i = 0; i < GPEX_NUM_IRQS; i++) { -- irq = qdev_get_gpio_in(plic, PCIE_IRQ + i); -- -- sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); -- gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); -- } -- -- return dev; --} -- --static FWCfgState *create_fw_cfg(const MachineState *mc) --{ -- hwaddr base = virt_memmap[VIRT_FW_CFG].base; -- hwaddr size = virt_memmap[VIRT_FW_CFG].size; -- FWCfgState *fw_cfg; -- char *nodename; -- -- fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, -- &address_space_memory); -- fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus); -- -- nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); -- qemu_fdt_add_subnode(mc->fdt, nodename); -- qemu_fdt_setprop_string(mc->fdt, nodename, -- "compatible", "qemu,fw-cfg-mmio"); -- qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg", -- 2, base, 2, size); -- qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0); -- g_free(nodename); -- return fw_cfg; --} -- - static void virt_machine_init(MachineState *machine) - { - const MemMapEntry *memmap = virt_memmap; -@@ -554,7 +254,7 @@ static void virt_machine_init(MachineState *machine) - target_ulong firmware_end_addr, kernel_start_addr; - uint32_t fdt_load_addr; - uint64_t kernel_entry; -- DeviceState *mmio_plic, *virtio_plic, *pcie_plic; -+ DeviceState *mmio_plic; - int i, j, base_hartid, hart_count; - - /* Check socket count limit */ -@@ -565,7 +265,7 @@ static void virt_machine_init(MachineState *machine) - } - - /* Initialize sockets */ -- mmio_plic = virtio_plic = pcie_plic = NULL; -+ mmio_plic = NULL; - for (i = 0; i < riscv_socket_count(machine); i++) { - if (!riscv_socket_check_hartids(machine, i)) { - error_report("discontinuous hartids in socket%d", i); -@@ -634,15 +334,6 @@ static void virt_machine_init(MachineState *machine) - /* Try to use different PLIC instance based device type */ - if (i == 0) { - mmio_plic = s->plic[i]; -- virtio_plic = s->plic[i]; -- pcie_plic = s->plic[i]; -- } -- if (i == 1) { -- virtio_plic = s->plic[i]; -- pcie_plic = s->plic[i]; -- } -- if (i == 2) { -- pcie_plic = s->plic[i]; - } - } - -@@ -654,13 +345,6 @@ static void virt_machine_init(MachineState *machine) - error_report("Limiting RAM size to 10 GiB"); - } - #endif -- virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE; -- virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE; -- } else { -- virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE; -- virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size; -- virt_high_pcie_memmap.base = -- ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size); - } - - /* register system main memory (actual RAM) */ -@@ -681,10 +365,12 @@ static void virt_machine_init(MachineState *machine) - - if (riscv_is_32bit(&s->soc[0])) { - firmware_end_addr = riscv_find_and_load_firmware(machine, -- RISCV32_BIOS_BIN, start_addr, NULL); -+ "opensbi-riscv32-generic-fw_dynamic.bin", -+ start_addr, NULL); - } else { - firmware_end_addr = riscv_find_and_load_firmware(machine, -- RISCV64_BIOS_BIN, start_addr, NULL); -+ "opensbi-riscv64-generic-fw_dynamic.bin", -+ start_addr, NULL); - } - - if (machine->kernel_filename) { -@@ -712,21 +398,6 @@ static void virt_machine_init(MachineState *machine) - kernel_entry = 0; - } - -- if (drive_get(IF_PFLASH, 0, 0)) { -- /* -- * Pflash was supplied, let's overwrite the address we jump to after -- * reset to the base of the flash. -- */ -- start_addr = virt_memmap[VIRT_FLASH].base; -- } -- -- /* -- * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device -- * tree cannot be altered and we get FDT_ERR_NOSPACE. -- */ -- s->fw_cfg = create_fw_cfg(machine); -- rom_set_fw(s->fw_cfg); -- - /* Compute the fdt load address in dram */ - fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base, - machine->ram_size, machine->fdt); -@@ -736,41 +407,10 @@ static void virt_machine_init(MachineState *machine) - virt_memmap[VIRT_MROM].size, kernel_entry, - fdt_load_addr, machine->fdt); - -- /* SiFive Test MMIO device */ -- sifive_test_create(memmap[VIRT_TEST].base); -- -- /* VirtIO MMIO devices */ -- for (i = 0; i < VIRTIO_COUNT; i++) { -- sysbus_create_simple("virtio-mmio", -- memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, -- qdev_get_gpio_in(DEVICE(virtio_plic), VIRTIO_IRQ + i)); -- } -- -- gpex_pcie_init(system_memory, -- memmap[VIRT_PCIE_ECAM].base, -- memmap[VIRT_PCIE_ECAM].size, -- memmap[VIRT_PCIE_MMIO].base, -- memmap[VIRT_PCIE_MMIO].size, -- virt_high_pcie_memmap.base, -- virt_high_pcie_memmap.size, -- memmap[VIRT_PCIE_PIO].base, -- DEVICE(pcie_plic)); -- -- serial_mm_init(system_memory, memmap[VIRT_UART0].base, -+ serial_mm_init(system_memory, memmap[VIRT_UART0].base, - 0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193, - serial_hd(0), DEVICE_LITTLE_ENDIAN); - -- sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, -- qdev_get_gpio_in(DEVICE(mmio_plic), RTC_IRQ)); -- -- virt_flash_create(s); -- -- for (i = 0; i < ARRAY_SIZE(s->flash); i++) { -- /* Map legacy -drive if=pflash to machine properties */ -- pflash_cfi01_legacy_drive(s->flash[i], -- drive_get(IF_PFLASH, 0, i)); -- } -- virt_flash_map(s, system_memory); - } - - static void virt_machine_instance_init(Object *obj) -diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c -index 991a6bb760..401028b8d9 100644 ---- a/target/riscv/cpu.c -+++ b/target/riscv/cpu.c -@@ -269,6 +269,15 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", env->mip); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg); -+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcounteren ", env->mcounteren); -+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "misa ", env->misa); -+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mscratch ", env->mscratch); -+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "satp ", env->satp); -+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scounteren ", env->scounteren); -+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sscratch ", env->sscratch); -+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec ", env->stvec); -+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); -+ - if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg); - }