diff --git a/pipelined/src/fma/fma.do b/pipelined/src/fma/fma.do
index 9a7de126..6e6863d5 100644
--- a/pipelined/src/fma/fma.do
+++ b/pipelined/src/fma/fma.do
@@ -8,7 +8,7 @@ onbreak {resume}
 # create library
 vlib worklib
 
-vlog -lint -work worklib fma16.sv testbench.v
+vlog -lint -work worklib fma16.v testbench.v
 vopt +acc worklib.testbench_fma16 -work worklib -o testbenchopt
 vsim -lib worklib testbenchopt
 
diff --git a/pipelined/src/fma/lint-fma b/pipelined/src/fma/lint-fma
index 462d5350..290bf69f 100755
--- a/pipelined/src/fma/lint-fma
+++ b/pipelined/src/fma/lint-fma
@@ -5,4 +5,4 @@ export PATH=$PATH:/usr/local/bin/
 verilator=`which verilator`
 
 basepath=$(dirname $0)/..
-$verilator --lint-only --top-module fma16 fma16.sv
+$verilator --lint-only --top-module fma16 fma16.v
diff --git a/pipelined/src/fma/synth b/pipelined/src/fma/synth
new file mode 100755
index 00000000..0ced41c8
--- /dev/null
+++ b/pipelined/src/fma/synth
@@ -0,0 +1 @@
+make -C ../../../synthDC synth DESIGN=fma16
diff --git a/pipelined/src/generic/flop/bram2p1r1w.sv b/pipelined/src/generic/flop/bram2p1r1w.sv
index 4ccfa1c1..58038b8c 100644
--- a/pipelined/src/generic/flop/bram2p1r1w.sv
+++ b/pipelined/src/generic/flop/bram2p1r1w.sv
@@ -54,9 +54,22 @@ module bram2p1r1w
 	   input logic [ADDR_WIDTH-1:0]  addrB,
 	   input logic [DATA_WIDTH-1:0]  dinB
 	   );
-  // Core Memory
+
+
+
+  // *** TODO.
+/* -----\/----- EXCLUDED -----\/-----
+  if(`SRAM) begin
+    // instanciate SRAM model
+    // need multiple SRAM instances to map into correct dimentions.
+    // also map the byte write enables onto bit write enables.
+  end else begin // FPGA or infered flip flop memory
+    // Core Memory
+  end
+ -----/\----- EXCLUDED -----/\----- */
+
   logic [DATA_WIDTH-1:0] 			 RAM [(2**ADDR_WIDTH)-1:0];
-  integer 							 i;
+  integer                            i;
 
 /* -----\/----- EXCLUDED -----\/-----
   initial begin
@@ -128,4 +141,5 @@ module bram2p1r1w
 	  end
 	end
   end
+  
 endmodule // bytewrite_tdp_ram_rf
diff --git a/pipelined/src/mmu/adrdecs.sv b/pipelined/src/mmu/adrdecs.sv
index 5464f4ac..0104ca57 100644
--- a/pipelined/src/mmu/adrdecs.sv
+++ b/pipelined/src/mmu/adrdecs.sv
@@ -37,7 +37,6 @@ module adrdecs (
   input  logic [1:0]          Size,
   output logic [8:0]          SelRegions
 );
-  logic [3:0] clintaccesssize;
 
  // Determine which region of physical memory (if any) is being accessed
  // *** eventually uncomment Access signals
@@ -45,8 +44,7 @@ module adrdecs (
   adrdec boottimdec(PhysicalAddress, `BOOTROM_BASE, `BOOTROM_RANGE, `BOOTROM_SUPPORTED, /*1'b1*/AccessRX, Size, 4'b1111, SelRegions[6]);
   adrdec timdec(PhysicalAddress, `RAM_BASE, `RAM_RANGE, `RAM_SUPPORTED, /*1'b1*/AccessRWX, Size, 4'b1111, SelRegions[5]);
 
-  assign clintaccesssize = (`XLEN==64) ? 4'b1000 : 4'b0100;
-  adrdec clintdec(PhysicalAddress, `CLINT_BASE, `CLINT_RANGE, `CLINT_SUPPORTED, AccessRW, Size, clintaccesssize, SelRegions[4]);
+  adrdec clintdec(PhysicalAddress, `CLINT_BASE, `CLINT_RANGE, `CLINT_SUPPORTED, AccessRW, Size, 4'b1111, SelRegions[4]);
   adrdec gpiodec(PhysicalAddress, `GPIO_BASE, `GPIO_RANGE, `GPIO_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[3]);
   adrdec uartdec(PhysicalAddress, `UART_BASE, `UART_RANGE, `UART_SUPPORTED, AccessRW, Size, 4'b0001, SelRegions[2]);
   adrdec plicdec(PhysicalAddress, `PLIC_BASE, `PLIC_RANGE, `PLIC_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[1]);
diff --git a/pipelined/src/uncore/clint.sv b/pipelined/src/uncore/clint.sv
index be40d152..f3ee4f5c 100644
--- a/pipelined/src/uncore/clint.sv
+++ b/pipelined/src/uncore/clint.sv
@@ -35,6 +35,7 @@ module clint (
   input  logic             HCLK, HRESETn, TIMECLK,
   input  logic             HSELCLINT,
   input  logic [15:0]      HADDR,
+  input  logic [3:0]       HSIZED,
   input  logic             HWRITE,
   input  logic [`XLEN-1:0] HWDATA,
   input  logic             HREADY,
@@ -50,6 +51,8 @@ module clint (
   logic memwrite;
   logic initTrans;
   logic [63:0] MTIMECMP;
+  logic [`XLEN/8-1:0] ByteMaskM;
+  integer             i;
 
   assign initTrans = HREADY & HSELCLINT & (HTRANS != 2'b00);
   // entryd and memwrite are delayed by a cycle because AHB controller waits a cycle before outputting write data
@@ -63,6 +66,9 @@ module clint (
   if (`XLEN==64) assign #2 entry = {HADDR[15:3], 3'b000};
   else           assign #2 entry = {HADDR[15:2], 2'b00}; 
   
+  swbytemask swbytemask(.HSIZED, .HADDRD(entryd[2:0]), .ByteMask(ByteMaskM));
+
+
   // DH 2/20/21: Eventually allow MTIME to run off a separate clock
   // This will require synchronizing MTIME to the system clock
   // before it is read or compared to MTIMECMP.
@@ -86,7 +92,11 @@ module clint (
         // MTIMECMP is not reset
       end else if (memwrite) begin
         if (entryd == 16'h0000) MSIP <= HWDATA[0];
-        if (entryd == 16'h4000) MTIMECMP <= HWDATA;
+        if (entryd == 16'h4000) begin
+          for(i=0;i<`XLEN/8;i++)
+            if(ByteMaskM[i])
+              MTIMECMP[i*8 +: 8] <= HWDATA[i*8 +: 8];
+        end
       end
 
 // eventually replace MTIME logic below with timereg
@@ -98,7 +108,9 @@ module clint (
         // MTIMECMP is not reset
       end else if (memwrite & entryd == 16'hBFF8) begin
         // MTIME Counter.  Eventually change this to run off separate clock.  Synchronization then needed
-        MTIME <= HWDATA;
+        for(i=0;i<`XLEN/8;i++)
+          if(ByteMaskM[i])
+            MTIME[i*8 +: 8] <= HWDATA[i*8 +: 8];
       end else MTIME <= MTIME + 1; 
   end else begin:clint // 32-bit
     always @(posedge HCLK) begin
@@ -118,8 +130,14 @@ module clint (
         // MTIMECMP is not reset ***?
       end else if (memwrite) begin
         if (entryd == 16'h0000) MSIP <= HWDATA[0];
-        if (entryd == 16'h4000) MTIMECMP[31:0] <= HWDATA;
-        if (entryd == 16'h4004) MTIMECMP[63:32] <= HWDATA;
+        if (entryd == 16'h4000) 
+          for(i=0;i<`XLEN/8;i++)
+            if(ByteMaskM[i])
+              MTIMECMP[i*8 +: 8] <= HWDATA[i*8 +: 8];
+        if (entryd == 16'h4004) 
+          for(i=0;i<`XLEN/8;i++)
+            if(ByteMaskM[i])
+              MTIMECMP[32 + i*8 +: 8] <= HWDATA[i*8 +: 8];
         // MTIME Counter.  Eventually change this to run off separate clock.  Synchronization then needed
       end
 
@@ -130,10 +148,14 @@ module clint (
         MTIME <= 0;
         // MTIMECMP is not reset
       end else if (memwrite & (entryd == 16'hBFF8)) begin
-        MTIME[31:0] <= HWDATA;
+        for(i=0;i<`XLEN/8;i++)
+          if(ByteMaskM[i])
+            MTIME[i*8 +: 8] <= HWDATA[i*8 +: 8];
       end else if (memwrite & (entryd == 16'hBFFC)) begin
         // MTIME Counter.  Eventually change this to run off separate clock.  Synchronization then needed
-        MTIME[63:32]<= HWDATA;
+        for(i=0;i<`XLEN/8;i++)
+          if(ByteMaskM[i])
+            MTIME[32 + i*8 +: 8]<= HWDATA[i*8 +: 8];
       end else MTIME <= MTIME + 1;
   end 
 
diff --git a/pipelined/src/uncore/uncore.sv b/pipelined/src/uncore/uncore.sv
index 17daf50b..7649745b 100644
--- a/pipelined/src/uncore/uncore.sv
+++ b/pipelined/src/uncore/uncore.sv
@@ -116,7 +116,7 @@ module uncore (
       clint clint(
         .HCLK, .HRESETn, .TIMECLK,
         .HSELCLINT, .HADDR(HADDR[15:0]), .HWRITE,
-        .HWDATA, .HREADY, .HTRANS,
+        .HWDATA, .HREADY, .HTRANS, .HSIZED,
         .HREADCLINT,
         .HRESPCLINT, .HREADYCLINT,
         .MTIME(MTIME_CLINT), 
diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl
index 3146e14e..d79009fe 100755
--- a/synthDC/scripts/synth.tcl
+++ b/synthDC/scripts/synth.tcl
@@ -28,6 +28,9 @@ eval file copy -force [glob ${hdl_src}/../config/shared/*.vh] {hdl/}
 eval file copy -force [glob ${hdl_src}/*/*.sv] {hdl/}
 eval file copy -force [glob ${hdl_src}/*/flop/*.sv] {hdl/}
 
+# Only for FMA class project; comment out when done
+eval file copy -force [glob ${hdl_src}/fma/fma16.v] {hdl/}
+
 # Enables name mapping
 if { $saifpower == 1 } {
     saif_map -start