diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index 4669e48c..4058b4f0 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -26,7 +26,7 @@ add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/Ret add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/DataStall +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/DCacheStall add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD @@ -212,7 +212,7 @@ add wave -noupdate -group icache -expand -group pc /testbench/dut/hart/ifu/icach add wave -noupdate -group AHB -expand -group read /testbench/dut/hart/ebu/HRDATA add wave -noupdate -group AHB -expand -group read /testbench/dut/hart/ebu/HRDATAMasked add wave -noupdate -group AHB -expand -group read /testbench/dut/hart/ebu/HRDATANext -add wave -noupdate -group AHB /testbench/dut/hart/ebu/BusState +add wave -noupdate -group AHB -color Gold /testbench/dut/hart/ebu/BusState add wave -noupdate -group AHB /testbench/dut/hart/ebu/ProposedNextBusState add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState add wave -noupdate -group AHB /testbench/dut/hart/ebu/DSquashBusAccessM @@ -306,15 +306,16 @@ add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/T add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/ValidPTE add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/LeafPTE add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/MMUStall -add wave -noupdate -expand -group ptwalker -expand -group {fsm outputs} /testbench/dut/hart/pagetablewalker/TranslationPAdr -add wave -noupdate -expand -group ptwalker -expand -group {fsm outputs} /testbench/dut/hart/pagetablewalker/PageTableEntry -add wave -noupdate -expand -group ptwalker -expand -group {fsm outputs} /testbench/dut/hart/pagetablewalker/PageType -add wave -noupdate -expand -group ptwalker -expand -group {fsm outputs} /testbench/dut/hart/pagetablewalker/ITLBWriteF -add wave -noupdate -expand -group ptwalker -expand -group {fsm outputs} /testbench/dut/hart/pagetablewalker/DTLBWriteM -add wave -noupdate -expand -group ptwalker -expand -group {fsm outputs} /testbench/dut/hart/pagetablewalker/WalkerInstrPageFaultF -add wave -noupdate -expand -group ptwalker -expand -group {fsm outputs} /testbench/dut/hart/pagetablewalker/WalkerLoadPageFaultM -add wave -noupdate -expand -group ptwalker -expand -group {fsm outputs} /testbench/dut/hart/pagetablewalker/WalkerStorePageFaultM -add wave -noupdate -expand -group ptwalker -expand -group {fsm outputs} /testbench/dut/hart/pagetablewalker/MMUStall +add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/TranslationPAdr +add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/PageTableEntry +add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/PageType +add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/ITLBWriteF +add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/DTLBWriteM +add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/WalkerInstrPageFaultF +add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/WalkerLoadPageFaultM +add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/WalkerStorePageFaultM +add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/MMUStall +add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/EndWalk add wave -noupdate -expand -group {LSU ARB} -color Gold /testbench/dut/hart/arbiter/CurrState add wave -noupdate -expand -group {LSU ARB} /testbench/dut/hart/arbiter/SelPTW add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/arbiter/HPTWTranslate @@ -349,9 +350,10 @@ add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genb add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/TXRDYb add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/RXRDYb add wave -noupdate -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss +add wave -noupdate -expand -group dtlb /testbench/dut/hart/lsu/dmmu/tlb/TLBWrite add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/ITLBMissF TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 5} {11172515 ns} 0} {{Cursor 8} {3207 ns} 0} +WaveRestoreCursors {{Cursor 5} {11172515 ns} 0} {{Cursor 8} {3377 ns} 0} quietly wave cursor active 2 configure wave -namecolwidth 250 configure wave -valuecolwidth 189 @@ -367,4 +369,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {2930 ns} {3454 ns} +WaveRestoreZoom {3091 ns} {3683 ns} diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index cd37ce94..709b9a24 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -111,7 +111,9 @@ module lsu ( STATE_FETCH_AMO_1, STATE_FETCH_AMO_2, STATE_STALLED, - STATE_TLB_MISS} statetype; + STATE_PTW_READY, + STATE_PTW_FETCH, + STATE_PTW_DONE} statetype; statetype CurrState, NextState; @@ -160,8 +162,8 @@ module lsu ( // Changed DataMisalignedM to a larger combination of trap sources // NonBusTrapM is anything that the bus doesn't contribute to producing // By contrast, using TrapM results in circular logic errors - assign MemReadM = MemRWM[1] & ~NonBusTrapM & CurrState != STATE_STALLED; - assign MemWriteM = MemRWM[0] & ~NonBusTrapM && ~SquashSCM & CurrState != STATE_STALLED; + assign MemReadM = MemRWM[1] & ~NonBusTrapM & ~DTLBMissM & CurrState != STATE_STALLED; + assign MemWriteM = MemRWM[0] & ~NonBusTrapM & ~DTLBMissM & ~SquashSCM & CurrState != STATE_STALLED; assign AtomicMaskedM = CurrState != STATE_STALLED ? AtomicM : 2'b00 ; assign MemAccessM = MemReadM | MemWriteM; @@ -222,7 +224,7 @@ module lsu ( case (CurrState) STATE_READY: if (DTLBMissM) begin - NextState = STATE_READY; + NextState = STATE_PTW_READY; DataStall = 1'b0; end else if (AtomicMaskedM[1]) begin NextState = STATE_FETCH_AMO_1; // *** should be some misalign check @@ -273,13 +275,29 @@ module lsu ( NextState = STATE_STALLED; end end - STATE_TLB_MISS: begin + STATE_PTW_READY: begin + DataStall = 1'b0; if (DTLBWriteM) begin - NextState = STATE_READY; + NextState = STATE_PTW_DONE; + end else if (MemReadM & ~DataMisalignedM) begin + NextState = STATE_PTW_FETCH; end else begin - NextState = STATE_TLB_MISS; + NextState = STATE_PTW_READY; end end + STATE_PTW_FETCH : begin + DataStall = 1'b1; + if (MemAckW & ~DTLBWriteM) begin + NextState = STATE_PTW_READY; + end else if (MemAckW & DTLBWriteM) begin + NextState = STATE_PTW_DONE; + end else begin + NextState = STATE_PTW_FETCH; + end + end + STATE_PTW_DONE: begin + NextState = STATE_READY; + end default: begin DataStall = 1'b0; NextState = STATE_READY; diff --git a/wally-pipelined/src/lsu/lsuArb.sv b/wally-pipelined/src/lsu/lsuArb.sv index dce509f7..bf925704 100644 --- a/wally-pipelined/src/lsu/lsuArb.sv +++ b/wally-pipelined/src/lsu/lsuArb.sv @@ -121,7 +121,7 @@ module lsuArb // multiplex the outputs to LSU assign DisableTranslation = SelPTW; // change names between SelPTW would be confusing in DTLB. - assign SelPTW = (CurrState == StatePTWActive) || (CurrState == StateReady && HPTWTranslate); + assign SelPTW = (CurrState == StatePTWActive && HPTWTranslate) || (CurrState == StateReady && HPTWTranslate); assign MemRWMtoLSU = SelPTW ? {HPTWRead, 1'b0} : MemRWM; generate @@ -158,6 +158,6 @@ module lsuArb .q(HPTWStall)); -----/\----- EXCLUDED -----/\----- */ - assign DCacheStall = SelPTW ? 1'b0 : DataStall; // *** this is probably going to change. + assign DCacheStall = SelPTW ? 1'b1 : DataStall; // *** this is probably going to change. endmodule diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv index e917e83c..160dccc3 100644 --- a/wally-pipelined/src/mmu/pagetablewalker.sv +++ b/wally-pipelined/src/mmu/pagetablewalker.sv @@ -148,9 +148,13 @@ module pagetablewalker ( assign StartWalk = WalkerState == IDLE && (DTLBMissM | ITLBMissF); - assign EndWalk = WalkerState == LEAF; + assign EndWalk = (WalkerState == LEVEL0 && ValidPTE && LeafPTE && ~AccessAlert) || + (WalkerState == LEVEL1 && ValidPTE && LeafPTE && ~AccessAlert) || + (WalkerState == LEVEL2 && ValidPTE && LeafPTE && ~AccessAlert) || + (WalkerState == LEVEL3 && ValidPTE && LeafPTE && ~AccessAlert) || + (WalkerState == FAULT); - assign MMUTranslate = DTLBMissMQ | ITLBMissFQ; + assign MMUTranslate = (DTLBMissMQ | ITLBMissFQ) & ~EndWalk; //assign MMUTranslate = DTLBMissM | ITLBMissF; // unswizzle PTE bits @@ -304,6 +308,10 @@ module pagetablewalker ( TranslationPAdr = '0; HPTWRead = 1'b0; MMUStall = 1'b1; + PageTableEntry = '0; + PageType = '0; + DTLBWriteM = '0; + ITLBWriteF = '0; WalkerInstrPageFaultF = 1'b0; WalkerLoadPageFaultM = 1'b0; @@ -343,7 +351,13 @@ module pagetablewalker ( // access bit. The following commented line of code is // supposed to perform that check. However, it is untested. if (ValidPTE && LeafPTE && ~BadTerapage) begin - NextWalkerState = LEAF; + NextWalkerState = IDLE; + PageTableEntry = CurrentPTE; + PageType = (WalkerState == LEVEL3) ? 2'b11 : + ((WalkerState == LEVEL2) ? 2'b10 : + ((WalkerState == LEVEL1) ? 2'b01 : 2'b00)); + DTLBWriteM = DTLBMissMQ; + ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions end // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. else if (ValidPTE && ~LeafPTE) begin @@ -376,7 +390,13 @@ module pagetablewalker ( // access bit. The following commented line of code is // supposed to perform that check. However, it is untested. if (ValidPTE && LeafPTE && ~BadGigapage) begin - NextWalkerState = LEAF; + NextWalkerState = IDLE; + PageTableEntry = CurrentPTE; + PageType = (WalkerState == LEVEL3) ? 2'b11 : + ((WalkerState == LEVEL2) ? 2'b10 : + ((WalkerState == LEVEL1) ? 2'b01 : 2'b00)); + DTLBWriteM = DTLBMissMQ; + ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions end // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. else if (ValidPTE && ~LeafPTE) begin @@ -409,7 +429,14 @@ module pagetablewalker ( // access bit. The following commented line of code is // supposed to perform that check. However, it is untested. if (ValidPTE && LeafPTE && ~BadMegapage) begin - NextWalkerState = LEAF; + NextWalkerState = IDLE; + PageTableEntry = CurrentPTE; + PageType = (WalkerState == LEVEL3) ? 2'b11 : + ((WalkerState == LEVEL2) ? 2'b10 : + ((WalkerState == LEVEL1) ? 2'b01 : 2'b00)); + DTLBWriteM = DTLBMissMQ; + ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions + end // else if (ValidPTE && LeafPTE) NextWalkerState = LEAF; // *** Once the above line is properly tested, delete this line. else if (ValidPTE && ~LeafPTE) begin @@ -437,7 +464,14 @@ module pagetablewalker ( LEVEL0: begin if (ValidPTE && LeafPTE && ~AccessAlert) begin - NextWalkerState = LEAF; + NextWalkerState = IDLE; + PageTableEntry = CurrentPTE; + PageType = (WalkerState == LEVEL3) ? 2'b11 : + ((WalkerState == LEVEL2) ? 2'b10 : + ((WalkerState == LEVEL1) ? 2'b01 : 2'b00)); + DTLBWriteM = DTLBMissMQ; + ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions + end else begin NextWalkerState = FAULT; WalkerInstrPageFaultF = ~DTLBMissMQ; @@ -485,11 +519,12 @@ module pagetablewalker ( always_comb begin // default values //TranslationPAdr = '0; +/* -----\/----- EXCLUDED -----\/----- PageTableEntry = '0; PageType = '0; DTLBWriteM = '0; ITLBWriteF = '0; -/* -----\/----- EXCLUDED -----\/----- + WalkerInstrPageFaultF = '0; WalkerLoadPageFaultM = '0; WalkerStorePageFaultM = '0; @@ -533,12 +568,6 @@ module pagetablewalker ( LEAF: begin // Keep physical address alive to prevent HADDR dropping to 0 //TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; - PageTableEntry = CurrentPTE; - PageType = (WalkerState == LEVEL3) ? 2'b11 : - ((WalkerState == LEVEL2) ? 2'b10 : - ((WalkerState == LEVEL1) ? 2'b01 : 2'b00)); - DTLBWriteM = DTLBMissMQ; - ITLBWriteF = ~DTLBMissMQ; // Prefer data over instructions end FAULT: begin // Keep physical address alive to prevent HADDR dropping to 0