From 872ff619e397b1fe63bbf1a4dca878d6642c63bb Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Thu, 29 Dec 2022 17:13:48 -0600
Subject: [PATCH] Fixed problems with changes to ram2p.

---
 pipelined/src/generic/mem/ram2p1r1wb.sv     |  2 +-
 pipelined/src/ifu/BTBPredictor.sv           | 14 +++++++-------
 pipelined/src/ifu/globalHistoryPredictor.sv | 14 +++++++-------
 pipelined/src/ifu/gsharePredictor.sv        | 14 +++++++-------
 pipelined/src/ifu/localHistoryPredictor.sv  | 14 +++++++-------
 pipelined/src/ifu/twoBitPredictor.sv        | 14 +++++++-------
 6 files changed, 36 insertions(+), 36 deletions(-)

diff --git a/pipelined/src/generic/mem/ram2p1r1wb.sv b/pipelined/src/generic/mem/ram2p1r1wb.sv
index 7ded3a20..dac1290f 100644
--- a/pipelined/src/generic/mem/ram2p1r1wb.sv
+++ b/pipelined/src/generic/mem/ram2p1r1wb.sv
@@ -63,7 +63,7 @@ module ram2p1r1wb
 
   logic [DEPTH-1:0]         ra1q, wa2q;
   logic                     wen2q;
-  logic [width-1:0]         wd2q;
+  logic [WIDTH-1:0]         wd2q;
 
   logic [WIDTH-1:0]         mem[2**DEPTH-1:0];
   logic [WIDTH-1:0]         bwe;
diff --git a/pipelined/src/ifu/BTBPredictor.sv b/pipelined/src/ifu/BTBPredictor.sv
index f03bbdd5..3c90497e 100644
--- a/pipelined/src/ifu/BTBPredictor.sv
+++ b/pipelined/src/ifu/BTBPredictor.sv
@@ -105,13 +105,13 @@ module BTBPredictor
   // *** optimize for byte write enables
   ram2p1r1wb #(Depth, `XLEN+5) memory(.clk(clk),
           .reset(reset),
-          .RA1(LookUpPCIndex),
-          .RD1({{InstrClass, TargetPC}}),
-          .REN1(~StallF),
-          .WA1(UpdatePCIndex),
-          .WD1({UpdateInstrClass, UpdateTarget}),
-          .WEN1(UpdateEN),
-          .BitWEN1({5'h1F, {`XLEN{1'b1}}})); // *** definitely not right.
+          .ra1(LookUpPCIndex),
+          .rd1({{InstrClass, TargetPC}}),
+          .ren1(~StallF),
+          .wa2(UpdatePCIndex),
+          .wd2({UpdateInstrClass, UpdateTarget}),
+          .wen2(UpdateEN),
+          .bwe2({5'h1F, {`XLEN{1'b1}}})); // *** definitely not right.
 
 
 endmodule
diff --git a/pipelined/src/ifu/globalHistoryPredictor.sv b/pipelined/src/ifu/globalHistoryPredictor.sv
index 6d06dc8c..29cb735d 100644
--- a/pipelined/src/ifu/globalHistoryPredictor.sv
+++ b/pipelined/src/ifu/globalHistoryPredictor.sv
@@ -116,12 +116,12 @@ module globalHistoryPredictor
   ram2p1r1wb #(k, 2) PHT(.clk(clk),
     .reset(reset),
     //.RA1(GHR[k-1:0]),
-    .RA1(GHRLookup),
-    .RD1(BPPredF),
-    .REN1(~StallF),
-    .WA1(PHTUpdateAdr),
-    .WD1(UpdateBPPredE),
-    .WEN1(PHTUpdateEN),
-    .BitWEN1(2'b11));
+    .ra1(GHRLookup),
+    .rd1(BPPredF),
+    .ren1(~StallF),
+    .wa2(PHTUpdateAdr),
+    .wd2(UpdateBPPredE),
+    .wen2(PHTUpdateEN),
+    .bwe2(2'b11));
 
 endmodule
diff --git a/pipelined/src/ifu/gsharePredictor.sv b/pipelined/src/ifu/gsharePredictor.sv
index ff111a3e..fa780194 100644
--- a/pipelined/src/ifu/gsharePredictor.sv
+++ b/pipelined/src/ifu/gsharePredictor.sv
@@ -113,12 +113,12 @@ module gsharePredictor
   ram2p1r1wb #(`BPRED_SIZE, 2) PHT(.clk(clk),
     .reset(reset),
     //.RA1(GHR[`BPRED_SIZE-1:0]),
-    .RA1(GHRLookup ^ PCNextF[`BPRED_SIZE:1]),
-    .RD1(BPPredF),
-    .REN1(~StallF),
-    .WA1(PHTUpdateAdr ^ PCE[`BPRED_SIZE:1]),
-    .WD1(UpdateBPPredE),
-    .WEN1(PHTUpdateEN),
-    .BitWEN1(2'b11));
+    .ra1(GHRLookup ^ PCNextF[`BPRED_SIZE:1]),
+    .rd1(BPPredF),
+    .ren1(~StallF),
+    .wa2(PHTUpdateAdr ^ PCE[`BPRED_SIZE:1]),
+    .wd2(UpdateBPPredE),
+    .wen2(PHTUpdateEN),
+    .bwe2(2'b11));
 
 endmodule // gsharePredictor
diff --git a/pipelined/src/ifu/localHistoryPredictor.sv b/pipelined/src/ifu/localHistoryPredictor.sv
index 97b2b6f5..02ad4cf1 100644
--- a/pipelined/src/ifu/localHistoryPredictor.sv
+++ b/pipelined/src/ifu/localHistoryPredictor.sv
@@ -86,13 +86,13 @@ module localHistoryPredictor
   // LHRE refers to the address that the past k branches points to in the exectution stage
   ram2p1r1wb #(k, 2) PHT(.clk(clk), 
     .reset(reset),
-    .RA1(ForwardLHRNext),
-    .RD1(PredictionMemory),
-    .REN1(~StallF),
-    .WA1(LHRFNext),
-    .WD1(UpdatePrediction),
-    .WEN1(UpdateEN),
-    .BitWEN1(2'b11));
+    .ra1(ForwardLHRNext),
+    .rd1(PredictionMemory),
+    .ren1(~StallF),
+    .wa2(LHRFNext),
+    .wd2(UpdatePrediction),
+    .wen2(UpdateEN),
+    .bwe2(2'b11));
 
 
   
diff --git a/pipelined/src/ifu/twoBitPredictor.sv b/pipelined/src/ifu/twoBitPredictor.sv
index 5ffb29d3..7459ea6a 100644
--- a/pipelined/src/ifu/twoBitPredictor.sv
+++ b/pipelined/src/ifu/twoBitPredictor.sv
@@ -62,13 +62,13 @@ module twoBitPredictor
 
   ram2p1r1wb #(Depth, 2) PHT(.clk(clk),
     .reset(reset),
-    .RA1(LookUpPCIndex),
-    .RD1(PredictionMemory),
-    .REN1(~StallF),
-    .WA1(UpdatePCIndex),
-    .WD1(UpdatePrediction),
-    .WEN1(UpdateEN),
-    .BitWEN1(2'b11));
+    .ra1(LookUpPCIndex),
+    .rd1(PredictionMemory),
+    .ren1(~StallF),
+    .wa2(UpdatePCIndex),
+    .wd2(UpdatePrediction),
+    .wen2(UpdateEN),
+    .bwe2(2'b11));
 
   // need to forward when updating to the same address as reading.
   // first we compare to see if the update and lookup addreses are the same