From 870c15c4f53cbba132b44c36d92df3aa87a46d62 Mon Sep 17 00:00:00 2001
From: David Harris <74973295+davidharrishmc@users.noreply.github.com>
Date: Thu, 20 Apr 2023 14:15:34 -0700
Subject: [PATCH] Update README.md

---
 README.md | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/README.md b/README.md
index ff76f72f..b73aecdb 100644
--- a/README.md
+++ b/README.md
@@ -1,12 +1,15 @@
 # core-v-wally
-Configurable RISC-V Processor
 
-Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, incluidng RV32/64, A, C, F, D, Q, M, and Zb* extensions, FENCE.I, and the various privileged modes and CSRs.  It is written in SystemVerilog.  It passes the RISC-V Arch Tests and boots Linux on an FPGA.
+Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, incluidng RV32/64, A, C, F, D, Q, M, and Zb* extensions, virtual memory, PMP, and the various privileged modes and CSRs. It provides optional caches, branch prediction, and standard RISC-V peripherals (CLINT, PLIC, UART, GPIO).   Wally is written in SystemVerilog.  It passes the RISC-V Arch Tests and boots Linux on an FPGA.  Configurations range from a minimal RV32E core to a fully featured RV64GC application processor.
 
 ![Wally block diagram](wallyriscvTopAll.png)
 
 Wally is described in an upcoming textbook, *RISC-V System-on-Chip Design*, by Harris, Stine, Thompson, and Harris.  Users should follow the setup instructions below.  A system administrator must install CAD tools using the directions further down.
 
+# Verification
+
+Wally is presently at Technology Readiness Level 4, passing the RISC-V compatibility test suite and custom tests, and booting Linux in simulation and on an FPGA.  See the [Test Plan](docs/testplan.md) for details.
+
 # New User Setup
 
 New users may wish to do the following setup to access the server via a GUI and use a text editor.