diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index 49c9a02c..72d2f216 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -97,6 +97,8 @@ module bpred (
   logic 		   BranchW, JumpW, ReturnW, CallW;
   logic 		   WrongBPReturnD;
   logic [`XLEN-1:0] BTAE;
+
+  
   
   // Part 1 branch direction prediction
   // look into the 2 port Sram model. something is wrong. 
@@ -161,7 +163,7 @@ module bpred (
   icpred #(`INSTR_CLASS_PRED) icpred(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
 		.PostSpillInstrRawF, .InstrD, .BranchD, .BranchE, .JumpD, .JumpE, .BranchM, .BranchW, .JumpM, .JumpW,
 		.CallD, .CallE, .CallM, .CallW, .ReturnD, .ReturnE, .ReturnM, .ReturnW, .BTBCallF, .BTBReturnF, .BTBJumpF,
-		.BTBBranchF, .BPCallF, .BPReturnF, .BPJumpF, .BPBranchF, .PredictionInstrClassWrongM, .WrongBPReturnD);
+		.BTBBranchF, .BPCallF, .BPReturnF, .BPJumpF, .BPBranchF, .PredictionInstrClassWrongM, .AnyWrongPredInstrClassE, .WrongBPReturnD);
 
   // Part 3 RAS
   RASPredictor RASPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv
index 31c3fed5..908288e2 100644
--- a/src/ifu/bpred/btb.sv
+++ b/src/ifu/bpred/btb.sv
@@ -97,7 +97,7 @@ module btb #(parameter Depth = 10 ) (
   // An optimization may be using a PC relative address.
   ram2p1r1wbe #(2**Depth, `XLEN+4) memory(
     .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredF),
-     .ce2(~StallW & ~FlushW), .wa2(PCMIndex), .wd2({InstrClassM, IEUAdrM}), .we2(UpdateEn), .bwe2('1));
+     .ce2(~StallW & ~FlushW), .wa2(PCMIndex), .wd2({InstrClassM, IEUAdrM}), .we2(BTBWrongM), .bwe2('1));
 
   assign UpdateEn = |InstrClassM | PredictionInstrClassWrongM;
 
diff --git a/src/ifu/bpred/icpred.sv b/src/ifu/bpred/icpred.sv
index f6b0f7d1..c37c3938 100644
--- a/src/ifu/bpred/icpred.sv
+++ b/src/ifu/bpred/icpred.sv
@@ -42,10 +42,10 @@ module icpred #(parameter INSTR_CLASS_PRED = 1)(
   output logic             ReturnD, ReturnE, ReturnM, ReturnW,
   input  logic             BTBCallF, BTBReturnF, BTBJumpF, BTBBranchF,
   output logic             BPCallF, BPReturnF, BPJumpF, BPBranchF,
-  output logic             PredictionInstrClassWrongM, WrongBPReturnD
+  output logic             PredictionInstrClassWrongM, WrongBPReturnD, AnyWrongPredInstrClassE
 );
 
-  logic 		   AnyWrongPredInstrClassD, AnyWrongPredInstrClassE;
+  logic 		   AnyWrongPredInstrClassD;
   logic 					BPBranchD, BPJumpD, BPReturnD, BPCallD;
 
   if (!INSTR_CLASS_PRED) begin : DirectClassDecode