From 86cc758354571190f2dcb34192cd00131cd02ab9 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Fri, 11 Mar 2022 18:09:22 -0600
Subject: [PATCH] cleanup of ram.sv

---
 pipelined/src/lsu/lsu.sv    | 3 +--
 pipelined/src/uncore/ram.sv | 8 ++------
 2 files changed, 3 insertions(+), 8 deletions(-)

diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index 1d0588b4..2e20b3a2 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -106,7 +106,7 @@ module lsu (
   logic [`XLEN-1:0]         LSUWriteDataM;
   logic [(`XLEN-1)/8:0]     ByteMaskM;
   
-  // *** TO DO: Burst mode, byte write enables to DTIM, cache, exeternal memory, remove subword write from uncore, 
+  // *** TO DO: Burst mode
 
   flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM);
   assign IEUAdrExtM = {2'b00, IEUAdrM}; 
@@ -187,7 +187,6 @@ module lsu (
   logic                SelUncachedAdr;
   assign IgnoreRequest = IgnoreRequestTLB | IgnoreRequestTrapM;
   
-  // *** change to allow TIM and BUS.  seaparate parameter for having bus (but have to have bus if have cache - check in testbench)
   if (`DMEM == `MEM_TIM) begin : dtim
     // *** directly instantiate RAM or ROM here.  Instantiate SRAM1P1RW.  
     // Merge SimpleRAM and SRAM1p1rw into one that is good for synthesis and RAM libraries and flops
diff --git a/pipelined/src/uncore/ram.sv b/pipelined/src/uncore/ram.sv
index 7eef08a7..e9b0af32 100644
--- a/pipelined/src/uncore/ram.sv
+++ b/pipelined/src/uncore/ram.sv
@@ -48,7 +48,6 @@ module ram #(parameter BASE=0, RANGE = 65535) (
   
   logic [`XLEN-1:0] RAM[BASE>>(1+`XLEN/32):(RANGE+BASE)>>1+(`XLEN/32)];
   logic [31:0] HWADDR, A;
-  logic [`XLEN-1:0] HREADRam0;
 
   logic        prevHREADYRam, risingHREADYRam;
   logic        initTrans;
@@ -157,7 +156,7 @@ module ram #(parameter BASE=0, RANGE = 65535) (
     HWADDR <= #1 A;
   if (`XLEN == 64)  begin:ramrw
     always_ff @(posedge HCLK) 
-      HREADRam0 <= #1 RAM[A[31:3]];
+      HREADRam <= #1 RAM[A[31:3]];
     for(index = 0; index < `XLEN/8; index++) begin
       always_ff @(posedge HCLK) begin
         if (memwrite & risingHREADYRam & ByteMaskM[index]) RAM[HWADDR[31:3]][8*(index+1)-1:8*index] <= #1 HWDATA[8*(index+1)-1:8*index];
@@ -165,7 +164,7 @@ module ram #(parameter BASE=0, RANGE = 65535) (
     end
   end else begin 
     always_ff @(posedge HCLK) 
-      HREADRam0 <= #1 RAM[A[31:2]];
+      HREADRam <= #1 RAM[A[31:2]];
     for(index = 0; index < `XLEN/8; index++) begin
       always_ff @(posedge HCLK) begin:ramrw
         if (memwrite & risingHREADYRam & ByteMaskM[index]) RAM[HWADDR[31:2]][8*(index+1)-1:8*index] <= #1 HWDATA[8*(index+1)-1:8*index];
@@ -174,8 +173,5 @@ module ram #(parameter BASE=0, RANGE = 65535) (
   end
   /* verilator lint_on WIDTH */
 
-  //assign HREADRam = HREADYRam ? HREADRam0 : `XLEN'bz;
-  // *** Ross Thompson: removed tristate as fpga synthesis removes.
-  assign HREADRam = HREADRam0;
 endmodule