From 868ddce5f2c560d615648bd3576de14c89e9197e Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 19 Jun 2021 08:58:32 -0500 Subject: [PATCH] Revert "Improved some names in icache." This reverts commit a57c63aa7b5e958c3aff046cf706bdca57408788. --- wally-pipelined/src/cache/ICacheCntrl.sv | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/wally-pipelined/src/cache/ICacheCntrl.sv b/wally-pipelined/src/cache/ICacheCntrl.sv index d73a85bc..9037748c 100644 --- a/wally-pipelined/src/cache/ICacheCntrl.sv +++ b/wally-pipelined/src/cache/ICacheCntrl.sv @@ -133,7 +133,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) ( logic [LOGWPL:0] FetchCount, NextFetchCount; - logic [`PA_BITS-1:0] PCPreFinalF, PCPSpillF; + logic [`PA_BITS-1:0] PCPreFinalF, PCPFinalF, PCSpillF; logic [`PA_BITS-1:OFFSETWIDTH] PCPTrunkF; @@ -156,11 +156,11 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) ( // on spill we want to get the first 2 bytes of the next cache block. // the spill only occurs if the PCPF mod BlockByteLength == -2. Therefore we can // simply add 2 to land on the next cache block. - assign PCPSpillF = PCPF + 2'b10; // *** modelsim does not allow the use of PA_BITS for literal width. + assign PCSpillF = PCPF + `XLEN'b10; // now we have to select between these three PCs assign PCPreFinalF = PCMux[0] | StallF ? PCPF : PCNextF; // *** don't like the stallf, but it is necessary - assign PCNextIndexF = PCMux[1] ? PCPSpillF : PCPreFinalF; + assign PCPFinalF = PCMux[1] ? PCSpillF : PCPreFinalF; // this mux needs to be delayed 1 cycle as it occurs 1 pipeline stage later. // *** read enable may not be necessary. @@ -170,7 +170,8 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) ( .d(PCMux), .q(PCMux_q)); - assign PCTagF = PCMux_q[1] ? PCPSpillF : PCPF; + assign PCTagF = PCMux_q[1] ? PCSpillF : PCPF; + assign PCNextIndexF = PCPFinalF; // truncate the offset from PCPF for memory address generation assign PCPTrunkF = PCTagF[`PA_BITS-1:OFFSETWIDTH]; @@ -394,7 +395,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) ( // we need to address on that number of bits so the PC is extended to the right by AHBByteLength with zeros. // fetch count is already aligned to AHBByteLength, but we need to extend back to the full address width with // more zeros after the addition. This will be the number of offset bits less the AHBByteLength. - logic [`PA_BITS-1:OFFSETWIDTH-LOGWPL] PCPTrunkExtF, InstrPAdrTrunkF ; + logic [`XLEN-1:OFFSETWIDTH-LOGWPL] PCPTrunkExtF, InstrPAdrTrunkF ; assign PCPTrunkExtF = {PCPTrunkF, {{LOGWPL}{1'b0}}}; // verilator lint_off WIDTH