From 861ef5e1cb13dec090872e0f6576418a25c49463 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 13 Jul 2021 09:32:02 -0400 Subject: [PATCH] Replaced .or with or_rows structural code in MMU read circuitry for synthesis. --- wally-pipelined/src/mmu/tlbcam.sv | 3 ++- wally-pipelined/src/mmu/tlbram.sv | 4 +++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/wally-pipelined/src/mmu/tlbcam.sv b/wally-pipelined/src/mmu/tlbcam.sv index e735afdc..5068972a 100644 --- a/wally-pipelined/src/mmu/tlbcam.sv +++ b/wally-pipelined/src/mmu/tlbcam.sv @@ -56,7 +56,8 @@ module tlbcam #(parameter TLB_ENTRIES = 8, .clk, .reset, .VPN, .SATP_ASID, .SV39Mode, .PTE_G(PTE_Gs), .PageTypeWriteVal, .TLBFlush, .WriteEnable(WriteEnables), .PageTypeRead, .Match(Matches)); assign CAMHit = |Matches & ~TLBFlush; - assign HitPageType = PageTypeRead.or; // applies OR to elements of the (TLB_ENTRIES x 2) array to get 2-bit result + or_rows #(TLB_ENTRIES,2) PageTypeOr(PageTypeRead, HitPageType); + //assign HitPageType = PageTypeRead.or; // applies OR to elements of the (TLB_ENTRIES x 2) array to get 2-bit result endmodule diff --git a/wally-pipelined/src/mmu/tlbram.sv b/wally-pipelined/src/mmu/tlbram.sv index 71d47c23..b79666a5 100644 --- a/wally-pipelined/src/mmu/tlbram.sv +++ b/wally-pipelined/src/mmu/tlbram.sv @@ -41,7 +41,9 @@ module tlbram #(parameter TLB_ENTRIES = 8) ( // RAM implemented with array of flops and AND/OR read logic tlbramline #(`PPN_BITS+10) tlblineram[TLB_ENTRIES-1:0](clk, reset, Matches, WriteEnables, PTE[`PPN_BITS+9:0], RamRead, PTE_Gs); - assign PageTableEntry = RamRead.or; // OR each column of RAM read to read PTE + //assign PageTableEntry = RamRead.or; // OR each column of RAM read to read PTE + or_rows #(TLB_ENTRIES, `PPN_BITS+10) PTEOr(RamRead, PageTableEntry); + // Rename the bits read from the TLB RAM assign PTEAccessBits = PageTableEntry[7:0]; assign PPN = PageTableEntry[`PPN_BITS+9:10];