From 8610ef204cca0ee0384e72f7d4422601ba27e547 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 15 Jul 2021 10:16:16 -0500 Subject: [PATCH] Renamed DCacheStall to LSUStall in hart and hazard. Added missing logic in lsu. --- wally-pipelined/src/cache/dcache.sv | 2 +- wally-pipelined/src/hazard/hazard.sv | 4 ++-- wally-pipelined/src/lsu/lsu.sv | 1 + wally-pipelined/src/wally/wallypipelinedhart.sv | 4 ++-- 4 files changed, 6 insertions(+), 5 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 6e5c95d2..6c3ae803 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -433,7 +433,7 @@ module dcache case (CurrState) STATE_READY: begin // TLB Miss - if(AnyCPUReqM & DTLBMissM) begin + if(AnyCPUReqM & DTLBMissM) begin NextState = STATE_PTW_READY; end // amo hit diff --git a/wally-pipelined/src/hazard/hazard.sv b/wally-pipelined/src/hazard/hazard.sv index 331fc326..e5480286 100644 --- a/wally-pipelined/src/hazard/hazard.sv +++ b/wally-pipelined/src/hazard/hazard.sv @@ -31,7 +31,7 @@ module hazard( // Detect hazards input logic BPPredWrongE, CSRWritePendingDEM, RetM, TrapM, input logic LoadStallD, StoreStallD, MulDivStallD, CSRRdStallD, - input logic DCacheStall, ICacheStallF, + input logic LSUStall, ICacheStallF, input logic FPUStallD, FStallD, input logic DivBusyE,FDivBusyE, // Stall & flush outputs @@ -59,7 +59,7 @@ module hazard( assign StallDCause = (LoadStallD | StoreStallD | MulDivStallD | CSRRdStallD | FPUStallD | FStallD) & ~(TrapM | RetM | BPPredWrongE); // stall in decode if instruction is a load/mul/csr dependent on previous assign StallECause = DivBusyE | FDivBusyE; assign StallMCause = 0; - assign StallWCause = DCacheStall | ICacheStallF; + assign StallWCause = LSUStall | ICacheStallF; assign StallF = StallFCause | StallD; assign StallD = StallDCause | StallE; diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index f8fa87a0..345e3514 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -152,6 +152,7 @@ module lsu logic CommittedMfromDCache; logic PendingInterruptMtoDCache; + logic FlushWtoDCache; pagetablewalker pagetablewalker( diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index e0337bc3..b8d7af57 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -126,7 +126,7 @@ module wallypipelinedhart // IMem stalls logic ICacheStallF; - logic DCacheStall; + logic LSUStall; @@ -233,7 +233,7 @@ module wallypipelinedhart .DTLBHitM(DTLBHitM), // not connected remove - .LSUStall(DCacheStall)); // change to DCacheStall + .LSUStall(LSUStall)); // change to LSUStall