From 850a2e9329696bfadd10d93d5ad343a8bc5bded2 Mon Sep 17 00:00:00 2001
From: bbracker <bbracker@hmc.edu>
Date: Fri, 5 Mar 2021 15:07:34 -0500
Subject: [PATCH] added a delay to sel signals

---
 wally-pipelined/src/uncore/uncore.sv | 22 ++++++++++------------
 1 file changed, 10 insertions(+), 12 deletions(-)

diff --git a/wally-pipelined/src/uncore/uncore.sv b/wally-pipelined/src/uncore/uncore.sv
index ae6899c4..c068616c 100644
--- a/wally-pipelined/src/uncore/uncore.sv
+++ b/wally-pipelined/src/uncore/uncore.sv
@@ -140,17 +140,15 @@ module uncore (
                             HSELUARTD);
 
 
-  // Synchronized Address Decoder (figure 4-2 in spec)
-  always_ff @(posedge HCLK) begin
-    HSELTimD   <= HSELTim;
-    HSELCLINTD <= HSELCLINT;
-    `ifdef GPIOBASE
-    HSELGPIOD  <= HSELGPIO;
-    `endif
-    HSELUARTD  <= HSELUART;
-    `ifdef BOOTTIMBASE
-    HSELBootTimD <= HSELBootTim;
-    `endif
-  end
+  // Address Decoder Delay (figure 4-2 in spec)
+  flopr #(1) hseltimreg(HCLK, ~HRESETn, HSELTim, HSELTimD);
+  flopr #(1) hselclintreg(HCLK, ~HRESETn, HSELCLINT, HSELCLINTD);
+  `ifdef GPIOBASE
+  flopr #(1) hselgpioreg(HCLK, ~HRESETn, HSELGPIO, HSELGPIOD);
+  `endif
+  flopr #(1) hseluartreg(HCLK, ~HRESETn, HSELUART, HSELUARTD);
+  `ifdef BOOTTIMBASE
+  flopr #(1) hselboottimreg(HCLK, ~HRESETn, HSELBootTim, HSELBootTimD);
+  `endif
 endmodule