From 8506f120e1fce554453e6f0de70c9c5b59d4fc4c Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 7 Jan 2023 05:46:22 -0800
Subject: [PATCH] Remove unused signals

---
 pipelined/src/ieu/controller.sv           | 2 +-
 pipelined/src/ieu/datapath.sv             | 1 -
 pipelined/src/ieu/ieu.sv                  | 1 -
 pipelined/src/ifu/ifu.sv                  | 3 ---
 pipelined/src/wally/wallypipelinedcore.sv | 2 +-
 5 files changed, 2 insertions(+), 7 deletions(-)

diff --git a/pipelined/src/ieu/controller.sv b/pipelined/src/ieu/controller.sv
index 24700c33..a082bd5f 100644
--- a/pipelined/src/ieu/controller.sv
+++ b/pipelined/src/ieu/controller.sv
@@ -103,7 +103,7 @@ module controller(
   logic        SubArithD;
   logic        subD, sraD, sltD, sltuD;
   logic        BranchTakenE;
-  logic        eqE, ltE, ltuE;
+  logic        eqE, ltE;
   logic        unused;
 	logic        BranchFlagE;
   logic        IEURegWriteE;
diff --git a/pipelined/src/ieu/datapath.sv b/pipelined/src/ieu/datapath.sv
index 7c05986d..44595343 100644
--- a/pipelined/src/ieu/datapath.sv
+++ b/pipelined/src/ieu/datapath.sv
@@ -62,7 +62,6 @@ module datapath (
   input  logic [2:0]       ResultSrcW,
   input logic [`XLEN-1:0]  FCvtIntResW,
   input logic [`XLEN-1:0] ReadDataW,
-  // input  logic [`XLEN-1:0] PCLinkW,
   input  logic [`XLEN-1:0] CSRReadValW, MDUResultW, 
   input logic [`XLEN-1:0] FPIntDivResultW,
    // Hazard Unit signals 
diff --git a/pipelined/src/ieu/ieu.sv b/pipelined/src/ieu/ieu.sv
index 1136452d..46a588ec 100644
--- a/pipelined/src/ieu/ieu.sv
+++ b/pipelined/src/ieu/ieu.sv
@@ -63,7 +63,6 @@ module ieu (
   input logic [`XLEN-1:0]  FCvtIntResW,
   output logic [4:0]       RdW,
   input logic [`XLEN-1:0] ReadDataW,
-  // input  logic [`XLEN-1:0] PCLinkW,
   output logic 		   InstrValidM, 
   // hazards
   input logic 		   StallD, StallE, StallM, StallW,
diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index b7fa6f55..dfdaf728 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -52,7 +52,6 @@ module ifu (
 	output logic [`XLEN-1:0] 	PCE,
 	output logic 				BPPredWrongE, 
 	// Mem
-	input logic 				RetM, TrapM, 
     output logic                CommittedF, 
 	input logic [`XLEN-1:0] 	UnalignedPCNextF,
     output logic [`XLEN-1:0]    PCNext2F,
@@ -248,11 +247,9 @@ module ifu (
                                  .s({SelIROM, ~CacheableF}), .y(InstrRawF[31:0]));
     end else begin : passthrough
       assign IFUHADDR = PCPF;
-      logic CaptureEn;
       logic [31:0]  FetchBuffer;
       logic [1:0] BusRW;
       assign BusRW = ~ITLBMissF & ~SelIROM ? IFURWF : '0;
-//      assign BusRW = IFURWF & ~{IgnoreRequest, IgnoreRequest} & ~{SelIROM, SelIROM};
       assign IFUHSIZE = 3'b010;
 
       ahbinterface #(0) ahbinterface(.HCLK(clk), .Flush(FlushD), .HRESETn(~reset), .HREADY(IFUHREADY), 
diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv
index 794a2742..8dc3c225 100644
--- a/pipelined/src/wally/wallypipelinedcore.sv
+++ b/pipelined/src/wally/wallypipelinedcore.sv
@@ -183,7 +183,7 @@ module wallypipelinedcore (
     .BPPredWrongE, 
   
     // Mem
-    .RetM, .TrapM, .CommittedF, .UnalignedPCNextF, .InvalidateICacheM, .CSRWriteFenceM,
+    .CommittedF, .UnalignedPCNextF, .InvalidateICacheM, .CSRWriteFenceM,
     .InstrD, .InstrM, .PCM, .InstrClassM, .DirPredictionWrongM,
     .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM,