From 799736632b5c24629762d668c97241411def5f6e Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 16 Feb 2022 17:21:05 +0000 Subject: [PATCH 1/2] Register file comments about reset --- pipelined/src/ieu/regfile.sv | 1 + 1 file changed, 1 insertion(+) diff --git a/pipelined/src/ieu/regfile.sv b/pipelined/src/ieu/regfile.sv index 2dfb0626..71ef621a 100644 --- a/pipelined/src/ieu/regfile.sv +++ b/pipelined/src/ieu/regfile.sv @@ -49,6 +49,7 @@ module regfile ( // register 0 hardwired to 0 // reset is intended for simulation only, not synthesis + // can logic be adjusted to not need resettable registers? always_ff @(negedge clk) // or posedge reset) // *** make this a preload in testbench rather than reset if (reset) for(i=1; i Date: Wed, 16 Feb 2022 17:40:13 +0000 Subject: [PATCH 2/2] Cleaned warning on HPTW default state --- pipelined/src/mmu/hptw.sv | 4 +++- pipelined/src/privileged/privdec.sv | 2 +- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/pipelined/src/mmu/hptw.sv b/pipelined/src/mmu/hptw.sv index 2bfad558..2700cf4e 100644 --- a/pipelined/src/mmu/hptw.sv +++ b/pipelined/src/mmu/hptw.sv @@ -151,6 +151,7 @@ module hptw // to decrease the latency of the HPTW. However, if the D$ is a cycle limiter, it's better to leave the // HPTW as shown below to keep the D$ setup time out of the critical path. // *** Is this really true. Talk with Ross. Seems like it's the next state logic on critical path instead. + // *** address TYPE(statetype) flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState); always_comb case (WalkerState) @@ -190,7 +191,8 @@ module hptw LEAF: NextWalkerState = IDLE; // updates TLB default: begin // synthesis translate_off - $error("Default state in HPTW should be unreachable; was %d", WalkerState); + if (WalkerState !== 'x) + $error("Default state in HPTW should be unreachable; was %d", WalkerState); // synthesis translate_on NextWalkerState = IDLE; // should never be reached end diff --git a/pipelined/src/privileged/privdec.sv b/pipelined/src/privileged/privdec.sv index 749f1387..25e929a2 100644 --- a/pipelined/src/privileged/privdec.sv +++ b/pipelined/src/privileged/privdec.sv @@ -49,7 +49,7 @@ module privdec ( assign ecallM = PrivilegedM & (InstrM[31:20] == 12'b000000000000); assign ebreakM = PrivilegedM & (InstrM[31:20] == 12'b000000000001); assign wfiM = PrivilegedM & (InstrM[31:20] == 12'b000100000101); - assign sfencevmaM = PrivilegedM & (InstrM[31:25] == 7'b0001001); + assign sfencevmaM = PrivilegedM & (InstrM[31:25] == 7'b0001001); // *** & (PrivilegedModeW == `M_MODE | ~STATUS_TVM); // *** does this work in U mode? assign IllegalPrivilegedInstrM = PrivilegedM & ~(sretM|mretM|ecallM|ebreakM|wfiM|sfencevmaM); assign IllegalInstrFaultM = (IllegalIEUInstrFaultM & IllegalFPUInstrM) | IllegalPrivilegedInstrM | IllegalCSRAccessM | TrappedSRETM; // *** generalize this for other instructions