From 81da8b8d2ab548ec321a721a9ed496eb61537377 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 13 Dec 2021 17:16:13 -0600
Subject: [PATCH] Formating changes to cache fsms.

---
 wally-pipelined/src/cache/dcachefsm.sv | 1310 ++++++++++++------------
 wally-pipelined/src/cache/icachefsm.sv |  246 ++---
 2 files changed, 778 insertions(+), 778 deletions(-)

diff --git a/wally-pipelined/src/cache/dcachefsm.sv b/wally-pipelined/src/cache/dcachefsm.sv
index cbfd2091..63e712f1 100644
--- a/wally-pipelined/src/cache/dcachefsm.sv
+++ b/wally-pipelined/src/cache/dcachefsm.sv
@@ -27,116 +27,116 @@
 
 module dcachefsm
   (input logic clk,
-   input logic 	      reset,
+   input logic 		  reset,
    // inputs from IEU
    input logic [1:0]  MemRWM,
    input logic [1:0]  AtomicM,
-   input logic 	      FlushDCacheM,
+   input logic 		  FlushDCacheM,
    // hazard inputs
-   input logic 	      ExceptionM,
-   input logic 	      PendingInterruptM,
-   input logic 	      StallWtoDCache,
+   input logic 		  ExceptionM,
+   input logic 		  PendingInterruptM,
+   input logic 		  StallWtoDCache,
    // mmu inputs
-   input logic 	      DTLBMissM,
-   input logic 	      ITLBMissF,
-   input logic 	      CacheableM,
-   input logic 	      DTLBWriteM,
-   input logic 	      ITLBWriteF,
-   input logic 	      WalkerInstrPageFaultF,
+   input logic 		  DTLBMissM,
+   input logic 		  ITLBMissF,
+   input logic 		  CacheableM,
+   input logic 		  DTLBWriteM,
+   input logic 		  ITLBWriteF,
+   input logic 		  WalkerInstrPageFaultF,
    // hptw inputs
-   input logic 	      SelPTW,
-   input logic 	      WalkerPageFaultM,
+   input logic 		  SelPTW,
+   input logic 		  WalkerPageFaultM,
    // Bus inputs
-   input logic 	      AHBAck, // from ahb
+   input logic 		  AHBAck, // from ahb
    // dcache internals
-   input logic 	      CacheHit,
-   input logic 	      FetchCountFlag,
-   input logic 	      VictimDirty,
-   input logic 	      FlushAdrFlag,
-   
+   input logic 		  CacheHit,
+   input logic 		  FetchCountFlag,
+   input logic 		  VictimDirty,
+   input logic 		  FlushAdrFlag,
+  
    // hazard outputs
-   output logic       DCacheStall,
-   output logic       CommittedM,
+   output logic 	  DCacheStall,
+   output logic 	  CommittedM,
    // counter outputs
-   output logic       DCacheMiss,
-   output logic       DCacheAccess,
+   output logic 	  DCacheMiss,
+   output logic 	  DCacheAccess,
    // hptw outputs
-   output logic       MemAfterIWalkDone,
+   output logic 	  MemAfterIWalkDone,
    // Bus outputs
-   output logic       AHBRead,
-   output logic       AHBWrite,
+   output logic 	  AHBRead,
+   output logic 	  AHBWrite,
 
    // dcache internals
    output logic [1:0] SelAdrM,
-   output logic       CntEn,
-   output logic       SetValid,
-   output logic       ClearValid,
-   output logic       SetDirty,
-   output logic       ClearDirty,
-   output logic       SRAMWordWriteEnableM,
-   output logic       SRAMBlockWriteEnableM,
-   output logic       CntReset,
-   output logic       SelUncached,
-   output logic       SelEvict,
-   output logic       LRUWriteEn,
-   output logic       SelFlush,
-   output logic       FlushAdrCntEn,
-   output logic       FlushWayCntEn, 
-   output logic       FlushAdrCntRst,
-   output logic       FlushWayCntRst,
-   output logic       VDWriteEnable
+   output logic 	  CntEn,
+   output logic 	  SetValid,
+   output logic 	  ClearValid,
+   output logic 	  SetDirty,
+   output logic 	  ClearDirty,
+   output logic 	  SRAMWordWriteEnableM,
+   output logic 	  SRAMBlockWriteEnableM,
+   output logic 	  CntReset,
+   output logic 	  SelUncached,
+   output logic 	  SelEvict,
+   output logic 	  LRUWriteEn,
+   output logic 	  SelFlush,
+   output logic 	  FlushAdrCntEn,
+   output logic 	  FlushWayCntEn, 
+   output logic 	  FlushAdrCntRst,
+   output logic 	  FlushWayCntRst,
+   output logic 	  VDWriteEnable
 
    );
   
-  logic 	     PreCntEn;
-  logic 	     AnyCPUReqM;
+  logic 			  PreCntEn;
+  logic 			  AnyCPUReqM;
   
-  typedef enum {STATE_READY,
+  typedef enum 		  {STATE_READY,
 
-		STATE_MISS_FETCH_WDV,
-		STATE_MISS_FETCH_DONE,
-		STATE_MISS_EVICT_DIRTY,
-		STATE_MISS_WRITE_CACHE_BLOCK,
-		STATE_MISS_READ_WORD,
-		STATE_MISS_READ_WORD_DELAY,
-		STATE_MISS_WRITE_WORD,
+					   STATE_MISS_FETCH_WDV,
+					   STATE_MISS_FETCH_DONE,
+					   STATE_MISS_EVICT_DIRTY,
+					   STATE_MISS_WRITE_CACHE_BLOCK,
+					   STATE_MISS_READ_WORD,
+					   STATE_MISS_READ_WORD_DELAY,
+					   STATE_MISS_WRITE_WORD,
 
-		STATE_PTW_READY,
-		STATE_PTW_READ_MISS_FETCH_WDV,
-		STATE_PTW_READ_MISS_FETCH_DONE,
-		STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK,
-		STATE_PTW_READ_MISS_EVICT_DIRTY,		
-		STATE_PTW_READ_MISS_READ_WORD,
-		STATE_PTW_READ_MISS_READ_WORD_DELAY,
-		STATE_PTW_ACCESS_AFTER_WALK,		
+					   STATE_PTW_READY,
+					   STATE_PTW_READ_MISS_FETCH_WDV,
+					   STATE_PTW_READ_MISS_FETCH_DONE,
+					   STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK,
+					   STATE_PTW_READ_MISS_EVICT_DIRTY,		
+					   STATE_PTW_READ_MISS_READ_WORD,
+					   STATE_PTW_READ_MISS_READ_WORD_DELAY,
+					   STATE_PTW_ACCESS_AFTER_WALK,		
 
-		STATE_UNCACHED_WRITE,
-		STATE_UNCACHED_WRITE_DONE,
-		STATE_UNCACHED_READ,
-		STATE_UNCACHED_READ_DONE,
+					   STATE_UNCACHED_WRITE,
+					   STATE_UNCACHED_WRITE_DONE,
+					   STATE_UNCACHED_READ,
+					   STATE_UNCACHED_READ_DONE,
 
-		STATE_PTW_FAULT_READY,
-		STATE_PTW_FAULT_CPU_BUSY,
-		STATE_PTW_FAULT_MISS_FETCH_WDV,
-		STATE_PTW_FAULT_MISS_FETCH_DONE,
-		STATE_PTW_FAULT_MISS_WRITE_CACHE_BLOCK,
-		STATE_PTW_FAULT_MISS_READ_WORD,
-		STATE_PTW_FAULT_MISS_READ_WORD_DELAY,
-		STATE_PTW_FAULT_MISS_WRITE_WORD,
-		STATE_PTW_FAULT_MISS_WRITE_WORD_DELAY,
-		STATE_PTW_FAULT_MISS_EVICT_DIRTY,
+					   STATE_PTW_FAULT_READY,
+					   STATE_PTW_FAULT_CPU_BUSY,
+					   STATE_PTW_FAULT_MISS_FETCH_WDV,
+					   STATE_PTW_FAULT_MISS_FETCH_DONE,
+					   STATE_PTW_FAULT_MISS_WRITE_CACHE_BLOCK,
+					   STATE_PTW_FAULT_MISS_READ_WORD,
+					   STATE_PTW_FAULT_MISS_READ_WORD_DELAY,
+					   STATE_PTW_FAULT_MISS_WRITE_WORD,
+					   STATE_PTW_FAULT_MISS_WRITE_WORD_DELAY,
+					   STATE_PTW_FAULT_MISS_EVICT_DIRTY,
 
-		STATE_PTW_FAULT_UNCACHED_WRITE,
-		STATE_PTW_FAULT_UNCACHED_WRITE_DONE,
-		STATE_PTW_FAULT_UNCACHED_READ,
-		STATE_PTW_FAULT_UNCACHED_READ_DONE,
+					   STATE_PTW_FAULT_UNCACHED_WRITE,
+					   STATE_PTW_FAULT_UNCACHED_WRITE_DONE,
+					   STATE_PTW_FAULT_UNCACHED_READ,
+					   STATE_PTW_FAULT_UNCACHED_READ_DONE,
 
-		STATE_CPU_BUSY,
-		STATE_CPU_BUSY_FINISH_AMO,
-		
-		STATE_FLUSH,
-		STATE_FLUSH_WRITE_BACK,
-		STATE_FLUSH_CLEAR_DIRTY} statetype;
+					   STATE_CPU_BUSY,
+					   STATE_CPU_BUSY_FINISH_AMO,
+  
+					   STATE_FLUSH,
+					   STATE_FLUSH_WRITE_BACK,
+					   STATE_FLUSH_CLEAR_DIRTY} statetype;
 
   (* mark_debug = "true" *) statetype CurrState, NextState;
 
@@ -181,118 +181,118 @@ module dcachefsm
     case (CurrState)
       STATE_READY: begin
 
-	CntReset = 1'b0;
-	DCacheStall = 1'b0;
-	AHBRead = 1'b0;	  
-	AHBWrite = 1'b0;
-	SelAdrM = 2'b00;
-	SRAMWordWriteEnableM = 1'b0;
-	SetDirty = 1'b0;
-	LRUWriteEn = 1'b0;
-	CommittedM = 1'b0;
+		CntReset = 1'b0;
+		DCacheStall = 1'b0;
+		AHBRead = 1'b0;	  
+		AHBWrite = 1'b0;
+		SelAdrM = 2'b00;
+		SRAMWordWriteEnableM = 1'b0;
+		SetDirty = 1'b0;
+		LRUWriteEn = 1'b0;
+		CommittedM = 1'b0;
 
 
-	// TLB Miss	
-	if(((AnyCPUReqM & DTLBMissM) | ITLBMissF) & ~(ExceptionM | PendingInterruptM)) begin
-	  // the LSU arbiter has not yet selected the PTW.
-	  // The CPU needs to be stalled until that happens.
-	  // If we set DCacheStall for 1 cycle before going to
-	  // PTW ready the CPU will stall.
-	  // The page table walker asserts it's control 1 cycle
-	  // after the TLBs miss.
-	  CommittedM = 1'b1;
-	  DCacheStall = 1'b1;
-	  NextState = STATE_PTW_READY;
-	end
+		// TLB Miss	
+		if(((AnyCPUReqM & DTLBMissM) | ITLBMissF) & ~(ExceptionM | PendingInterruptM)) begin
+		  // the LSU arbiter has not yet selected the PTW.
+		  // The CPU needs to be stalled until that happens.
+		  // If we set DCacheStall for 1 cycle before going to
+		  // PTW ready the CPU will stall.
+		  // The page table walker asserts it's control 1 cycle
+		  // after the TLBs miss.
+		  CommittedM = 1'b1;
+		  DCacheStall = 1'b1;
+		  NextState = STATE_PTW_READY;
+		end
 
-	// Flush dcache to next level of memory
-	else if(FlushDCacheM  & ~(ExceptionM | PendingInterruptM)) begin
-	  NextState = STATE_FLUSH;
-	  DCacheStall = 1'b1;
-	  SelAdrM = 2'b11;
-	  FlushAdrCntRst = 1'b1;
-	  FlushWayCntRst = 1'b1;	
-	end
-	
-	// amo hit
-	else if(AtomicM[1] & (&MemRWM) & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
-	  SelAdrM = 2'b10;
-	  DCacheStall = 1'b0;
-	  
-	  if(StallWtoDCache) begin 
-	    NextState = STATE_CPU_BUSY_FINISH_AMO;
-	    SelAdrM = 2'b10;
-	  end
-	  else begin
-	    SRAMWordWriteEnableM = 1'b1;
-	    SetDirty = 1'b1;
-	    LRUWriteEn = 1'b1;
-	    NextState = STATE_READY;
-	  end
-	end
-	// read hit valid cached
-	else if(MemRWM[1] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
-	  DCacheStall = 1'b0;
-	  LRUWriteEn = 1'b1;
-	  
-	  if(StallWtoDCache) begin
-	    NextState = STATE_CPU_BUSY;
+		// Flush dcache to next level of memory
+		else if(FlushDCacheM  & ~(ExceptionM | PendingInterruptM)) begin
+		  NextState = STATE_FLUSH;
+		  DCacheStall = 1'b1;
+		  SelAdrM = 2'b11;
+		  FlushAdrCntRst = 1'b1;
+		  FlushWayCntRst = 1'b1;	
+		end
+		
+		// amo hit
+		else if(AtomicM[1] & (&MemRWM) & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
+		  SelAdrM = 2'b10;
+		  DCacheStall = 1'b0;
+		  
+		  if(StallWtoDCache) begin 
+			NextState = STATE_CPU_BUSY_FINISH_AMO;
+			SelAdrM = 2'b10;
+		  end
+		  else begin
+			SRAMWordWriteEnableM = 1'b1;
+			SetDirty = 1'b1;
+			LRUWriteEn = 1'b1;
+			NextState = STATE_READY;
+		  end
+		end
+		// read hit valid cached
+		else if(MemRWM[1] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
+		  DCacheStall = 1'b0;
+		  LRUWriteEn = 1'b1;
+		  
+		  if(StallWtoDCache) begin
+			NextState = STATE_CPU_BUSY;
             SelAdrM = 2'b10;
-	  end
-	  else begin
-	    NextState = STATE_READY;
-	    end
-	end
-	// write hit valid cached
-	else if (MemRWM[0] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
-	  SelAdrM = 2'b10;
-	  DCacheStall = 1'b0;
-	  SRAMWordWriteEnableM = 1'b1;
-	  SetDirty = 1'b1;
-	  LRUWriteEn = 1'b1;
-	  
-	  if(StallWtoDCache) begin 
-	    NextState = STATE_CPU_BUSY;
-	    SelAdrM = 2'b10;
-	  end
-	  else begin
-	    NextState = STATE_READY;
-	  end
-	end
-	// read or write miss valid cached
-	else if((|MemRWM) & CacheableM & ~(ExceptionM | PendingInterruptM) & ~CacheHit & ~DTLBMissM) begin
-	  NextState = STATE_MISS_FETCH_WDV;
-	  CntReset = 1'b1;
-	  DCacheStall = 1'b1;
-	end
-	// uncached write
-	else if(MemRWM[0] & ~CacheableM & ~(ExceptionM | PendingInterruptM) & ~DTLBMissM) begin
-	  NextState = STATE_UNCACHED_WRITE;
-	  CntReset = 1'b1;
-	  DCacheStall = 1'b1;
-	  AHBWrite = 1'b1;
-	end
-	// uncached read
-	else if(MemRWM[1] & ~CacheableM & ~(ExceptionM | PendingInterruptM) & ~DTLBMissM) begin
-	  NextState = STATE_UNCACHED_READ;
-	  CntReset = 1'b1;
-	  DCacheStall = 1'b1;
-	  AHBRead = 1'b1;	  
-	end
-	// fault
-	else if(AnyCPUReqM & (ExceptionM | PendingInterruptM) & ~DTLBMissM) begin
-	  NextState = STATE_READY;
-	end
-	else NextState = STATE_READY;
+		  end
+		  else begin
+			NextState = STATE_READY;
+	      end
+		end
+		// write hit valid cached
+		else if (MemRWM[0] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
+		  SelAdrM = 2'b10;
+		  DCacheStall = 1'b0;
+		  SRAMWordWriteEnableM = 1'b1;
+		  SetDirty = 1'b1;
+		  LRUWriteEn = 1'b1;
+		  
+		  if(StallWtoDCache) begin 
+			NextState = STATE_CPU_BUSY;
+			SelAdrM = 2'b10;
+		  end
+		  else begin
+			NextState = STATE_READY;
+		  end
+		end
+		// read or write miss valid cached
+		else if((|MemRWM) & CacheableM & ~(ExceptionM | PendingInterruptM) & ~CacheHit & ~DTLBMissM) begin
+		  NextState = STATE_MISS_FETCH_WDV;
+		  CntReset = 1'b1;
+		  DCacheStall = 1'b1;
+		end
+		// uncached write
+		else if(MemRWM[0] & ~CacheableM & ~(ExceptionM | PendingInterruptM) & ~DTLBMissM) begin
+		  NextState = STATE_UNCACHED_WRITE;
+		  CntReset = 1'b1;
+		  DCacheStall = 1'b1;
+		  AHBWrite = 1'b1;
+		end
+		// uncached read
+		else if(MemRWM[1] & ~CacheableM & ~(ExceptionM | PendingInterruptM) & ~DTLBMissM) begin
+		  NextState = STATE_UNCACHED_READ;
+		  CntReset = 1'b1;
+		  DCacheStall = 1'b1;
+		  AHBRead = 1'b1;	  
+		end
+		// fault
+		else if(AnyCPUReqM & (ExceptionM | PendingInterruptM) & ~DTLBMissM) begin
+		  NextState = STATE_READY;
+		end
+		else NextState = STATE_READY;
       end
       
       STATE_MISS_FETCH_WDV: begin
-	DCacheStall = 1'b1;
+		DCacheStall = 1'b1;
         PreCntEn = 1'b1;
-	AHBRead = 1'b1;
-	SelAdrM = 2'b10;
-	CommittedM = 1'b1;
-	
+		AHBRead = 1'b1;
+		SelAdrM = 2'b10;
+		CommittedM = 1'b1;
+		
         if (FetchCountFlag & AHBAck) begin
           NextState = STATE_MISS_FETCH_DONE;
         end else begin
@@ -301,170 +301,170 @@ module dcachefsm
       end
 
       STATE_MISS_FETCH_DONE: begin
-	DCacheStall = 1'b1;
-	SelAdrM = 2'b10;
+		DCacheStall = 1'b1;
+		SelAdrM = 2'b10;
         CntReset = 1'b1;
-	CommittedM = 1'b1;
-	if(VictimDirty) begin
-	  NextState = STATE_MISS_EVICT_DIRTY;
-	end else begin
-	  NextState = STATE_MISS_WRITE_CACHE_BLOCK;
-	end
+		CommittedM = 1'b1;
+		if(VictimDirty) begin
+		  NextState = STATE_MISS_EVICT_DIRTY;
+		end else begin
+		  NextState = STATE_MISS_WRITE_CACHE_BLOCK;
+		end
       end
 
       STATE_MISS_WRITE_CACHE_BLOCK: begin
-	SRAMBlockWriteEnableM = 1'b1;
-	DCacheStall = 1'b1;
-	NextState = STATE_MISS_READ_WORD;
-	SelAdrM = 2'b10;
-	SetValid = 1'b1;
-	ClearDirty = 1'b1;
-	CommittedM = 1'b1;
-	//LRUWriteEn = 1'b1;  // DO not update LRU on SRAM fetch update.  Wait for subsequent read/write
+		SRAMBlockWriteEnableM = 1'b1;
+		DCacheStall = 1'b1;
+		NextState = STATE_MISS_READ_WORD;
+		SelAdrM = 2'b10;
+		SetValid = 1'b1;
+		ClearDirty = 1'b1;
+		CommittedM = 1'b1;
+		//LRUWriteEn = 1'b1;  // DO not update LRU on SRAM fetch update.  Wait for subsequent read/write
       end
 
       STATE_MISS_READ_WORD: begin
-	SelAdrM = 2'b10;
-	DCacheStall = 1'b1;
-	CommittedM = 1'b1;
-	if (MemRWM[0] & ~AtomicM[1]) begin // handles stores and amo write.
-	  NextState = STATE_MISS_WRITE_WORD;
-	end else begin
-	  NextState = STATE_MISS_READ_WORD_DELAY;
-	  // delay state is required as the read signal MemRWM[1] is still high when we
-	  // return to the ready state because the cache is stalling the cpu.
-	end
+		SelAdrM = 2'b10;
+		DCacheStall = 1'b1;
+		CommittedM = 1'b1;
+		if (MemRWM[0] & ~AtomicM[1]) begin // handles stores and amo write.
+		  NextState = STATE_MISS_WRITE_WORD;
+		end else begin
+		  NextState = STATE_MISS_READ_WORD_DELAY;
+		  // delay state is required as the read signal MemRWM[1] is still high when we
+		  // return to the ready state because the cache is stalling the cpu.
+		end
       end
 
       STATE_MISS_READ_WORD_DELAY: begin
-	//SelAdrM = 2'b10;
-	CommittedM = 1'b1;
-	SRAMWordWriteEnableM = 1'b0;
-	SetDirty = 1'b0;
-	LRUWriteEn = 1'b0;
-	if(&MemRWM & AtomicM[1]) begin // amo write
-	  SelAdrM = 2'b10;
-	  if(StallWtoDCache) begin 
-	    NextState = STATE_CPU_BUSY_FINISH_AMO;
-	  end
-	  else begin
-	    SRAMWordWriteEnableM = 1'b1;
-	    SetDirty = 1'b1;
-	    LRUWriteEn = 1'b1;
-	    NextState = STATE_READY;
-	  end
-	end else begin
-	  LRUWriteEn = 1'b1;
-	  if(StallWtoDCache) begin 
-	    NextState = STATE_CPU_BUSY;
-	    SelAdrM = 2'b10;
-	  end
-	  else begin
-	    NextState = STATE_READY;
-	  end
-	end
+		//SelAdrM = 2'b10;
+		CommittedM = 1'b1;
+		SRAMWordWriteEnableM = 1'b0;
+		SetDirty = 1'b0;
+		LRUWriteEn = 1'b0;
+		if(&MemRWM & AtomicM[1]) begin // amo write
+		  SelAdrM = 2'b10;
+		  if(StallWtoDCache) begin 
+			NextState = STATE_CPU_BUSY_FINISH_AMO;
+		  end
+		  else begin
+			SRAMWordWriteEnableM = 1'b1;
+			SetDirty = 1'b1;
+			LRUWriteEn = 1'b1;
+			NextState = STATE_READY;
+		  end
+		end else begin
+		  LRUWriteEn = 1'b1;
+		  if(StallWtoDCache) begin 
+			NextState = STATE_CPU_BUSY;
+			SelAdrM = 2'b10;
+		  end
+		  else begin
+			NextState = STATE_READY;
+		  end
+		end
       end
 
       STATE_MISS_WRITE_WORD: begin
-	SRAMWordWriteEnableM = 1'b1;
-	SetDirty = 1'b1;
-	SelAdrM = 2'b10;
-	CommittedM = 1'b1;
-	LRUWriteEn = 1'b1;
-	if(StallWtoDCache) begin 
-	  NextState = STATE_CPU_BUSY;
-	  SelAdrM = 2'b10;
-	end
-	else begin
-	  NextState = STATE_READY;
-	end
+		SRAMWordWriteEnableM = 1'b1;
+		SetDirty = 1'b1;
+		SelAdrM = 2'b10;
+		CommittedM = 1'b1;
+		LRUWriteEn = 1'b1;
+		if(StallWtoDCache) begin 
+		  NextState = STATE_CPU_BUSY;
+		  SelAdrM = 2'b10;
+		end
+		else begin
+		  NextState = STATE_READY;
+		end
       end
 
       STATE_MISS_EVICT_DIRTY: begin
-	DCacheStall = 1'b1;
+		DCacheStall = 1'b1;
         PreCntEn = 1'b1;
-	AHBWrite = 1'b1;
-	SelAdrM = 2'b10;
-	CommittedM = 1'b1;
-	SelEvict = 1'b1;
-	if(FetchCountFlag & AHBAck) begin
-	  NextState = STATE_MISS_WRITE_CACHE_BLOCK;
-	end else begin
-	  NextState = STATE_MISS_EVICT_DIRTY;
-	end	  
+		AHBWrite = 1'b1;
+		SelAdrM = 2'b10;
+		CommittedM = 1'b1;
+		SelEvict = 1'b1;
+		if(FetchCountFlag & AHBAck) begin
+		  NextState = STATE_MISS_WRITE_CACHE_BLOCK;
+		end else begin
+		  NextState = STATE_MISS_EVICT_DIRTY;
+		end	  
       end
 
       STATE_PTW_READY: begin
-	// now all output connect to PTW instead of CPU.
-	CommittedM = 1'b1;
-	SelAdrM = 2'b00;
-	DCacheStall = 1'b0;
-	LRUWriteEn = 1'b0;
-	CntReset = 1'b0;
+		// now all output connect to PTW instead of CPU.
+		CommittedM = 1'b1;
+		SelAdrM = 2'b00;
+		DCacheStall = 1'b0;
+		LRUWriteEn = 1'b0;
+		CntReset = 1'b0;
 
-	// In this branch we remove stall and go back to ready.  There is no request for memory from the
-	// datapath or the walker had a fault.
-	// types 3b, 4a, 4b, and 7c.
-	if ((DTLBMissM & WalkerPageFaultM) | // 3b
-	    (ITLBMissF & (WalkerInstrPageFaultF | ITLBWriteF) & ~AnyCPUReqM & ~DTLBMissM) | // 4a and 4b
-	    (DTLBMissM & ITLBMissF & WalkerPageFaultM)) begin // 7c
-	  NextState = STATE_READY;
-	  DCacheStall = 1'b0;
-	end
-	// in this branch we go back to ready, but there is a memory operation from
-	// the datapath so we MUST stall and replay the operation.
-	// types 3a and 5a
-	else if ((DTLBMissM & DTLBWriteM) |  // 3a
-		 (ITLBMissF & ITLBWriteF & AnyCPUReqM)) begin // 5a
-	  NextState = STATE_READY;
-	  DCacheStall = 1'b1;
-	  SelAdrM = 2'b01;
-	end
+		// In this branch we remove stall and go back to ready.  There is no request for memory from the
+		// datapath or the walker had a fault.
+		// types 3b, 4a, 4b, and 7c.
+		if ((DTLBMissM & WalkerPageFaultM) | // 3b or 7c (can have either itlb miss or not)
+			(ITLBMissF & (WalkerInstrPageFaultF | ITLBWriteF) & ~AnyCPUReqM & ~DTLBMissM) | // 4a and 4b
+			(DTLBMissM & ITLBMissF & WalkerPageFaultM)) begin // 7c  *** BUG redundant with first condiction.
+		  NextState = STATE_READY;
+		  DCacheStall = 1'b0;
+		end
+		// in this branch we go back to ready, but there is a memory operation from
+		// the datapath so we MUST stall and replay the operation.
+		// types 3a and 5a
+		else if ((DTLBMissM & DTLBWriteM) |  // 3a
+				 (ITLBMissF & ITLBWriteF & AnyCPUReqM)) begin // 5a
+		  NextState = STATE_READY;
+		  DCacheStall = 1'b1;
+		  SelAdrM = 2'b01;
+		end
 
-	// like 5a we want to stall and go to the ready state, but we also have to save
-	// the WalkerInstrPageFaultF so it is held until the end of the memory operation
-	// from the datapath.
-	// types 5b
-	else if (ITLBMissF & WalkerInstrPageFaultF & AnyCPUReqM) begin // 5b
-	  NextState = STATE_PTW_FAULT_READY;
-	  DCacheStall = 1'b1;
-	  SelAdrM = 2'b01;
-	end
+		// like 5a we want to stall and go to the ready state, but we also have to save
+		// the WalkerInstrPageFaultF so it is held until the end of the memory operation
+		// from the datapath.
+		// types 5b
+		else if (ITLBMissF & WalkerInstrPageFaultF & AnyCPUReqM) begin // 5b
+		  NextState = STATE_PTW_FAULT_READY;
+		  DCacheStall = 1'b1;
+		  SelAdrM = 2'b01;
+		end
 
-	// in this branch we stay in ptw_ready because we are doing an itlb walk
-	// after a dtlb walk.
-	// types 7a and 7b.
-	else if (DTLBMissM & DTLBWriteM & ITLBMissF)begin
-	  NextState = STATE_PTW_READY;
-	  DCacheStall = 1'b0;
-	  
-	// read hit valid cached
-	end else if(MemRWM[1] & CacheableM & ~ExceptionM & CacheHit) begin
-	  NextState = STATE_PTW_READY;
-	  DCacheStall = 1'b0;
-	  LRUWriteEn = 1'b1;
-	end
+		// in this branch we stay in ptw_ready because we are doing an itlb walk
+		// after a dtlb walk.
+		// types 7a and 7b.
+		else if (DTLBMissM & DTLBWriteM & ITLBMissF)begin
+		  NextState = STATE_PTW_READY;
+		  DCacheStall = 1'b0;
+		  
+		  // read hit valid cached
+		end else if(MemRWM[1] & CacheableM & ~ExceptionM & CacheHit) begin
+		  NextState = STATE_PTW_READY;
+		  DCacheStall = 1'b0;
+		  LRUWriteEn = 1'b1;
+		end
 
-	// read miss valid cached
-	else if(SelPTW & MemRWM[1] & CacheableM & ~ExceptionM & ~CacheHit) begin
-	  NextState = STATE_PTW_READ_MISS_FETCH_WDV;
-	  CntReset = 1'b1;
-	  DCacheStall = 1'b1;
-	end
+		// read miss valid cached
+		else if(SelPTW & MemRWM[1] & CacheableM & ~ExceptionM & ~CacheHit) begin
+		  NextState = STATE_PTW_READ_MISS_FETCH_WDV;
+		  CntReset = 1'b1;
+		  DCacheStall = 1'b1;
+		end
 
-	else begin
-	  NextState = STATE_PTW_READY;
-	  DCacheStall = 1'b0;
-	end
+		else begin
+		  NextState = STATE_PTW_READY;
+		  DCacheStall = 1'b0;
+		end
       end
 
       STATE_PTW_READ_MISS_FETCH_WDV: begin
-	DCacheStall = 1'b1;
+		DCacheStall = 1'b1;
         PreCntEn = 1'b1;
-	AHBRead = 1'b1;
-	SelAdrM = 2'b10;
-	CommittedM = 1'b1;
-	
+		AHBRead = 1'b1;
+		SelAdrM = 2'b10;
+		CommittedM = 1'b1;
+		
         if(FetchCountFlag & AHBAck) begin
           NextState = STATE_PTW_READ_MISS_FETCH_DONE;
         end else begin
@@ -473,238 +473,238 @@ module dcachefsm
       end
 
       STATE_PTW_READ_MISS_FETCH_DONE: begin
-	DCacheStall = 1'b1;
-	SelAdrM = 2'b10;
+		DCacheStall = 1'b1;
+		SelAdrM = 2'b10;
         CntReset = 1'b1;
-	CommittedM = 1'b1;
+		CommittedM = 1'b1;
         CntReset = 1'b1;
-	if(VictimDirty) begin
-	  NextState = STATE_PTW_READ_MISS_EVICT_DIRTY;
-	end else begin
-	  NextState = STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK;
-	end
+		if(VictimDirty) begin
+		  NextState = STATE_PTW_READ_MISS_EVICT_DIRTY;
+		end else begin
+		  NextState = STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK;
+		end
       end
 
       STATE_PTW_READ_MISS_EVICT_DIRTY: begin
-	DCacheStall = 1'b1;
+		DCacheStall = 1'b1;
         PreCntEn = 1'b1;
-	AHBWrite = 1'b1;
-	SelAdrM = 2'b10;
-	CommittedM = 1'b1;
-	SelEvict = 1'b1;
-	if(FetchCountFlag & AHBAck) begin
-	  NextState = STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK;
-	end else begin
-	  NextState = STATE_PTW_READ_MISS_EVICT_DIRTY;
-	end	  
+		AHBWrite = 1'b1;
+		SelAdrM = 2'b10;
+		CommittedM = 1'b1;
+		SelEvict = 1'b1;
+		if(FetchCountFlag & AHBAck) begin
+		  NextState = STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK;
+		end else begin
+		  NextState = STATE_PTW_READ_MISS_EVICT_DIRTY;
+		end	  
       end
       
 
       STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK: begin
-	SRAMBlockWriteEnableM = 1'b1;
-	DCacheStall = 1'b1;
-	NextState = STATE_PTW_READ_MISS_READ_WORD;
-	SelAdrM = 2'b10;
-	SetValid = 1'b1;
-	ClearDirty = 1'b1;
-	CommittedM = 1'b1;
-	//LRUWriteEn = 1'b1;
+		SRAMBlockWriteEnableM = 1'b1;
+		DCacheStall = 1'b1;
+		NextState = STATE_PTW_READ_MISS_READ_WORD;
+		SelAdrM = 2'b10;
+		SetValid = 1'b1;
+		ClearDirty = 1'b1;
+		CommittedM = 1'b1;
+		//LRUWriteEn = 1'b1;
       end
 
       STATE_PTW_READ_MISS_READ_WORD: begin
-	SelAdrM = 2'b10;
-	DCacheStall = 1'b1;
-	CommittedM = 1'b1;
-	NextState = STATE_PTW_READ_MISS_READ_WORD_DELAY;
+		SelAdrM = 2'b10;
+		DCacheStall = 1'b1;
+		CommittedM = 1'b1;
+		NextState = STATE_PTW_READ_MISS_READ_WORD_DELAY;
       end
 
       STATE_PTW_READ_MISS_READ_WORD_DELAY: begin
-	SelAdrM = 2'b10;
-	NextState = STATE_PTW_READY;
-	CommittedM = 1'b1;
+		SelAdrM = 2'b10;
+		NextState = STATE_PTW_READY;
+		CommittedM = 1'b1;
       end
       
       STATE_PTW_ACCESS_AFTER_WALK: begin
-	DCacheStall = 1'b1;
-	SelAdrM = 2'b10;
-	CommittedM = 1'b1;
-	LRUWriteEn = 1'b1;
-	NextState = STATE_READY;
+		DCacheStall = 1'b1;
+		SelAdrM = 2'b10;
+		CommittedM = 1'b1;
+		LRUWriteEn = 1'b1;
+		NextState = STATE_READY;
       end
       
       STATE_CPU_BUSY: begin
-	CommittedM = 1'b1;
-	SelAdrM = 2'b00;
-	if(StallWtoDCache) begin
-	  NextState = STATE_CPU_BUSY;
-	  SelAdrM = 2'b10;
-	end
-	else begin
-	  NextState = STATE_READY;
-	end
+		CommittedM = 1'b1;
+		SelAdrM = 2'b00;
+		if(StallWtoDCache) begin
+		  NextState = STATE_CPU_BUSY;
+		  SelAdrM = 2'b10;
+		end
+		else begin
+		  NextState = STATE_READY;
+		end
       end
 
       STATE_CPU_BUSY_FINISH_AMO: begin
-	CommittedM = 1'b1;
-	SelAdrM = 2'b10;
-	SRAMWordWriteEnableM = 1'b0;
-	SetDirty = 1'b0;
-	LRUWriteEn = 1'b0;
-	if(StallWtoDCache) begin
-	  NextState = STATE_CPU_BUSY_FINISH_AMO;
-	end
-	else begin
-	  SRAMWordWriteEnableM = 1'b1;
-	  SetDirty = 1'b1;
-	  LRUWriteEn = 1'b1;
-	  NextState = STATE_READY;
-	end
+		CommittedM = 1'b1;
+		SelAdrM = 2'b10;
+		SRAMWordWriteEnableM = 1'b0;
+		SetDirty = 1'b0;
+		LRUWriteEn = 1'b0;
+		if(StallWtoDCache) begin
+		  NextState = STATE_CPU_BUSY_FINISH_AMO;
+		end
+		else begin
+		  SRAMWordWriteEnableM = 1'b1;
+		  SetDirty = 1'b1;
+		  LRUWriteEn = 1'b1;
+		  NextState = STATE_READY;
+		end
       end
 
       STATE_UNCACHED_WRITE : begin
-	DCacheStall = 1'b1;	
-	AHBWrite = 1'b1;
-	CommittedM = 1'b1;
-	if(AHBAck) begin
-	  NextState = STATE_UNCACHED_WRITE_DONE;
-	end else begin
-	  NextState = STATE_UNCACHED_WRITE;
-	end
+		DCacheStall = 1'b1;	
+		AHBWrite = 1'b1;
+		CommittedM = 1'b1;
+		if(AHBAck) begin
+		  NextState = STATE_UNCACHED_WRITE_DONE;
+		end else begin
+		  NextState = STATE_UNCACHED_WRITE;
+		end
       end
 
       STATE_UNCACHED_READ: begin
-	DCacheStall = 1'b1;	
-	AHBRead = 1'b1;
-	CommittedM = 1'b1;
-	if(AHBAck) begin
-	  NextState = STATE_UNCACHED_READ_DONE;
-	end else begin
-	  NextState = STATE_UNCACHED_READ;
-	end
+		DCacheStall = 1'b1;	
+		AHBRead = 1'b1;
+		CommittedM = 1'b1;
+		if(AHBAck) begin
+		  NextState = STATE_UNCACHED_READ_DONE;
+		end else begin
+		  NextState = STATE_UNCACHED_READ;
+		end
       end
       
       STATE_UNCACHED_WRITE_DONE: begin
-	CommittedM = 1'b1;
-	SelAdrM = 2'b00;
-	if(StallWtoDCache) begin
-	  NextState = STATE_CPU_BUSY;
-	  SelAdrM = 2'b10;
-	end
-	else begin
-	  NextState = STATE_READY;
-	end
+		CommittedM = 1'b1;
+		SelAdrM = 2'b00;
+		if(StallWtoDCache) begin
+		  NextState = STATE_CPU_BUSY;
+		  SelAdrM = 2'b10;
+		end
+		else begin
+		  NextState = STATE_READY;
+		end
       end
 
       STATE_UNCACHED_READ_DONE: begin
-	CommittedM = 1'b1;
-	SelUncached = 1'b1;
-	SelAdrM = 2'b00;
-	if(StallWtoDCache) begin 
-	  NextState = STATE_CPU_BUSY;
-	  SelAdrM = 2'b10;
-	end
-	else begin
-	  NextState = STATE_READY;
-	end 
+		CommittedM = 1'b1;
+		SelUncached = 1'b1;
+		SelAdrM = 2'b00;
+		if(StallWtoDCache) begin 
+		  NextState = STATE_CPU_BUSY;
+		  SelAdrM = 2'b10;
+		end
+		else begin
+		  NextState = STATE_READY;
+		end 
       end
 
 
       // itlb => instruction page fault states with memory request.
       STATE_PTW_FAULT_READY: begin
-	DCacheStall = 1'b0;
-	LRUWriteEn = 1'b0;
-	SelAdrM = 2'b00;
-	MemAfterIWalkDone = 1'b0;
-	SetDirty = 1'b0;
-	LRUWriteEn = 1'b0;
-	CntReset = 1'b0;
-	AHBWrite = 1'b0;
-	AHBRead = 1'b0;
-	CommittedM = 1'b1;
-	NextState = STATE_READY;
-	
-	
-	// read hit valid cached
-	if(MemRWM[1] & CacheableM & CacheHit & ~DTLBMissM) begin
-	  DCacheStall = 1'b0;
-	  LRUWriteEn = 1'b1;
-	  
-	  if(StallWtoDCache) begin
-	    NextState = STATE_PTW_FAULT_CPU_BUSY;
+		DCacheStall = 1'b0;
+		LRUWriteEn = 1'b0;
+		SelAdrM = 2'b00;
+		MemAfterIWalkDone = 1'b0;
+		SetDirty = 1'b0;
+		LRUWriteEn = 1'b0;
+		CntReset = 1'b0;
+		AHBWrite = 1'b0;
+		AHBRead = 1'b0;
+		CommittedM = 1'b1;
+		NextState = STATE_READY;
+		
+		
+		// read hit valid cached
+		if(MemRWM[1] & CacheableM & CacheHit & ~DTLBMissM) begin
+		  DCacheStall = 1'b0;
+		  LRUWriteEn = 1'b1;
+		  
+		  if(StallWtoDCache) begin
+			NextState = STATE_PTW_FAULT_CPU_BUSY;
             SelAdrM = 2'b10;
-	  end
-	  else begin
-	    MemAfterIWalkDone = 1'b1;
-	    NextState = STATE_READY;
-	  end
-	end
-	
-	// write hit valid cached
-	else if (MemRWM[0] & CacheableM & CacheHit & ~DTLBMissM) begin
-	  SelAdrM = 2'b10;
-	  DCacheStall = 1'b0;
-	  SRAMWordWriteEnableM = 1'b1;
-	  SetDirty = 1'b1;
-	  LRUWriteEn = 1'b1;
-	  
-	  if(StallWtoDCache) begin 
-	    NextState = STATE_PTW_FAULT_CPU_BUSY;
-	    SelAdrM = 2'b10;
-	  end
-	  else begin
-	    MemAfterIWalkDone = 1'b1;
-	    NextState = STATE_READY;
-	  end
-	end
-	// read or write miss valid cached
-	else if((|MemRWM) & CacheableM & ~CacheHit & ~DTLBMissM) begin
-	  NextState = STATE_PTW_FAULT_MISS_FETCH_WDV;
-	  CntReset = 1'b1;
-	  DCacheStall = 1'b1;
-	end
-	// uncached write
-	else if(MemRWM[0] & ~CacheableM & ~DTLBMissM) begin
-	  NextState = STATE_PTW_FAULT_UNCACHED_WRITE;
-	  CntReset = 1'b1;
-	  DCacheStall = 1'b1;
-	  AHBWrite = 1'b1;
-	end
-	// uncached read
-	else if(MemRWM[1] & ~CacheableM & ~DTLBMissM) begin
-	  NextState = STATE_PTW_FAULT_UNCACHED_READ;
-	  CntReset = 1'b1;
-	  DCacheStall = 1'b1;
-	  AHBRead = 1'b1;	  
-	  MemAfterIWalkDone = 1'b0;
-	end
-	// fault
-	else  begin
-	  MemAfterIWalkDone = 1'b1;
-	  NextState = STATE_READY;
-	end
+		  end
+		  else begin
+			MemAfterIWalkDone = 1'b1;
+			NextState = STATE_READY;
+		  end
+		end
+		
+		// write hit valid cached
+		else if (MemRWM[0] & CacheableM & CacheHit & ~DTLBMissM) begin
+		  SelAdrM = 2'b10;
+		  DCacheStall = 1'b0;
+		  SRAMWordWriteEnableM = 1'b1;
+		  SetDirty = 1'b1;
+		  LRUWriteEn = 1'b1;
+		  
+		  if(StallWtoDCache) begin 
+			NextState = STATE_PTW_FAULT_CPU_BUSY;
+			SelAdrM = 2'b10;
+		  end
+		  else begin
+			MemAfterIWalkDone = 1'b1;
+			NextState = STATE_READY;
+		  end
+		end
+		// read or write miss valid cached
+		else if((|MemRWM) & CacheableM & ~CacheHit & ~DTLBMissM) begin
+		  NextState = STATE_PTW_FAULT_MISS_FETCH_WDV;
+		  CntReset = 1'b1;
+		  DCacheStall = 1'b1;
+		end
+		// uncached write
+		else if(MemRWM[0] & ~CacheableM & ~DTLBMissM) begin
+		  NextState = STATE_PTW_FAULT_UNCACHED_WRITE;
+		  CntReset = 1'b1;
+		  DCacheStall = 1'b1;
+		  AHBWrite = 1'b1;
+		end
+		// uncached read
+		else if(MemRWM[1] & ~CacheableM & ~DTLBMissM) begin
+		  NextState = STATE_PTW_FAULT_UNCACHED_READ;
+		  CntReset = 1'b1;
+		  DCacheStall = 1'b1;
+		  AHBRead = 1'b1;	  
+		  MemAfterIWalkDone = 1'b0;
+		end
+		// fault
+		else  begin
+		  MemAfterIWalkDone = 1'b1;
+		  NextState = STATE_READY;
+		end
       end
       
       STATE_PTW_FAULT_CPU_BUSY: begin
-	CommittedM = 1'b1;
-	if(StallWtoDCache) begin
-	  NextState = STATE_PTW_FAULT_CPU_BUSY;
-	  MemAfterIWalkDone = 1'b0;
-	  SelAdrM = 2'b10;
-	end
-	else begin
-	  MemAfterIWalkDone = 1'b1;
-	  NextState = STATE_READY;
-	  SelAdrM = 2'b00;
-	end
+		CommittedM = 1'b1;
+		if(StallWtoDCache) begin
+		  NextState = STATE_PTW_FAULT_CPU_BUSY;
+		  MemAfterIWalkDone = 1'b0;
+		  SelAdrM = 2'b10;
+		end
+		else begin
+		  MemAfterIWalkDone = 1'b1;
+		  NextState = STATE_READY;
+		  SelAdrM = 2'b00;
+		end
       end
 
       STATE_PTW_FAULT_MISS_FETCH_WDV: begin
-	DCacheStall = 1'b1;
+		DCacheStall = 1'b1;
         PreCntEn = 1'b1;
-	AHBRead = 1'b1;
-	SelAdrM = 2'b10;
-	CommittedM = 1'b1;
-	
+		AHBRead = 1'b1;
+		SelAdrM = 2'b10;
+		CommittedM = 1'b1;
+		
         if(FetchCountFlag & AHBAck) begin
           NextState = STATE_PTW_FAULT_MISS_FETCH_DONE;
         end else begin
@@ -713,201 +713,201 @@ module dcachefsm
       end
 
       STATE_PTW_FAULT_MISS_FETCH_DONE: begin
-	DCacheStall = 1'b1;
-	SelAdrM = 2'b10;
+		DCacheStall = 1'b1;
+		SelAdrM = 2'b10;
         CntReset = 1'b1;
-	CommittedM = 1'b1;
-	if(VictimDirty) begin
-	  NextState = STATE_PTW_FAULT_MISS_EVICT_DIRTY;
-	end else begin
-	  NextState = STATE_PTW_FAULT_MISS_WRITE_CACHE_BLOCK;
-	end
+		CommittedM = 1'b1;
+		if(VictimDirty) begin
+		  NextState = STATE_PTW_FAULT_MISS_EVICT_DIRTY;
+		end else begin
+		  NextState = STATE_PTW_FAULT_MISS_WRITE_CACHE_BLOCK;
+		end
       end
 
       STATE_PTW_FAULT_MISS_WRITE_CACHE_BLOCK: begin
-	SRAMBlockWriteEnableM = 1'b1;
-	DCacheStall = 1'b1;
-	NextState = STATE_PTW_FAULT_MISS_READ_WORD;
-	SelAdrM = 2'b10;
-	SetValid = 1'b1;
-	ClearDirty = 1'b1;
-	CommittedM = 1'b1;
-	//LRUWriteEn = 1'b1;  // DO not update LRU on SRAM fetch update.  Wait for subsequent read/write
+		SRAMBlockWriteEnableM = 1'b1;
+		DCacheStall = 1'b1;
+		NextState = STATE_PTW_FAULT_MISS_READ_WORD;
+		SelAdrM = 2'b10;
+		SetValid = 1'b1;
+		ClearDirty = 1'b1;
+		CommittedM = 1'b1;
+		//LRUWriteEn = 1'b1;  // DO not update LRU on SRAM fetch update.  Wait for subsequent read/write
       end
 
       STATE_PTW_FAULT_MISS_READ_WORD: begin
-	SelAdrM = 2'b10;
-	DCacheStall = 1'b1;
-	CommittedM = 1'b1;
-	if(MemRWM[1]) begin
-	  NextState = STATE_PTW_FAULT_MISS_READ_WORD_DELAY;
-	  // delay state is required as the read signal MemRWM[1] is still high when we
-	  // return to the ready state because the cache is stalling the cpu.
-	end else begin
-	  NextState = STATE_PTW_FAULT_MISS_WRITE_WORD;
-	end
+		SelAdrM = 2'b10;
+		DCacheStall = 1'b1;
+		CommittedM = 1'b1;
+		if(MemRWM[1]) begin
+		  NextState = STATE_PTW_FAULT_MISS_READ_WORD_DELAY;
+		  // delay state is required as the read signal MemRWM[1] is still high when we
+		  // return to the ready state because the cache is stalling the cpu.
+		end else begin
+		  NextState = STATE_PTW_FAULT_MISS_WRITE_WORD;
+		end
       end
 
       STATE_PTW_FAULT_MISS_READ_WORD_DELAY: begin
-	CommittedM = 1'b1;
-	LRUWriteEn = 1'b1;
-	if(StallWtoDCache) begin 
-	  NextState = STATE_PTW_FAULT_CPU_BUSY;
-	  SelAdrM = 2'b10;
-	  MemAfterIWalkDone = 1'b0;
-	end
-	else begin
-	  MemAfterIWalkDone = 1'b1;
-	  NextState = STATE_READY;
-	  SelAdrM = 2'b00;
-	end
+		CommittedM = 1'b1;
+		LRUWriteEn = 1'b1;
+		if(StallWtoDCache) begin 
+		  NextState = STATE_PTW_FAULT_CPU_BUSY;
+		  SelAdrM = 2'b10;
+		  MemAfterIWalkDone = 1'b0;
+		end
+		else begin
+		  MemAfterIWalkDone = 1'b1;
+		  NextState = STATE_READY;
+		  SelAdrM = 2'b00;
+		end
       end
 
       STATE_PTW_FAULT_MISS_WRITE_WORD: begin
-	SRAMWordWriteEnableM = 1'b1;
-	SetDirty = 1'b1;
-	SelAdrM = 2'b10;
-	DCacheStall = 1'b1;
-	CommittedM = 1'b1;
-	LRUWriteEn = 1'b1;
-	NextState = STATE_PTW_FAULT_MISS_WRITE_WORD_DELAY;
+		SRAMWordWriteEnableM = 1'b1;
+		SetDirty = 1'b1;
+		SelAdrM = 2'b10;
+		DCacheStall = 1'b1;
+		CommittedM = 1'b1;
+		LRUWriteEn = 1'b1;
+		NextState = STATE_PTW_FAULT_MISS_WRITE_WORD_DELAY;
       end
 
       STATE_PTW_FAULT_MISS_WRITE_WORD_DELAY: begin
-	CommittedM = 1'b1;
-	if(StallWtoDCache) begin 
-	  NextState = STATE_PTW_FAULT_CPU_BUSY;
-	  MemAfterIWalkDone = 1'b0;
-	  SelAdrM = 2'b10;
-	end
-	else begin
-	  MemAfterIWalkDone = 1'b1;
-	  NextState = STATE_READY;
-	  SelAdrM = 2'b00;
-	end
+		CommittedM = 1'b1;
+		if(StallWtoDCache) begin 
+		  NextState = STATE_PTW_FAULT_CPU_BUSY;
+		  MemAfterIWalkDone = 1'b0;
+		  SelAdrM = 2'b10;
+		end
+		else begin
+		  MemAfterIWalkDone = 1'b1;
+		  NextState = STATE_READY;
+		  SelAdrM = 2'b00;
+		end
       end
 
       STATE_PTW_FAULT_MISS_EVICT_DIRTY: begin
-	DCacheStall = 1'b1;
+		DCacheStall = 1'b1;
         PreCntEn = 1'b1;
-	AHBWrite = 1'b1;
-	SelAdrM = 2'b10;
-	CommittedM = 1'b1;
-	SelEvict = 1'b1;
-	if(FetchCountFlag & AHBAck) begin
-	  NextState = STATE_PTW_FAULT_MISS_WRITE_CACHE_BLOCK;
-	end else begin
-	  NextState = STATE_PTW_FAULT_MISS_EVICT_DIRTY;
-	end	  
+		AHBWrite = 1'b1;
+		SelAdrM = 2'b10;
+		CommittedM = 1'b1;
+		SelEvict = 1'b1;
+		if(FetchCountFlag & AHBAck) begin
+		  NextState = STATE_PTW_FAULT_MISS_WRITE_CACHE_BLOCK;
+		end else begin
+		  NextState = STATE_PTW_FAULT_MISS_EVICT_DIRTY;
+		end	  
       end
 
 
       STATE_PTW_FAULT_UNCACHED_WRITE : begin
-	DCacheStall = 1'b1;	
-	AHBWrite = 1'b1;
-	CommittedM = 1'b1;
-	if(AHBAck) begin
-	  NextState = STATE_PTW_FAULT_UNCACHED_WRITE_DONE;
-	end else begin
-	  NextState = STATE_PTW_FAULT_UNCACHED_WRITE;
-	end
+		DCacheStall = 1'b1;	
+		AHBWrite = 1'b1;
+		CommittedM = 1'b1;
+		if(AHBAck) begin
+		  NextState = STATE_PTW_FAULT_UNCACHED_WRITE_DONE;
+		end else begin
+		  NextState = STATE_PTW_FAULT_UNCACHED_WRITE;
+		end
       end
 
       STATE_PTW_FAULT_UNCACHED_READ : begin
-	DCacheStall = 1'b1;	
-	AHBRead = 1'b1;
-	CommittedM = 1'b1;
-	if(AHBAck) begin
-	  NextState = STATE_PTW_FAULT_UNCACHED_READ_DONE;
-	end else begin
-	  NextState = STATE_PTW_FAULT_UNCACHED_READ;
-	end
+		DCacheStall = 1'b1;	
+		AHBRead = 1'b1;
+		CommittedM = 1'b1;
+		if(AHBAck) begin
+		  NextState = STATE_PTW_FAULT_UNCACHED_READ_DONE;
+		end else begin
+		  NextState = STATE_PTW_FAULT_UNCACHED_READ;
+		end
       end
       
       STATE_PTW_FAULT_UNCACHED_WRITE_DONE: begin
-	CommittedM = 1'b1;
-	if(StallWtoDCache) begin
-	  NextState = STATE_PTW_FAULT_CPU_BUSY;
-	  MemAfterIWalkDone = 1'b0;
-	  SelAdrM = 2'b10;
-	end
-	else begin
-	  MemAfterIWalkDone = 1'b1;
-	  NextState = STATE_READY;
-	  SelAdrM = 2'b00;
-	end
+		CommittedM = 1'b1;
+		if(StallWtoDCache) begin
+		  NextState = STATE_PTW_FAULT_CPU_BUSY;
+		  MemAfterIWalkDone = 1'b0;
+		  SelAdrM = 2'b10;
+		end
+		else begin
+		  MemAfterIWalkDone = 1'b1;
+		  NextState = STATE_READY;
+		  SelAdrM = 2'b00;
+		end
       end
 
       STATE_PTW_FAULT_UNCACHED_READ_DONE: begin
-	CommittedM = 1'b1;
-	SelUncached = 1'b1;
-	if(StallWtoDCache) begin 
-	  NextState = STATE_PTW_FAULT_CPU_BUSY;
-	  SelAdrM = 2'b10;
-	end
-	else begin
-	  MemAfterIWalkDone = 1'b1;
-	  NextState = STATE_READY;
-	end 
+		CommittedM = 1'b1;
+		SelUncached = 1'b1;
+		if(StallWtoDCache) begin 
+		  NextState = STATE_PTW_FAULT_CPU_BUSY;
+		  SelAdrM = 2'b10;
+		end
+		else begin
+		  MemAfterIWalkDone = 1'b1;
+		  NextState = STATE_READY;
+		end 
       end
 
       STATE_FLUSH: begin
-	DCacheStall = 1'b1;
-	CommittedM = 1'b1;
-	SelAdrM = 2'b11;
-	SelFlush = 1'b1;
-	FlushAdrCntEn = 1'b1;
-	FlushWayCntEn = 1'b1;
-	CntReset = 1'b1;
-	if(VictimDirty) begin
-	  NextState = STATE_FLUSH_WRITE_BACK;
-	  FlushAdrCntEn = 1'b0;
-	  FlushWayCntEn = 1'b0;
-	end else if (FlushAdrFlag) begin
-	  NextState = STATE_READY;
-	  DCacheStall = 1'b0;
-	  FlushAdrCntEn = 1'b0;
-	  FlushWayCntEn = 1'b0;	
-	end else begin
-	  NextState = STATE_FLUSH;
-	end
+		DCacheStall = 1'b1;
+		CommittedM = 1'b1;
+		SelAdrM = 2'b11;
+		SelFlush = 1'b1;
+		FlushAdrCntEn = 1'b1;
+		FlushWayCntEn = 1'b1;
+		CntReset = 1'b1;
+		if(VictimDirty) begin
+		  NextState = STATE_FLUSH_WRITE_BACK;
+		  FlushAdrCntEn = 1'b0;
+		  FlushWayCntEn = 1'b0;
+		end else if (FlushAdrFlag) begin
+		  NextState = STATE_READY;
+		  DCacheStall = 1'b0;
+		  FlushAdrCntEn = 1'b0;
+		  FlushWayCntEn = 1'b0;	
+		end else begin
+		  NextState = STATE_FLUSH;
+		end
       end
 
       STATE_FLUSH_WRITE_BACK: begin
-	DCacheStall = 1'b1;
-	AHBWrite = 1'b1;
-	SelAdrM = 2'b11;
-	CommittedM = 1'b1;
-	SelFlush = 1'b1;
+		DCacheStall = 1'b1;
+		AHBWrite = 1'b1;
+		SelAdrM = 2'b11;
+		CommittedM = 1'b1;
+		SelFlush = 1'b1;
         PreCntEn = 1'b1;
-	if(FetchCountFlag & AHBAck) begin
-	  NextState = STATE_FLUSH_CLEAR_DIRTY;
-	end else begin
-	  NextState = STATE_FLUSH_WRITE_BACK;
-	end	  
+		if(FetchCountFlag & AHBAck) begin
+		  NextState = STATE_FLUSH_CLEAR_DIRTY;
+		end else begin
+		  NextState = STATE_FLUSH_WRITE_BACK;
+		end	  
       end
 
       STATE_FLUSH_CLEAR_DIRTY: begin
-	DCacheStall = 1'b1;
-	ClearDirty = 1'b1;
-	VDWriteEnable = 1'b1;
-	SelFlush = 1'b1;
-	SelAdrM = 2'b11;
-	FlushAdrCntEn = 1'b0;
-	FlushWayCntEn = 1'b0;	
-	if(FlushAdrFlag) begin
-	  NextState = STATE_READY;
-	  DCacheStall = 1'b0;
-	  SelAdrM = 2'b00;
-	end else begin
-	  NextState = STATE_FLUSH;
-	  FlushAdrCntEn = 1'b1;
-	  FlushWayCntEn = 1'b1;	
-	end
+		DCacheStall = 1'b1;
+		ClearDirty = 1'b1;
+		VDWriteEnable = 1'b1;
+		SelFlush = 1'b1;
+		SelAdrM = 2'b11;
+		FlushAdrCntEn = 1'b0;
+		FlushWayCntEn = 1'b0;	
+		if(FlushAdrFlag) begin
+		  NextState = STATE_READY;
+		  DCacheStall = 1'b0;
+		  SelAdrM = 2'b00;
+		end else begin
+		  NextState = STATE_FLUSH;
+		  FlushAdrCntEn = 1'b1;
+		  FlushWayCntEn = 1'b1;	
+		end
       end
 
       default: begin
-	NextState = STATE_READY;
+		NextState = STATE_READY;
       end
     endcase
   end
diff --git a/wally-pipelined/src/cache/icachefsm.sv b/wally-pipelined/src/cache/icachefsm.sv
index 433328ab..33080d9f 100644
--- a/wally-pipelined/src/cache/icachefsm.sv
+++ b/wally-pipelined/src/cache/icachefsm.sv
@@ -27,95 +27,95 @@
 
 module icachefsm
   (// Inputs from pipeline
-   input logic 	      clk, reset,
+   input logic 		  clk, reset,
 
-   input logic 	      StallF,
+   input logic 		  StallF,
 
    // inputs from mmu
-   input logic 	      ITLBMissF,
-   input logic 	      ITLBWriteF,
-   input logic 	      WalkerInstrPageFaultF,
+   input logic 		  ITLBMissF,
+   input logic 		  ITLBWriteF,
+   input logic 		  WalkerInstrPageFaultF,
 
-   input logic ExceptionM, PendingInterruptM,
+   input logic 		  ExceptionM, PendingInterruptM,
 
    // BUS interface
-   input logic 	      InstrAckF,
+   input logic 		  InstrAckF,
 
    // icache internal inputs
-   input logic 	      hit,
-   input logic 	      FetchCountFlag,
-   input logic 	      spill,
+   input logic 		  hit,
+   input logic 		  FetchCountFlag,
+   input logic 		  spill,
 
    // icache internal outputs
-   output logic       ICacheReadEn,
+   output logic 	  ICacheReadEn,
    // Load data into the cache
-   output logic       ICacheMemWriteEnable,
+   output logic 	  ICacheMemWriteEnable,
 
    // Outputs to pipeline control stuff
-   output logic       ICacheStallF,
+   output logic 	  ICacheStallF,
 
    // Bus interface outputs
-   output logic       InstrReadF,
+   output logic 	  InstrReadF,
 
    // icache internal outputs
-   output logic       spillSave,
-   output logic       CntEn,
-   output logic       CntReset,
+   output logic 	  spillSave,
+   output logic 	  CntEn,
+   output logic 	  CntReset,
    output logic [1:0] SelAdr,
-   output logic       LRUWriteEn
+   output logic 	  LRUWriteEn
    );
 
   // FSM states
-  typedef enum {STATE_READY,
-		STATE_HIT_SPILL, // spill, block 0 hit
-		STATE_HIT_SPILL_MISS_FETCH_WDV, // block 1 miss, issue read to AHB and wait data.
-		STATE_HIT_SPILL_MISS_FETCH_DONE, // write data into SRAM/LUT
-		STATE_HIT_SPILL_MERGE,   // Read block 0 of CPU access, should be able to optimize into STATE_HIT_SPILL.
+  typedef enum 		  {STATE_READY,
+					   STATE_HIT_SPILL, // spill, block 0 hit
+					   STATE_HIT_SPILL_MISS_FETCH_WDV, // block 1 miss, issue read to AHB and wait data.
+					   STATE_HIT_SPILL_MISS_FETCH_DONE, // write data into SRAM/LUT
+					   STATE_HIT_SPILL_MERGE,   // Read block 0 of CPU access, should be able to optimize into STATE_HIT_SPILL.
 
-		// a challenge is the spill signal gets us out of the ready state and moves us to
-		// 1 of the 2 spill branches.  However the original fsm design had us return to
-		// the ready state when the spill + hits/misses were fully resolved.  The problem
-		// is the spill signal is based on PCPF so when we return to READY to check if the
-		// cache has a hit it still expresses spill.  We can fix in 1 of two ways.
-		// 1. we can add 1 extra state at the end of each spill branch to returns the instruction
-		// to the CPU advancing the CPU and icache to the next instruction.
-		// 2. We can assert a signal which is delayed 1 cycle to suppress the spill when we get
-		// to the READY state.
-		// The first first option is more robust and increases the number of states by 2.  The
-		// second option is seams like it should work, but I worry there is a hidden interaction 
-		// between CPU stalling and that register.
-		// Picking option 1.
+					   // a challenge is the spill signal gets us out of the ready state and moves us to
+					   // 1 of the 2 spill branches.  However the original fsm design had us return to
+					   // the ready state when the spill + hits/misses were fully resolved.  The problem
+					   // is the spill signal is based on PCPF so when we return to READY to check if the
+					   // cache has a hit it still expresses spill.  We can fix in 1 of two ways.
+					   // 1. we can add 1 extra state at the end of each spill branch to returns the instruction
+					   // to the CPU advancing the CPU and icache to the next instruction.
+					   // 2. We can assert a signal which is delayed 1 cycle to suppress the spill when we get
+					   // to the READY state.
+					   // The first first option is more robust and increases the number of states by 2.  The
+					   // second option is seams like it should work, but I worry there is a hidden interaction 
+					   // between CPU stalling and that register.
+					   // Picking option 1.
 
-		STATE_HIT_SPILL_FINAL, // this state replicates STATE_READY's replay of the
-		// spill access but does nto consider spill.  It also does not do another operation.
+					   STATE_HIT_SPILL_FINAL, // this state replicates STATE_READY's replay of the
+					   // spill access but does nto consider spill.  It also does not do another operation.
   
-		STATE_MISS_FETCH_WDV, // aligned miss, issue read to AHB and wait for data.
-		STATE_MISS_FETCH_DONE, // write data into SRAM/LUT
-		STATE_MISS_READ, // read block 1 from SRAM/LUT
-		STATE_MISS_READ_DELAY, // read block 1 from SRAM/LUT  		
+					   STATE_MISS_FETCH_WDV, // aligned miss, issue read to AHB and wait for data.
+					   STATE_MISS_FETCH_DONE, // write data into SRAM/LUT
+					   STATE_MISS_READ, // read block 1 from SRAM/LUT
+					   STATE_MISS_READ_DELAY, // read block 1 from SRAM/LUT  		
 
-		STATE_MISS_SPILL_FETCH_WDV, // spill, miss on block 0, issue read to AHB and wait
-		STATE_MISS_SPILL_FETCH_DONE, // write data into SRAM/LUT
-		STATE_MISS_SPILL_READ1, // read block 0 from SRAM/LUT
-		STATE_MISS_SPILL_2, // return to ready if hit or do second block update.
-		STATE_MISS_SPILL_2_START, // return to ready if hit or do second block update.  
-		STATE_MISS_SPILL_MISS_FETCH_WDV, // miss on block 1, issue read to AHB and wait
-		STATE_MISS_SPILL_MISS_FETCH_DONE, // write data to SRAM/LUT
-		STATE_MISS_SPILL_MERGE, // read block 0 of CPU access,
+					   STATE_MISS_SPILL_FETCH_WDV, // spill, miss on block 0, issue read to AHB and wait
+					   STATE_MISS_SPILL_FETCH_DONE, // write data into SRAM/LUT
+					   STATE_MISS_SPILL_READ1, // read block 0 from SRAM/LUT
+					   STATE_MISS_SPILL_2, // return to ready if hit or do second block update.
+					   STATE_MISS_SPILL_2_START, // return to ready if hit or do second block update.  
+					   STATE_MISS_SPILL_MISS_FETCH_WDV, // miss on block 1, issue read to AHB and wait
+					   STATE_MISS_SPILL_MISS_FETCH_DONE, // write data to SRAM/LUT
+					   STATE_MISS_SPILL_MERGE, // read block 0 of CPU access,
 
-		STATE_MISS_SPILL_FINAL, // this state replicates STATE_READY's replay of the
-		// spill access but does nto consider spill.  It also does not do another operation.
+					   STATE_MISS_SPILL_FINAL, // this state replicates STATE_READY's replay of the
+					   // spill access but does nto consider spill.  It also does not do another operation.
 
-		STATE_INVALIDATE, // *** not sure if invalidate or evict? invalidate by cache block or address?
-		STATE_TLB_MISS,
-		STATE_TLB_MISS_DONE,
+					   STATE_INVALIDATE, // *** not sure if invalidate or evict? invalidate by cache block or address?
+					   STATE_TLB_MISS,
+					   STATE_TLB_MISS_DONE,
 
-		STATE_CPU_BUSY,
-		STATE_CPU_BUSY_SPILL		
-		} statetype;
+					   STATE_CPU_BUSY,
+					   STATE_CPU_BUSY_SPILL		
+					   } statetype;
   
   (* mark_debug = "true" *)  statetype CurrState, NextState;
-  logic 		       PreCntEn;
+  logic 			  PreCntEn;
 
   // the FSM is always runing, do not stall.
   always_ff @(posedge clk)
@@ -141,18 +141,18 @@ module icachefsm
           NextState = STATE_TLB_MISS;
         end else if (hit & ~spill) begin
           ICacheStallF = 1'b0;
-	  LRUWriteEn = 1'b1;
-	  if(StallF) begin
-	    NextState = STATE_CPU_BUSY;
-	    SelAdr = 2'b01;
-	  end else begin
+		  LRUWriteEn = 1'b1;
+		  if(StallF) begin
+			NextState = STATE_CPU_BUSY;
+			SelAdr = 2'b01;
+		  end else begin
             NextState = STATE_READY;
-	  end
+		  end
         end else if (hit & spill) begin
           spillSave = 1'b1;
           SelAdr = 2'b10;
           LRUWriteEn = 1'b1;
-	  NextState = STATE_HIT_SPILL;
+		  NextState = STATE_HIT_SPILL;
         end else if (~hit & ~spill) begin
           CntReset = 1'b1;
           NextState = STATE_MISS_FETCH_WDV;
@@ -161,12 +161,12 @@ module icachefsm
           SelAdr = 2'b01;
           NextState = STATE_MISS_SPILL_FETCH_WDV;
         end else begin
-	  if(StallF) begin
-	    NextState = STATE_CPU_BUSY;
-	    SelAdr = 2'b01;
-	  end else begin
+		  if(StallF) begin
+			NextState = STATE_CPU_BUSY;
+			SelAdr = 2'b01;
+		  end else begin
             NextState = STATE_READY;
-	  end
+		  end
         end
       end
       // branch 1,  hit spill and 2, miss spill hit
@@ -204,15 +204,15 @@ module icachefsm
         ICacheReadEn = 1'b1;
         SelAdr = 2'b00;
         ICacheStallF = 1'b0;
-	LRUWriteEn = 1'b1;
-	
-	if(StallF) begin
-	  NextState = STATE_CPU_BUSY_SPILL;
-	  SelAdr = 2'b10;
-	end else begin
+		LRUWriteEn = 1'b1;
+		
+		if(StallF) begin
+		  NextState = STATE_CPU_BUSY_SPILL;
+		  SelAdr = 2'b10;
+		end else begin
           NextState = STATE_READY;
-	end
-	
+		end
+		
       end
       // branch 3 miss no spill
       STATE_MISS_FETCH_WDV: begin
@@ -238,15 +238,15 @@ module icachefsm
       STATE_MISS_READ_DELAY: begin
         //SelAdr = 2'b01;
         ICacheReadEn = 1'b1;
-	ICacheStallF = 1'b0;
-	LRUWriteEn = 1'b1;
-	if(StallF) begin
-	  SelAdr = 2'b01;
-	  NextState = STATE_CPU_BUSY;
-	  SelAdr = 2'b01;
-	end else begin
+		ICacheStallF = 1'b0;
+		LRUWriteEn = 1'b1;
+		if(StallF) begin
+		  SelAdr = 2'b01;
+		  NextState = STATE_CPU_BUSY;
+		  SelAdr = 2'b01;
+		end else begin
           NextState = STATE_READY;
-	end
+		end
       end
       // branch 4 miss spill hit, and 5 miss spill miss
       STATE_MISS_SPILL_FETCH_WDV: begin
@@ -267,7 +267,7 @@ module icachefsm
       STATE_MISS_SPILL_READ1: begin // always be a hit as we just wrote that cache block.
         SelAdr = 2'b01;	 // there is a 1 cycle delay after setting the address before the date arrives.
         ICacheReadEn = 1'b1;
-	LRUWriteEn = 1'b1;
+		LRUWriteEn = 1'b1;
         NextState = STATE_MISS_SPILL_2;
       end
       STATE_MISS_SPILL_2: begin
@@ -284,13 +284,13 @@ module icachefsm
           ICacheReadEn = 1'b1;
           SelAdr = 2'b00;
           ICacheStallF = 1'b0;
-	  LRUWriteEn = 1'b1;
-	  if(StallF) begin
-	    NextState = STATE_CPU_BUSY;
-	    SelAdr = 2'b01;
-	  end else begin
+		  LRUWriteEn = 1'b1;
+		  if(StallF) begin
+			NextState = STATE_CPU_BUSY;
+			SelAdr = 2'b01;
+		  end else begin
             NextState = STATE_READY;
-	  end
+		  end
         end
       end
       STATE_MISS_SPILL_MISS_FETCH_WDV: begin
@@ -317,13 +317,13 @@ module icachefsm
         ICacheReadEn = 1'b1;
         SelAdr = 2'b00;
         ICacheStallF = 1'b0;	
-	LRUWriteEn = 1'b1;
-	if(StallF) begin
-	  NextState = STATE_CPU_BUSY_SPILL;
-	  SelAdr = 2'b10;
-	end else begin
+		LRUWriteEn = 1'b1;
+		if(StallF) begin
+		  NextState = STATE_CPU_BUSY_SPILL;
+		  SelAdr = 2'b10;
+		end else begin
           NextState = STATE_READY;
-	end
+		end
       end
       STATE_TLB_MISS: begin
         if (WalkerInstrPageFaultF) begin
@@ -336,33 +336,33 @@ module icachefsm
         end
       end
       STATE_TLB_MISS_DONE: begin
-	SelAdr = 2'b01;
+		SelAdr = 2'b01;
         NextState = STATE_READY;
       end
       STATE_CPU_BUSY: begin
-	ICacheStallF = 1'b0;
-	if (ITLBMissF) begin
+		ICacheStallF = 1'b0;
+		if (ITLBMissF) begin
           NextState = STATE_TLB_MISS;
-	end else if(StallF) begin
-	  NextState = STATE_CPU_BUSY;
-	  SelAdr = 2'b01;
-	end
-	else begin
-	  NextState = STATE_READY;
-	end
+		end else if(StallF) begin
+		  NextState = STATE_CPU_BUSY;
+		  SelAdr = 2'b01;
+		end
+		else begin
+		  NextState = STATE_READY;
+		end
       end
       STATE_CPU_BUSY_SPILL: begin
-	ICacheStallF = 1'b0;
-	ICacheReadEn = 1'b1;
-	if (ITLBMissF) begin
+		ICacheStallF = 1'b0;
+		ICacheReadEn = 1'b1;
+		if (ITLBMissF) begin
           NextState = STATE_TLB_MISS;
-	end else if(StallF) begin
-	  NextState = STATE_CPU_BUSY_SPILL;
-	  SelAdr = 2'b10;
-	end
-	else begin
-	  NextState = STATE_READY;
-	end
+		end else if(StallF) begin
+		  NextState = STATE_CPU_BUSY_SPILL;
+		  SelAdr = 2'b10;
+		end
+		else begin
+		  NextState = STATE_READY;
+		end
       end
       default: begin
         SelAdr = 2'b01;
@@ -374,8 +374,8 @@ module icachefsm
 
   assign CntEn = PreCntEn & InstrAckF;
   assign InstrReadF = (CurrState == STATE_HIT_SPILL_MISS_FETCH_WDV) ||
-		      (CurrState == STATE_MISS_FETCH_WDV) ||
-		      (CurrState == STATE_MISS_SPILL_FETCH_WDV) ||
-		      (CurrState == STATE_MISS_SPILL_MISS_FETCH_WDV);
+					  (CurrState == STATE_MISS_FETCH_WDV) ||
+					  (CurrState == STATE_MISS_SPILL_FETCH_WDV) ||
+					  (CurrState == STATE_MISS_SPILL_MISS_FETCH_WDV);
   
 endmodule