From 80ca75e21673f9e540b601c8c385f14edc26aecd Mon Sep 17 00:00:00 2001
From: cturek <cturek@hmc.edu>
Date: Thu, 22 Dec 2022 05:44:55 +0000
Subject: [PATCH] Added ForwardedSrcAM to postprocessor. Now passing 8 tests on
 rv32gc.

---
 pipelined/src/fpu/fdivsqrt/fdivsqrt.sv        |  5 +++--
 .../src/fpu/fdivsqrt/fdivsqrtpostproc.sv      | 22 ++++++++++++-------
 pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv |  5 +++--
 3 files changed, 20 insertions(+), 12 deletions(-)

diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
index a780aaca..86993a7d 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
@@ -69,10 +69,11 @@ module fdivsqrt(
   logic [`DIVBLEN:0] nE, nM, mM;
   logic OTFCSwapE, ALTBM, As;
   logic DivStartE;
+  logic [`XLEN-1:0] ForwardedSrcAM;
 
   fdivsqrtpreproc fdivsqrtpreproc(
     .clk, .IFDivStartE, .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE), 
-    .Sqrt(SqrtE), .Ym(YmE), .XZeroE, .X, .DPreproc, 
+    .Sqrt(SqrtE), .Ym(YmE), .XZeroE, .X, .DPreproc, .ForwardedSrcAM,
     .nE, .nM, .mM, .OTFCSwapE, .ALTBM, .AZeroM, .BZeroM, .AZeroE, .BZeroE, .As,
     .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E);
   fdivsqrtfsm fdivsqrtfsm(
@@ -88,7 +89,7 @@ module fdivsqrt(
     .FDivBusyE);
   fdivsqrtpostproc fdivsqrtpostproc(
     .WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun, 
-    .SqrtM, .SpecialCaseM, .RemOpM(Funct3M[1]), .ForwardedSrcAE,
+    .SqrtM, .SpecialCaseM, .RemOpM(Funct3M[1]), .ForwardedSrcAM,
     .nM, .ALTBM, .mM, .BZeroM, .As,
     .QmM, .WZeroM, .DivSM, .FPIntDivResultM);
 endmodule
\ No newline at end of file
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
index 3b20570f..87bb47d6 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
@@ -38,7 +38,7 @@ module fdivsqrtpostproc(
   input  logic              Firstun,
   input  logic              SqrtM,
   input  logic              SpecialCaseM,
-	input  logic [`XLEN-1:0]  ForwardedSrcAE,
+	input  logic [`XLEN-1:0]  ForwardedSrcAM,
   input  logic              RemOpM, ALTBM, BZeroM, As,
   input  logic [`DIVBLEN:0] nM, mM,
   output logic [`DIVb:0]    QmM, 
@@ -106,12 +106,12 @@ module fdivsqrtpostproc(
 
   // Integer division: Special cases
   always_comb
-    if(ALTBM) begin
-      IntQuotM = '0;
-      IntRemM  = {{(`DIVb-`XLEN+4){1'b0}}, ForwardedSrcAE};
-    end else if (BZeroM) begin
+    if (BZeroM) begin
       IntQuotM = '1;
-      IntRemM  = {{(`DIVb-`XLEN+4){1'b0}}, ForwardedSrcAE};
+      IntRemM  = {{(`DIVb-`XLEN+4){1'b0}}, ForwardedSrcAM};
+    end else if (ALTBM) begin
+      IntQuotM = '0;
+      IntRemM  = {{(`DIVb-`XLEN+4){1'b0}}, ForwardedSrcAM};
     end else if (WZeroM) begin
       if (weq0) begin
         IntQuotM = FirstU;
@@ -130,8 +130,14 @@ module fdivsqrtpostproc(
       NormShiftM = (mM + (`DIVBLEN+1)'(`DIVa));
       PreResultM = IntRemM;
     end else begin
-      NormShiftM = ((`DIVBLEN+1)'(`DIVb) - (nM * (`DIVBLEN+1)'(`LOGR)));
-      PreResultM = {3'b000, IntQuotM};
+      if (BZeroM) begin
+        NormShiftM = 0;
+        PreResultM = {3'b111, IntQuotM};
+      end else begin
+        NormShiftM = ((`DIVBLEN+1)'(`DIVb) - (nM * (`DIVBLEN+1)'(`LOGR)));
+        PreResultM = {3'b000, IntQuotM};
+      end
+      //PreResultM = {IntQuotM[`DIVb], IntQuotM[`DIVb], IntQuotM[`DIVb], IntQuotM}; // Suspicious Sign Extender
     end
   
 
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
index c5d2676e..359bb0c8 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
@@ -45,7 +45,8 @@ module fdivsqrtpreproc (
   output logic OTFCSwapE, ALTBM, As, AZeroM, BZeroM, AZeroE, BZeroE,
   output logic [`NE+1:0] QeM,
   output logic [`DIVb+3:0] X,
-  output logic [`DIVb-1:0] DPreproc
+  output logic [`DIVb-1:0] DPreproc,
+  output logic [`XLEN-1:0] ForwardedSrcAM
 );
 
   logic  [`DIVb-1:0] XPreproc;
@@ -129,7 +130,7 @@ module fdivsqrtpreproc (
   flopen #(1)      bzeroreg(clk, IFDivStartE, BZeroE, BZeroM);
   flopen #(`DIVBLEN+1) nreg(clk, IFDivStartE, nE, nM);
   flopen #(`DIVBLEN+1) mreg(clk, IFDivStartE, mE, mM);
-  //flopen #(`XLEN)   srcareg(clk, IFDivStartE, ForwardedSrcAE, ForwardedSrcAM); //HERE
+  flopen #(`XLEN)   srcareg(clk, IFDivStartE, ForwardedSrcAE, ForwardedSrcAM);
   expcalc expcalc(.Fmt, .Xe, .Ye, .Sqrt, .XZeroE, .ell, .m(mE), .Qe(QeE));
 
 endmodule