From 80be2e7be5b845a1302a47ae47f21b7187b71862 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 20 Dec 2022 18:05:44 -0600 Subject: [PATCH] privileged pc mux cleanup. --- pipelined/src/privileged/csr.sv | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index fc9a9f68..c14a7a00 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -100,8 +100,8 @@ module csr #(parameter logic [`XLEN-1:0] TVec, TrapVector, NextFaultMtvalM; logic MTrapM, STrapM; - logic [`XLEN-1:0] PrivilegedNextPCM; - + logic [`XLEN-1:0] XEPC_REG; + logic RetM; logic InstrValidNotFlushedM; assign InstrValidNotFlushedM = ~StallW & ~FlushW; @@ -146,14 +146,10 @@ module csr #(parameter assign TrapVector = {TVec[`XLEN-1:2], 2'b00}; end - always_comb - if (TrapM) PrivilegedNextPCM = TrapVector; - else if (mretM) PrivilegedNextPCM = MEPC_REGW; - else PrivilegedNextPCM = SEPC_REGW; - - logic PrivilegedChangePCM; - assign PrivilegedChangePCM = mretM | sretM | TrapM; - mux2 #(`XLEN) pcmux3(.d0(PCNext2F), .d1(PrivilegedNextPCM), .s(PrivilegedChangePCM), .y(UnalignedPCNextF)); + assign RetM = mretM | sretM; + mux2 #(`XLEN) xepcMux(SEPC_REGW, MEPC_REGW, mretM, XEPC_REG); + mux3 #(`XLEN) pcmux3(PCNext2F, XEPC_REG, TrapVector, {TrapM, RetM}, UnalignedPCNextF); + /////////////////////////////////////////// // CSRWriteValM