From 8045b50fc7ebc7479c70e6b8c32649e9ee31ea41 Mon Sep 17 00:00:00 2001 From: James Stine Date: Tue, 1 Nov 2022 07:36:39 -0500 Subject: [PATCH] Commit debug module wip --- pipelined/dm/fifo.do | 63 ++++++++++++ pipelined/dm/fifo.sv | 43 +++++++++ pipelined/dm/fifomem.sv | 24 +++++ pipelined/dm/flopenl.sv | 43 +++++++++ pipelined/dm/flopenr.sv | 42 ++++++++ pipelined/dm/flopr.sv | 42 ++++++++ pipelined/dm/jtag.sv | 182 +++++++++++++++++++++++++++++++++++ pipelined/dm/jtag_fsm.sv | 113 ++++++++++++++++++++++ pipelined/dm/jtag_tap.do | 57 +++++++++++ pipelined/dm/jtag_tap.sv | 185 ++++++++++++++++++++++++++++++++++++ pipelined/dm/jtag_tap_tb.sv | 101 ++++++++++++++++++++ pipelined/dm/notes | 6 ++ pipelined/dm/rptr_empty.sv | 37 ++++++++ pipelined/dm/sync_r2w.sv | 16 ++++ pipelined/dm/sync_w2r.sv | 16 ++++ pipelined/dm/tap.do | 81 ++++++++++++++++ pipelined/dm/tap.out | 0 pipelined/dm/tap_fsm.sv | 161 +++++++++++++++++++++++++++++++ pipelined/dm/tap_tb.sv | 86 +++++++++++++++++ pipelined/dm/tb.sv | 81 ++++++++++++++++ pipelined/dm/wptr_full.sv | 44 +++++++++ 21 files changed, 1423 insertions(+) create mode 100644 pipelined/dm/fifo.do create mode 100644 pipelined/dm/fifo.sv create mode 100644 pipelined/dm/fifomem.sv create mode 100644 pipelined/dm/flopenl.sv create mode 100644 pipelined/dm/flopenr.sv create mode 100644 pipelined/dm/flopr.sv create mode 100644 pipelined/dm/jtag.sv create mode 100644 pipelined/dm/jtag_fsm.sv create mode 100644 pipelined/dm/jtag_tap.do create mode 100644 pipelined/dm/jtag_tap.sv create mode 100644 pipelined/dm/jtag_tap_tb.sv create mode 100644 pipelined/dm/notes create mode 100644 pipelined/dm/rptr_empty.sv create mode 100644 pipelined/dm/sync_r2w.sv create mode 100644 pipelined/dm/sync_w2r.sv create mode 100644 pipelined/dm/tap.do create mode 100644 pipelined/dm/tap.out create mode 100644 pipelined/dm/tap_fsm.sv create mode 100644 pipelined/dm/tap_tb.sv create mode 100755 pipelined/dm/tb.sv create mode 100644 pipelined/dm/wptr_full.sv diff --git a/pipelined/dm/fifo.do b/pipelined/dm/fifo.do new file mode 100644 index 00000000..210ac073 --- /dev/null +++ b/pipelined/dm/fifo.do @@ -0,0 +1,63 @@ +# Copyright 1991-2016 Mentor Graphics Corporation +# +# Modification by Oklahoma State University +# Use with Testbench +# James Stine, 2008 +# Go Cowboys!!!!!! +# +# All Rights Reserved. +# +# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION +# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION +# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. + +# Use this run.do file to run this example. +# Either bring up ModelSim and type the following at the "ModelSim>" prompt: +# do run.do +# or, to run from a shell, type the following at the shell prompt: +# vsim -do run.do -c +# (omit the "-c" to see the GUI while running from the shell) + +onbreak {resume} + +# create library +if [file exists work] { + vdel -all +} +vlib work + +# compile source files +vlog sync_r2w.sv sync_w2r.sv rptr_empty.sv wptr_full.sv fifomem.sv fifo.sv tb.sv + +# start and run simulation +vsim -voptargs=+acc work.stimulus + +view wave + +-- display input and output signals as hexidecimal values +# Diplays All Signals recursively +# add wave -hex -r /stimulus/* + +add wave -noupdate -divider -height 32 "fifomem" +add wave -hex /stimulus/dut/fifomem/* +add wave -noupdate -divider -height 32 "wptr_full" +add wave -hex /stimulus/dut/wptr_full/* +add wave -noupdate -divider -height 32 "rptr_full" +add wave -hex /stimulus/dut/rptr_full/* + + +-- Set Wave Output Items +TreeUpdate [SetDefaultTree] +WaveRestoreZoom {0 ps} {75 ns} +configure wave -namecolwidth 150 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 + +-- Run the Simulation +run -all +quit diff --git a/pipelined/dm/fifo.sv b/pipelined/dm/fifo.sv new file mode 100644 index 00000000..b6f3fcdc --- /dev/null +++ b/pipelined/dm/fifo.sv @@ -0,0 +1,43 @@ +module fifo #(parameter DSIZE = 8, + parameter ASIZE = 4) + (rdata, wfull, rempty, wdata, + winc, wclk, wrst_n, rinc, rclk, rrst_n); + + input logic [DSIZE-1:0] wdata; + input logic winc; + input logic wclk; + input logic wrst_n; + input logic rinc; + input logic rclk; + input logic rrst_n; + + output logic [DSIZE-1:0] rdata; + output logic wfull; + output logic rempty; + + logic [ASIZE-1:0] waddr, raddr; + logic [ASIZE:0] wptr, rptr, wq2_rptr, rq2_wptr; + + sync_r2w sync_r2w (.wq2_rptr(wq2_rptr), .rptr(rptr), + .wclk(wclk), .wrst_n(wrst_n)); + sync_w2r sync_w2r (.rq2_wptr(rq2_wptr), .wptr(wptr), + .rclk(rclk), .rrst_n(rrst_n)); + + fifomem #(DSIZE, ASIZE) fifomem (.rdata(rdata), .wdata(wdata), + .waddr(waddr), .raddr(raddr), + .wclken(winc), .wfull(wfull), + .wclk(wclk)); + rptr_empty #(ASIZE) rptr_empty (.rempty(rempty), .raddr(raddr), + .rptr(rptr), .rq2_wptr(rq2_wptr), + .rinc(rinc), .rclk(rclk), + .rrst_n(rrst_n)); + wptr_full #(ASIZE) wptr_full (.wfull(wfull), .waddr(waddr), + .wptr(wptr), .wq2_rptr(wq2_rptr), + .winc(winc), .wclk(wclk), + .wrst_n(wrst_n)); + +endmodule // fifo1 + + + + diff --git a/pipelined/dm/fifomem.sv b/pipelined/dm/fifomem.sv new file mode 100644 index 00000000..3e3665c0 --- /dev/null +++ b/pipelined/dm/fifomem.sv @@ -0,0 +1,24 @@ + +// DATASIZE = Memory data word width +// ADDRSIZE = Number of mem address bits +module fifomem #(parameter DATASIZE = 8, + parameter ADDRSIZE = 4) + (rdata, wdata, waddr, raddr, wclken, wfull, wclk); + + input logic [DATASIZE-1:0] wdata; + input logic [ADDRSIZE-1:0] waddr; + input logic [ADDRSIZE-1:0] raddr; + input logic wclken; + input logic wfull; + input logic wclk; + output logic [DATASIZE-1:0] rdata; + + // RTL Verilog memory model + localparam DEPTH = 1 << ADDRSIZE; + logic [DATASIZE-1:0] mem [0:DEPTH-1]; + + assign rdata = mem[raddr]; + always @(posedge wclk) + if (wclken && !wfull) mem[waddr] <= wdata; + +endmodule // fifomem diff --git a/pipelined/dm/flopenl.sv b/pipelined/dm/flopenl.sv new file mode 100644 index 00000000..9147fe05 --- /dev/null +++ b/pipelined/dm/flopenl.sv @@ -0,0 +1,43 @@ +/////////////////////////////////////////// +// flopenl.sv +// +// Written: David_Harris@hmc.edu 9 January 2021 +// Modified: +// +// Purpose: various flavors of flip-flops +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ns +// flop with enable, synchronous load +module flopenl #(parameter WIDTH = 8, parameter type TYPE=logic [WIDTH-1:0]) ( + input logic clk, load, en, + input TYPE d, + input TYPE val, + output TYPE q); + + always_ff @(posedge clk) + if (load) q <= #1 val; + else if (en) q <= #1 d; +endmodule + diff --git a/pipelined/dm/flopenr.sv b/pipelined/dm/flopenr.sv new file mode 100644 index 00000000..f13c3106 --- /dev/null +++ b/pipelined/dm/flopenr.sv @@ -0,0 +1,42 @@ +/////////////////////////////////////////// +// flopenr.sv +// +// Written: David_Harris@hmc.edu 9 January 2021 +// Modified: +// +// Purpose: various flavors of flip-flops +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ns +// flop with enable, synchronous reset +module flopenr #(parameter WIDTH = 8) ( + input logic clk, reset, en, + input logic [WIDTH-1:0] d, + output logic [WIDTH-1:0] q); + + always_ff @(posedge clk) + if (reset) q <= #1 0; + else if (en) q <= #1 d; +endmodule + diff --git a/pipelined/dm/flopr.sv b/pipelined/dm/flopr.sv new file mode 100644 index 00000000..3c913993 --- /dev/null +++ b/pipelined/dm/flopr.sv @@ -0,0 +1,42 @@ +/////////////////////////////////////////// +// flopr.sv +// +// Written: David_Harris@hmc.edu 9 January 2021 +// Modified: +// +// Purpose: various flavors of flip-flops +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ns +// flop with synchronous reset +module flopr #(parameter WIDTH = 8) ( + input logic clk, reset, + input logic [WIDTH-1:0] d, + output logic [WIDTH-1:0] q); + + always_ff @(posedge clk) + if (reset) q <= #1 0; + else q <= #1 d; +endmodule + diff --git a/pipelined/dm/jtag.sv b/pipelined/dm/jtag.sv new file mode 100644 index 00000000..2810318f --- /dev/null +++ b/pipelined/dm/jtag.sv @@ -0,0 +1,182 @@ +/////////////////////////////////////////// +// jtag.sv +// +// Written: Juliette Reeder/James Stine +// Modified: +// +// Purpose: Main JTAG DM module +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module jtag #(parameter logic [31:0] IdcodeValue = 32'h00000001) + (clk, reset, testmode, + dmi_rst_o, dmi_req_o, dmi_req_valid_o, dmi_req_ready_i, + dmi_resp_i, dmi_resp_ready_o, dmi_resp_valid_i, + tck_i, tms_i, trst_i, tdi_i, tdo_o, tdo_oe_o); + + input logic clk; + input logic reset; + input logic testmode; + + output logic dmi_rst_o; + output logic [40:0] dmi_req_o; + output logic dmi_req_valid_o; + input logic dmi_req_ready_i; + + input logic dmi_resp_i; + output logic dmi_resp_ready_o; + input logic dmi_resp_valid_i; + + input logic tck_input; + input logic tms_input; + input logic trst_input; + input logic tdi_input; + output logic tdo_output; + output logic tdo_oe_output; + + typedef enum logic [1:0] {DMINoError = 2'h0, + DMIReservedError = 2'h1, + DMIOPFailed = 2'h2, + DMIBusy = 2'h3 + } dmi_error_e; + + dmi_error_e error_d, error_q; + + logic tck; + logic jtag_dmi_clear; + logic dmi_clear; + logic update; + logic capture; + logic shift; + logic tdi; + logic dmihardreset; + + logic dtmcs_select; + + // struct : 7 + IrLength + 32 = 39+IrLength + // logic [6:0] addr; + // dtm_op_e op; + // logic [31:0] data; + //} dmi_req_t; + // struct: 32 + 2 = 34 + // logic [31:0] data; + // logic [1:0] resp; + //} dmi_resp_t; + // struct: 7 + 32 + 2 = 41 + // logic [6:0] address; + // logic [31:0] data; + // logic [1:0] op; + //} dmi_t; + + logic dmi_select; + logic dmi_tdo; + logic [39+IrLength-1:0] dmi_req_t; + logic dmi_req_ready; + logic dmi_req_valid; + + logic [33:0] dmi_resp_t; + logic dmi_resp_valid; + logic dmi_resp_ready; + logic [40:0] dmi_t; + logic DTM_WRITE; + logic DTM_READ; + + typedef enum logic [2:0] {Idle, Read, WaitReadValid, Write, WaitWriteValid} state_e; + state_e state_d, state_q; + + logic [40:0] dr_d, dr_q; + logic [6:0] address_d, address_q; + logic [31:0] data_d, data_q; + + logic [40:0] dmi; + logic error_dmi_busy; + + // struct + // logic [31:18] zero1; + // logic dmihardreset; + // logic dmireset; + // logic zero0; + // logic [14:12] idle; + // logic [11:10] dmistat; + // logic [9:4] abits; + // logic [3:0] version; + //} dtmcs_t; + logic [31:0] dtmcs_d, dtmcs_q; + + assign dmi = {3'h0, dr_q}; + assign DTM_WRITE = 2'h2; + assign DTM_READ = 2'h1; + assign dmi_req = {address_q, data_q, (state_q == Write) ? DTM_WRITE : DTM_READ}; + assign dmi_resp_ready = 1'b1; + assign dmi_clear = jtag_dmi_clear || (dtmcs_select && update && dmihardreset); + + always_comb begin + dtmcs_d = dtmcs_q; + if (capture) begin + if (dtmcs_select) begin + // What? (fixme) + //dtmcs_d = '{1'b0, 1'b0, 1'b0, 1'b0, 3'd1, error_q, 6'd7, 4'd1}'; + end + end + if (shift) begin + if (dtmcs_select) + dtmcs_d = {tdi, 31'(dtmcs_q >> 1)}; + end + end + + // Insert new FSM + + // shift register + assign dmi_tdo = dr_q[0]; + always_comb begin + dr_d = dr_q; + if (dmi_clear) begin + dr_d = '0; + end else begin + if (capture) begin + if (dmi_select) begin + if (error_q == DMINoError && !error_dmi_busy) begin + dr_d = {address_q, data_q, DMINoError}; + // DMI was busy, report an error + end else if (error_q == DMIBusy || error_dmi_busy) begin + dr_d = {address_q, data_q, DMIBusy}; + end + end + end + + if (shift) begin + if (dmi_select) begin + dr_d = {tdi, dr_q[$bits(dr_q)-1:1]}; + end + end + end + end // always_comb + + flopr #(32) dtmcsreg (tck, trst, dtmcs_d, tdmcs_q); + + + + + +endmodule // jtag + diff --git a/pipelined/dm/jtag_fsm.sv b/pipelined/dm/jtag_fsm.sv new file mode 100644 index 00000000..ea71db5b --- /dev/null +++ b/pipelined/dm/jtag_fsm.sv @@ -0,0 +1,113 @@ +/////////////////////////////////////////// +// jtag_fsm.sv +// +// Written: Juliette Reeder/James Stine +// Modified: +// +// Purpose: FSM to control 1149.1 JTAG module +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module jtag_fsm (clk, reset, + dmi_req_ready, dmi_resp_valid, dmi_op, dmi_select, dmi_resp, + update, error, + address, data, dmi_req_valid, error_dmi_busy, error_dmi_op_failed); + + input logic clk; + input logic reset; + input logic dmi_req_ready; + input logic dmi_resp_valid; + input logic dmi_op; + input logic dmi_select; + input logic dmi_resp; + input logic update; + input logic error; + + output logic address; + output logic data; + output logic dmi_req_valid; + output logic error_dmi_busy; + output logic error_dmi_op_failed; + + typedef enum logic [2:0] {Idel, Read, WaitReadValid, Write, + WaitWriteValid} statetype; + + logic [1:0] DMINoError = 2'h0; + logic [1:0] DMIReservedError = 2'h1; + logic [1:0] DMIOPFailed = 2'h2; + logic [1:0] DMIBusy = 2'h3; + + logic [1:0] DTM_NOP = 2'h0; + logic [1:0] DTM_READ = 2'h1; + logic [1:0] DTM_WRITE = 2'h2; + + logic [1:0] DTM_SUCCESS = 2'h0; + logic [1:0] DTM_ERR = 2'h1; + logic [1:0] DTM_BUSY = 2'h2; + + statetype state, nextstate; + + // state register + always_ff @(posedge clk, negedge reset) + if (reset) begin + state <= Idle; + end + else begin + state <= nextstate; + end + + // next state logic + always_comb + case (state) + Idle: begin + if (dmi_select and update and (error == DMINoError) and (dtm_op == DTM_READ)) + nextstate = Read; + if (dmi_select and update and (error == DMINoError) and (dtm_op == DTM_WRITE)) + nextstate = Write; + else nextstate = Idle; + end + Read: begin + if (dmi_req_ready) + nextstate = WaitReadValid; + else + nextstate = Read; + end + WaitReadValid: begin + nextstate = Idle; + end + Write: begin + if (dmi_req_ready) + nextstate = WaitWriteValid; + else + nextstate = Write; + end + WaitWriteValid: begin + nextstate = Idle; + end + default: nextstate = Idle; + endcase // case (state) + + assign test_logic_reset = (state == testLogicReset); + + +endmodule // jtag_fsm diff --git a/pipelined/dm/jtag_tap.do b/pipelined/dm/jtag_tap.do new file mode 100644 index 00000000..951c706a --- /dev/null +++ b/pipelined/dm/jtag_tap.do @@ -0,0 +1,57 @@ +# Copyright 1991-2016 Mentor Graphics Corporation +# +# Modification by Oklahoma State University +# Use with Testbench +# James Stine, 2008 +# Go Cowboys!!!!!! +# +# All Rights Reserved. +# +# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION +# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION +# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. + +# Use this run.do file to run this example. +# Either bring up ModelSim and type the following at the "ModelSim>" prompt: +# do run.do +# or, to run from a shell, type the following at the shell prompt: +# vsim -do run.do -c +# (omit the "-c" to see the GUI while running from the shell) + +onbreak {resume} + +# create library +if [file exists work] { + vdel -all +} +vlib work + +# compile source files +vlog flopr.sv flopenr.sv tap_fsm.sv jtag_tap.sv jtag_tap_tb.sv + +# start and run simulation +vsim -voptargs=+acc work.stimulus + +view list +view wave + +-- display input and output signals as hexidecimal values +# Diplays All Signals recursively + add wave -hex -r /stimulus/* + +-- Set Wave Output Items +TreeUpdate [SetDefaultTree] +WaveRestoreZoom {0 ps} {75 ns} +configure wave -namecolwidth 250 +configure wave -valuecolwidth 300 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 + +-- Run the Simulation +run 1000 ns + + diff --git a/pipelined/dm/jtag_tap.sv b/pipelined/dm/jtag_tap.sv new file mode 100644 index 00000000..4ea76127 --- /dev/null +++ b/pipelined/dm/jtag_tap.sv @@ -0,0 +1,185 @@ +/////////////////////////////////////////// +// jtag_tap.sv +// +// Written: Juliette Reeder/James Stine +// Modified: +// +// Purpose: 1149.1 tap controller +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module jtag_tap #(parameter int unsigned IrLength = 5, + parameter logic [31:0] IdcodeValue = 32'h00000001) + (tck, tms, trst, tdi, tdo, + test_logic_reset, update_dr, capture_dr, shift_dr, + dtmcs_select, dtmcs_tdo, dmi_select, dmi_tdo, + tck_output, tdi_output, tdo_oe, testmode); + + input logic tck; // JTAG test clock pad + input logic tms; // JTAG test mode select pad + input logic trst; // JTAG test reset pad + input logic tdi; // JTAG test data input pad + output logic tdo; // JTAG test data output pad + + input logic dmi_tdo; + input logic dtmcs_tdo; + + output logic dmi_select; + output logic test_logic_reset; + output logic update_dr; + output logic shift_dr; + output logic capture_dr; + output logic dtmcs_select; + + output logic tck_output; + output logic tdi_output; + output logic tdo_oe; + input logic testmode; + + // DM : Table 6.1 (page 63) + typedef enum logic [IrLength-1:0] {BYPASS0 = 'h0, + IDCODE = 'h1, + DTMCSR = 'h10, + DMIACCESS = 'h11, + BYPASS1 = 'h1f + } ir_reg_e; + + logic capture_ir, shift_ir, update_ir; + logic [31:0] idcode_d, idcode_q; + logic idcode_select; + logic bypass_select; + logic bypass_d, bypass_q; + logic tdo_mux; + logic [IrLength-1:0] jtag_ir_shift_d; + logic [IrLength-1:0] jtag_ir_shift_q; + + // IR register -> this gets captured from shift register upon update_ir + ir_reg_e jtag_ir_d; + ir_reg_e jtag_ir_q; + + // For daisy chaining for multiple JTAG + assign tck_output = tck; + assign tdi_output = tdi; + + // FIXME: get rid of if-then-else + always_comb begin + + // not needed? + idcode_d = idcode_q; + bypass_d = bypass_q; + + if (shift_dr) begin + if (idcode_select) idcode_d = {tdi, 31'(idcode_q >> 1)}; + if (bypass_select) bypass_d = tdi; + end + + if (test_logic_reset) begin + // Bring all TAP state to the initial value. + idcode_d = IdcodeValue; + bypass_d = 1'b0; + end + end + + always_comb begin : p_jtag + + // ? + jtag_ir_shift_d = jtag_ir_shift_q; + jtag_ir_d = jtag_ir_q; + + // IR shift register + if (shift_ir) begin + jtag_ir_shift_d = {tdi, jtag_ir_shift_q[IrLength-1:1]}; + end + + // capture IR register + if (capture_ir) begin + jtag_ir_shift_d = IrLength'(4'b0101); + end + + // update IR register + if (update_ir) begin + jtag_ir_d = ir_reg_e'(jtag_ir_shift_q); + end + + if (test_logic_reset) begin + // Bring all TAP state to the initial value. + jtag_ir_shift_d = '0; + jtag_ir_d = IDCODE; + end + end + + // Data reg select + always_comb begin : p_data_reg_sel + dmi_select = 1'b0; + dtmcs_select = 1'b0; + idcode_select = 1'b0; + bypass_select = 1'b0; + unique case (jtag_ir_q) + BYPASS0: bypass_select = 1'b1; + IDCODE: idcode_select = 1'b1; + DTMCSR: dtmcs_select = 1'b1; + DMIACCESS: dmi_select = 1'b1; + BYPASS1: bypass_select = 1'b1; + default: bypass_select = 1'b1; + endcase + end + + always_comb begin : p_out_sel + // we are shifting out the IR register + if (shift_ir) begin + tdo_mux = jtag_ir_shift_q[0]; + // here we are shifting the DR register + end else begin + unique case (jtag_ir_q) + IDCODE: tdo_mux = idcode_q[0]; // Reading ID code + DTMCSR: tdo_mux = dtmcs_tdo; // Read from DTMCS TDO + DMIACCESS: tdo_mux = dmi_tdo; // Read from DMI TDO + default: tdo_mux = bypass_q; // BYPASS instruction + endcase + end + end // block: p_out_sel + + // Is there a better way of doing this? + always_ff @(posedge tck, negedge trst) begin + if (!trst) begin + jtag_ir_q <= IDCODE; + idcode_q <= IdcodeValue; + end else begin + jtag_ir_q <= jtag_ir_d; + idcode_q <= idcode_d; + end + end + + // Instatiate TAP controller + tap_fsm ieeetap (tck, trst, tms, + test_logic_reset, run_test_idle, select_dr_scan, capture_dr, shift_dr, + exit1_dr, pause_dr, exit2_dr, update_dr, select_ir_scan, capture_ir, + shift_ir, exit1_ir, pause_ir, exit2_ir, update_ir); + + // JTAG registers + flopr #(IrLength) jtag_ir_shiftreg (tck, trst, jtag_ir_shift_d, jtag_ir_shift_q); + flopr #(1) tdoreg (tck, trst, tdo_mux, tdo); + flopr #(1) tdooereg (tck, trst, (shift_ir | shift_dr), tdo_oe); + flopr #(1) bypassreg (tck, trst, bypass_d, bypass_q); + +endmodule // TAP diff --git a/pipelined/dm/jtag_tap_tb.sv b/pipelined/dm/jtag_tap_tb.sv new file mode 100644 index 00000000..42e75278 --- /dev/null +++ b/pipelined/dm/jtag_tap_tb.sv @@ -0,0 +1,101 @@ +`timescale 1ns / 1ns +module stimulus (); + + + logic tck; + logic tms; + logic trst; + logic tdi; + logic tdo; + logic dmi_tdo; + logic dtmcs_tdo; + logic dmi_select; + logic test_logic_reset; + logic update_dr; + logic shift_dr; + logic capture_dr; + logic dtmcs_select; + logic tck_output; + logic tdi_output; + logic tdo_oe; + logic testmode; + + integer handle3; + integer desc3; + integer j; + + // Instantiate DUTx + jtag_tap #(5, 32'h00000001) dut (tck, tms, trst, tdi, tdo, + test_logic_reset, update_dr, capture_dr, shift_dr, + dtmcs_select, dtmcs_tdo, dmi_select, dmi_tdo, + tck_output, tdi_output, tdo_oe, testmode); + + // Setup the clock to toggle every 1 time units + initial + begin + tck = 1'b1; + forever #5 tck = ~tck; + end + + initial + begin + // Gives output file name + handle3 = $fopen("tap.out"); + // Tells when to finish simulation + #1000 $finish; + end + + // Randomize tdi for fun + initial + begin + for (j=0; j < 256; j=j+1) + begin + // Put vectors before beginning of clk + @(posedge tck) + begin + tdi = $random; + end + end // for (j=0; j < 4; j=j+1) + end // initial begin + + + initial //play around with delays!!! + begin + #0 testmode = 1'b0; + #0 trst = 1'b1; + #41 trst = 1'b0; + #0 tms = 1'b1; + #10 tms = 1'b0; + #10 tms = 1'b0; + #10 tms = 1'b1; //testing DR + #10 tms = 1'b0; + #10 tms = 1'b1; + #10 tms = 1'b1; + #10 tms = 1'b0; + #10 tms = 1'b1; + #10 tms = 1'b1; + #10 tms = 1'b0; + #10 tms = 1'b0; + #10 tms = 1'b1; //testing IR + #10 tms = 1'b0; + #10 tms = 1'b1; + #10 tms = 1'b1; + #10 tms = 1'b1; + #10 tms = 1'b0; + #10 tms = 1'b1; + #10 tms = 1'b1; + #10 tms = 1'b1; //this point onwards is just random + #10 tms = 1'b1; + #10 tms = 1'b0; + #10 tms = 1'b1; + #10 tms = 1'b1; + #10 tms = 1'b0; + #10 tms = 1'b1; + #10 tms = 1'b0; + #10 tms = 1'b1; + #10 tms = 1'b0; + end + +endmodule // stimulus + + diff --git a/pipelined/dm/notes b/pipelined/dm/notes new file mode 100644 index 00000000..973f21f1 --- /dev/null +++ b/pipelined/dm/notes @@ -0,0 +1,6 @@ +Nice explaining video +https://youtu.be/PhaqHKyAvR4 + +The infamous eeBlog +https://youtu.be/TlWlLeC5BUs + diff --git a/pipelined/dm/rptr_empty.sv b/pipelined/dm/rptr_empty.sv new file mode 100644 index 00000000..68ec5cb6 --- /dev/null +++ b/pipelined/dm/rptr_empty.sv @@ -0,0 +1,37 @@ +module rptr_empty #(parameter ADDRSIZE = 4) + (rempty, raddr, rptr, rq2_wptr, rinc, rclk, rrst_n); + + input logic [ADDRSIZE:0] rq2_wptr; + input logic rinc; + input logic rclk; + input logic rrst_n; + output logic rempty; + output logic [ADDRSIZE-1:0] raddr; + output logic [ADDRSIZE :0] rptr; + + logic [ADDRSIZE:0] rbin; + logic [ADDRSIZE:0] rgraynext; + logic [ADDRSIZE:0] rbinnext; + + //------------------- + // GRAYSTYLE2 pointer + //------------------- + always @(posedge rclk or negedge rrst_n) + if (!rrst_n) {rbin, rptr} <= 0; + else {rbin, rptr} <= {rbinnext, rgraynext}; + + // Memory read-address pointer (okay to use binary to address memory) + assign raddr = rbin[ADDRSIZE-1:0]; + assign rbinnext = rbin + (rinc & ~rempty); + assign rgraynext = (rbinnext>>1) ^ rbinnext; + + //--------------------------------------------------------------- + // FIFO empty when the next rptr == synchronized wptr or on reset + //--------------------------------------------------------------- + assign rempty_val = (rgraynext == rq2_wptr); + + always @(posedge rclk or negedge rrst_n) + if (!rrst_n) rempty <= 1'b1; + else rempty <= rempty_val; + +endmodule // rptr_empty diff --git a/pipelined/dm/sync_r2w.sv b/pipelined/dm/sync_r2w.sv new file mode 100644 index 00000000..97ac299a --- /dev/null +++ b/pipelined/dm/sync_r2w.sv @@ -0,0 +1,16 @@ +module sync_r2w #(parameter ADDRSIZE = 4) + (wq2_rptr, rptr, wclk, wrst_n); + + input logic [ADDRSIZE:0] rptr; + input logic wclk; + input logic wrst_n; + + output logic [ADDRSIZE:0] wq2_rptr; + + logic [ADDRSIZE:0] wq1_rptr; + + always @(posedge wclk or negedge wrst_n) + if (!wrst_n) {wq2_rptr,wq1_rptr} <= 0; + else {wq2_rptr,wq1_rptr} <= {wq1_rptr,rptr}; + +endmodule // sync_r2w diff --git a/pipelined/dm/sync_w2r.sv b/pipelined/dm/sync_w2r.sv new file mode 100644 index 00000000..f186968b --- /dev/null +++ b/pipelined/dm/sync_w2r.sv @@ -0,0 +1,16 @@ +module sync_w2r #(parameter ADDRSIZE = 4) + (rq2_wptr, wptr, rclk, rrst_n); + + input logic [ADDRSIZE:0] wptr; + input logic rclk; + input logic rrst_n; + + output logic [ADDRSIZE:0] rq2_wptr; + + logic [ADDRSIZE:0] rq1_wptr; + + always @(posedge rclk or negedge rrst_n) + if (!rrst_n) {rq2_wptr,rq1_wptr} <= 0; + else {rq2_wptr,rq1_wptr} <= {rq1_wptr,wptr}; + +endmodule // sync_w2r diff --git a/pipelined/dm/tap.do b/pipelined/dm/tap.do new file mode 100644 index 00000000..02e47340 --- /dev/null +++ b/pipelined/dm/tap.do @@ -0,0 +1,81 @@ +# Copyright 1991-2016 Mentor Graphics Corporation +# +# Modification by Oklahoma State University +# Use with Testbench +# James Stine, 2008 +# Go Cowboys!!!!!! +# +# All Rights Reserved. +# +# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION +# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION +# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. + +# Use this run.do file to run this example. +# Either bring up ModelSim and type the following at the "ModelSim>" prompt: +# do run.do +# or, to run from a shell, type the following at the shell prompt: +# vsim -do run.do -c +# (omit the "-c" to see the GUI while running from the shell) + +onbreak {resume} + +# create library +if [file exists work] { + vdel -all +} +vlib work + +# compile source files +vlog tap_fsm.sv tap_tb.sv + +# start and run simulation +vsim -voptargs=+acc work.stimulus + +view list +view wave + +-- display input and output signals as hexidecimal values +# Diplays All Signals recursively +# add wave -hex -r /stimulus/* +add wave -noupdate -divider -height 32 "TAP" +add wave -hex /stimulus/dut/reset +add wave -hex /stimulus/dut/clk +add wave -hex /stimulus/dut/tms +add wave -noupdate -divider -height 32 "State for TAP" +add wave -hex /stimulus/dut/state +add wave -hex /stimulus/dut/nextstate +add wave -noupdate -divider -height 32 "Outputs" +add wave -hex /stimulus/dut/test_logic_reset; +add wave -hex /stimulus/dut/run_test_idle; +add wave -hex /stimulus/dut/select_dr_scan; +add wave -hex /stimulus/dut/capture_dr; +add wave -hex /stimulus/dut/shift_dr; +add wave -hex /stimulus/dut/exit1_dr; +add wave -hex /stimulus/dut/pause_dr; +add wave -hex /stimulus/dut/exit2_dr; +add wave -hex /stimulus/dut/update_dr; +add wave -hex /stimulus/dut/select_ir_scan; +add wave -hex /stimulus/dut/capture_ir; +add wave -hex /stimulus/dut/shift_ir; +add wave -hex /stimulus/dut/exit1_ir; +add wave -hex /stimulus/dut/pause_ir; +add wave -hex /stimulus/dut/exit2_ir; +add wave -hex /stimulus/dut/update_ir; + +-- Set Wave Output Items +TreeUpdate [SetDefaultTree] +WaveRestoreZoom {0 ps} {75 ns} +configure wave -namecolwidth 250 +configure wave -valuecolwidth 300 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 + +-- Run the Simulation +run 1000 ns + + diff --git a/pipelined/dm/tap.out b/pipelined/dm/tap.out new file mode 100644 index 00000000..e69de29b diff --git a/pipelined/dm/tap_fsm.sv b/pipelined/dm/tap_fsm.sv new file mode 100644 index 00000000..68699e99 --- /dev/null +++ b/pipelined/dm/tap_fsm.sv @@ -0,0 +1,161 @@ +/////////////////////////////////////////// +// tap_fsm.sv +// +// Written: Juliette Reeder/James Stine +// Modified: +// +// Purpose: 1149.1 tap controller +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module tap_fsm (clk, reset, tms, + test_logic_reset, run_test_idle, select_dr_scan, capture_dr, shift_dr, + exit1_dr, pause_dr, exit2_dr, update_dr, select_ir_scan, capture_ir, + shift_ir, exit1_ir, pause_ir, exit2_ir, update_ir); + + input logic clk; + input logic reset; + input logic tms; + + output logic test_logic_reset; + output logic run_test_idle; + output logic select_dr_scan; + output logic capture_dr; + output logic shift_dr; + output logic exit1_dr; + output logic pause_dr; + output logic exit2_dr; + output logic update_dr; + output logic select_ir_scan; + output logic capture_ir; + output logic shift_ir; + output logic exit1_ir; + output logic pause_ir; + output logic exit2_ir; + output logic update_ir; + + typedef enum logic [3:0] {testLogicReset, runTestIdle, + selectDRScan, captureDR, shiftDR, + exit1DR, pauseDR, exit2DR, updateDR, + selectIRScan, captureIR, shiftIR, + exit1IR, pauseIR, exit2IR, updateIR} statetype; + + statetype state, nextstate; + + // state register + always_ff @(posedge clk, negedge reset) + if (reset) begin + state <= runTestIdle; + end + else begin + state <= nextstate; + end + + // next state logic + always_comb + case (state) + testLogicReset: begin + if (tms) nextstate = testLogicReset; + else nextstate = runTestIdle; + end + runTestIdle: begin + if (tms) nextstate = selectDRScan; + else nextstate = runTestIdle; + end + selectDRScan: begin + if (tms) nextstate = selectIRScan; + else nextstate = captureDR; + end + captureDR: begin + if (tms) nextstate = exit1DR; + else nextstate = shiftDR; + end + shiftDR: begin + if (tms) nextstate = exit1DR; + else nextstate = shiftDR; + end + exit1DR: begin + if (tms) nextstate = updateDR; + else nextstate = pauseDR; + end + pauseDR: begin + if (tms) nextstate = exit2DR; + else nextstate = pauseDR; + end + exit2DR: begin + if (tms) nextstate = updateDR; + else nextstate = shiftDR; + end + updateDR: begin + if (tms) nextstate = selectDRScan; + else nextstate = runTestIdle; + end + selectIRScan: begin + if (tms) nextstate = testLogicReset; + else nextstate = captureIR; + end + captureIR: begin + if (tms) nextstate = exit1IR; + else nextstate = shiftIR; + end + shiftIR: begin + if (tms) nextstate = exit1IR; + else nextstate = shiftIR; + end + exit1IR: begin + if (tms) nextstate = updateIR; + else nextstate = pauseIR; + end + pauseIR: begin + if (tms) nextstate = exit2IR; + else nextstate = pauseIR; + end + exit2IR: begin + if (tms) nextstate = updateIR; + else nextstate = shiftIR; + end + updateIR: begin + if (tms) nextstate = selectDRScan; + else nextstate = runTestIdle; + end + default: nextstate = testLogicReset; + endcase // case (state) + + assign test_logic_reset = (state == testLogicReset); + assign run_test_idle = (state == runTestIdle); + assign select_dr_scan = (state == selectDRScan); + assign capture_dr = (state == captureDR); + assign shift_dr = (state == captureDR); + assign exit1_dr = (state == exit1DR); + assign pause_dr = (state == pauseDR); + assign exit2_dr = (state == exit2DR); + assign update_dr = (state == updateDR); + assign select_ir_scan = (state == selectIRScan); + assign capture_ir = (state == captureIR); + assign shift_ir = (state == shiftIR); + assign exit1_ir = (state == exit1IR); + assign pause_ir = (state == pauseIR); + assign exit2_ir = (state == exit2IR); + assign update_ir = (state == updateIR); + +endmodule // tap_fsm diff --git a/pipelined/dm/tap_tb.sv b/pipelined/dm/tap_tb.sv new file mode 100644 index 00000000..4540cdaa --- /dev/null +++ b/pipelined/dm/tap_tb.sv @@ -0,0 +1,86 @@ +`timescale 1ns / 1ns +module stimulus (); + + logic clk; + logic tms; + logic reset; + + logic test_logic_reset; + logic run_test_idle; + logic select_dr_scan; + logic capture_dr; + logic shift_dr; + logic exit1_dr; + logic pause_dr; + logic exit2_dr; + logic update_dr; + logic select_ir_scan; + logic capture_ir; + logic shift_ir; + logic exit1_ir; + logic pause_ir; + logic exit2_ir; + logic update_ir; + + integer handle3; + integer desc3; + + // Instantiate DUTx + tap_fsm dut (clk, reset, tms, + test_logic_reset, run_test_idle, select_dr_scan, capture_dr, shift_dr, + exit1_dr, pause_dr, exit2_dr, update_dr, select_ir_scan, capture_ir, + shift_ir, exit1_ir, pause_ir, exit2_ir, update_ir); + + // Setup the clock to toggle every 1 time units + initial + begin + clk = 1'b1; + forever #5 clk = ~clk; + end + + initial + begin + // Gives output file name + handle3 = $fopen("tap.out"); + // Tells when to finish simulation + #1000 $finish; + end + + initial //play around with delays!!! + begin + #0 reset = 1'b1; + #41 reset = 1'b0; + #0 tms = 1'b1; + #10 tms = 1'b0; + #10 tms = 1'b0; + #10 tms = 1'b1; //testing DR + #10 tms = 1'b0; + #10 tms = 1'b1; + #10 tms = 1'b1; + #10 tms = 1'b0; + #10 tms = 1'b1; + #10 tms = 1'b1; + #10 tms = 1'b0; + #10 tms = 1'b0; + #10 tms = 1'b1; //testing IR + #10 tms = 1'b0; + #10 tms = 1'b1; + #10 tms = 1'b1; + #10 tms = 1'b1; + #10 tms = 1'b0; + #10 tms = 1'b1; + #10 tms = 1'b1; + #10 tms = 1'b1; //this point onwards is just random + #10 tms = 1'b1; + #10 tms = 1'b0; + #10 tms = 1'b1; + #10 tms = 1'b1; + #10 tms = 1'b0; + #10 tms = 1'b1; + #10 tms = 1'b0; + #10 tms = 1'b1; + #10 tms = 1'b0; + end + +endmodule // TAP_tb + diff --git a/pipelined/dm/tb.sv b/pipelined/dm/tb.sv new file mode 100755 index 00000000..9d5e0600 --- /dev/null +++ b/pipelined/dm/tb.sv @@ -0,0 +1,81 @@ +// +// File name : tb.v +// Title : stimulus +// project : ECEN3233 +// Library : test +// Author(s) : James E. Stine, Jr. +// Purpose : definition of modules for testbench +// notes : +// +// Copyright Oklahoma State University +// + +module stimulus(); + + logic clk; + + // Declare variables for stimulating input + logic [31:0] rdata; + logic wfull; + logic rempty; + + logic [31:0] wdata; + logic winc, wclk, wrst_n; + logic rinc, rclk, rrst_n; + + logic [31:0] vectornum; + logic [31:0] errors; + + integer handle3; + integer desc3; + integer i; + integer j; + + // Instantiate the design block counter + fifo #(32,4) dut (rdata, wfull, rempty, + wdata, winc, clk, wrst_n, + rinc, clk, rrst_n); + + // Setup the clock to toggle every 1 time units + initial + begin + clk = 1'b1; + forever #5 clk = ~clk; + end + + initial + begin + // Gives output file name + handle3 = $fopen("test.out"); + rrst_n = 1'b0; + wrst_n = 1'b0; + end + + initial + begin + #43 rrst_n = 1'b1; + #0 wrst_n = 1'b1; + for (j=0; j < 16; j=j+1) + begin + // Put vectors before beginning of clk + @(posedge clk) + begin + wdata = $random; + winc = $random; + end + @(negedge clk) + begin + vectornum = vectornum + 1; + end // @(negedge clk) + end // for (i=0; i < 16; i=i+1) + $display("%d tests completed with %d errors", vectornum, errors); + $finish; + end // initial begin + + +endmodule // stimulus + + + + + diff --git a/pipelined/dm/wptr_full.sv b/pipelined/dm/wptr_full.sv new file mode 100644 index 00000000..a6f4fdf9 --- /dev/null +++ b/pipelined/dm/wptr_full.sv @@ -0,0 +1,44 @@ +module wptr_full #(parameter ADDRSIZE = 4) + (wfull, waddr, wptr, wq2_rptr, winc, wclk, wrst_n); + + input logic [ADDRSIZE :0] wq2_rptr; + input logic winc; + input logic wclk; + input logic wrst_n; + + output logic wfull; + output logic [ADDRSIZE-1:0] waddr; + output logic [ADDRSIZE:0] wptr; + + logic [ADDRSIZE:0] wbin; + logic [ADDRSIZE:0] wgraynext; + logic [ADDRSIZE:0] wbinnext; + + // GRAYSTYLE2 pointer + always @(posedge wclk or negedge wrst_n) + if (!wrst_n) {wbin, wptr} <= 0; + else {wbin, wptr} <= {wbinnext, wgraynext}; + + // Memory write-address pointer (okay to use binary to address memory) + assign waddr = wbin[ADDRSIZE-1:0]; + assign wbinnext = wbin + (winc & ~wfull); + assign wgraynext = (wbinnext>>1) ^ wbinnext; + + //------------------------------------------------------------------ + // Simplified version of the three necessary full-tests: + // assign wfull_val=((wgnext[ADDRSIZE] !=wq2_rptr[ADDRSIZE] ) && + // (wgnext[ADDRSIZE-1] !=wq2_rptr[ADDRSIZE-1]) && + // (wgnext[ADDRSIZE-2:0]==wq2_rptr[ADDRSIZE-2:0])); + //------------------------------------------------------------------ + assign wfull_val = (wgraynext=={~wq2_rptr[ADDRSIZE:ADDRSIZE-1], + wq2_rptr[ADDRSIZE-2:0]}); + + always @(posedge wclk or negedge wrst_n) + if (!wrst_n) + wfull <= 1'b0; + else + wfull <= wfull_val; + +endmodule // wptr_full + +