From 800fdeb7ad6156651d5f3a5a5415dd2df7970826 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Fri, 31 Mar 2023 10:54:03 -0700
Subject: [PATCH] Added SSTC support to imperas.ic and wallyTracer.  Fixes many
 of the privileged tests

---
 sim/imperas.ic                  | 10 +++++++++-
 testbench/common/wallyTracer.sv |  6 ++++++
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/sim/imperas.ic b/sim/imperas.ic
index fe822039..beadba6f 100644
--- a/sim/imperas.ic
+++ b/sim/imperas.ic
@@ -10,10 +10,15 @@
 --override cpu/mimpid=0x100
 --override cpu/misa_Extensions_mask=0x0
 
-# THIS NEEDS FIXING to 16
 --override cpu/PMP_registers=16
 --override cpu/PMP_undefined=T
 
+# Wally-specific non-default configuraiton
+--override refRoot/cpu/Sstc=T 
+# Zba doesn't seem to exist - Lee is finding the name
+#--override refRoot/cpu/Zba=T 
+
+
 # Illegal instruction should not contain the bit pattern
 # illegal pmp read contained this
 # --override cpu/tval_ii_code=F
@@ -47,8 +52,11 @@
 #-override  refRoot/cpu/cv/cover=basic
 #-override  refRoot/cpu/cv/extensions=RV32I
 
+
+
 # Add Imperas simulator application instruction tracing
 --override cpu/show_c_prefix=T
+
 --trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange --traceafter 800000
 
 # Exceptions and pagetables debug
diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv
index 4df1956a..221c8d7f 100644
--- a/testbench/common/wallyTracer.sv
+++ b/testbench/common/wallyTracer.sv
@@ -162,6 +162,7 @@ module wallyTracer(rvviTrace rvvi);
 	  CSRArray[12'h143] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW;
 	  CSRArray[12'h142] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW;
 	  CSRArray[12'h144] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW & & 12'h222 & testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW;
+	  CSRArray[12'h14D] = testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW;
 	  // user CSRs
 	  CSRArray[12'h001] = testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW;
 	  CSRArray[12'h002] = testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW;
@@ -211,6 +212,7 @@ module wallyTracer(rvviTrace rvvi);
 	  CSRArray[12'h143] = CSRArrayOld[12'h143];
 	  CSRArray[12'h142] = CSRArrayOld[12'h142];
 	  CSRArray[12'h144] = CSRArrayOld[12'h144];
+	  CSRArray[12'h14D] = CSRArrayOld[12'h14D];
 	  // user CSRs
 	  CSRArray[12'h001] = CSRArrayOld[12'h001];
 	  CSRArray[12'h002] = CSRArrayOld[12'h002];
@@ -329,6 +331,7 @@ module wallyTracer(rvviTrace rvvi);
     CSRArrayOld[12'h143] = CSRArray[12'h143];
     CSRArrayOld[12'h142] = CSRArray[12'h142];
     CSRArrayOld[12'h144] = CSRArray[12'h144];
+    CSRArrayOld[12'h14D] = CSRArray[12'h14D];
     // user CSRs
     CSRArrayOld[12'h001] = CSRArray[12'h001];
     CSRArrayOld[12'h002] = CSRArray[12'h002];
@@ -376,6 +379,7 @@ module wallyTracer(rvviTrace rvvi);
   assign #2 CSR_W[12'h143] = (CSRArrayOld[12'h143] != CSRArray[12'h143]) ? 1 : 0;
   assign #2 CSR_W[12'h142] = (CSRArrayOld[12'h142] != CSRArray[12'h142]) ? 1 : 0;
   assign #2 CSR_W[12'h144] = (CSRArrayOld[12'h144] != CSRArray[12'h144]) ? 1 : 0;
+  assign #2 CSR_W[12'h14D] = (CSRArrayOld[12'h14D] != CSRArray[12'h14D]) ? 1 : 0;
   assign #2 CSR_W[12'h001] = (CSRArrayOld[12'h001] != CSRArray[12'h001]) ? 1 : 0;
   assign #2 CSR_W[12'h002] = (CSRArrayOld[12'h002] != CSRArray[12'h002]) ? 1 : 0;
   assign #2 CSR_W[12'h003] = (CSRArrayOld[12'h003] != CSRArray[12'h003]) ? 1 : 0;
@@ -412,6 +416,7 @@ module wallyTracer(rvviTrace rvvi);
   assign rvvi.csr_wb[0][0][12'h143] = CSR_W[12'h143];
   assign rvvi.csr_wb[0][0][12'h142] = CSR_W[12'h142];
   assign rvvi.csr_wb[0][0][12'h144] = CSR_W[12'h144];
+  assign rvvi.csr_wb[0][0][12'h14D] = CSR_W[12'h14D];
   assign rvvi.csr_wb[0][0][12'h001] = CSR_W[12'h001];
   assign rvvi.csr_wb[0][0][12'h002] = CSR_W[12'h002];
   assign rvvi.csr_wb[0][0][12'h003] = CSR_W[12'h003];
@@ -448,6 +453,7 @@ module wallyTracer(rvviTrace rvvi);
   assign rvvi.csr[0][0][12'h143]    = CSRArray[12'h143];
   assign rvvi.csr[0][0][12'h142]    = CSRArray[12'h142];
   assign rvvi.csr[0][0][12'h144]    = CSRArray[12'h144];
+  assign rvvi.csr[0][0][12'h14D]    = CSRArray[12'h14D];
   assign rvvi.csr[0][0][12'h001]    = CSRArray[12'h001];
   assign rvvi.csr[0][0][12'h002]    = CSRArray[12'h002];
   assign rvvi.csr[0][0][12'h003]    = CSRArray[12'h003];