From cbb5e4440ffc62e3bd4d4df78a0917230d9cc598 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 3 Dec 2021 10:05:13 -0600 Subject: [PATCH 1/5] Improved FPGA makefile and fixed timing constraints in clock converter. --- fpga/generator/Makefile | 18 +++++++++++++++--- fpga/generator/xlnx_axi_clock_converter.tcl | 8 +++++++- 2 files changed, 22 insertions(+), 4 deletions(-) diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile index d397c5ed..c65e522f 100644 --- a/fpga/generator/Makefile +++ b/fpga/generator/Makefile @@ -1,7 +1,11 @@ dst := IP +all: FPGA -all: $(dst)/xlnx_proc_sys_reset.log \ +FPGA: IP + vivado -mode batch -source wally.tcl | tee wally.log + +IP: $(dst)/xlnx_proc_sys_reset.log \ $(dst)/xlnx_ddr4.log \ $(dst)/xlnx_axi_clock_converter.log \ $(dst)/xlnx_ahblite_axi_bridge.log @@ -11,5 +15,13 @@ $(dst)/%.log: %.tcl cd IP;\ vivado -mode batch -source ../$*.tcl | tee $*.log -clean: - rm -rf IP vivado.jou vivado.log +cleanIP: + rm -rf IP + +cleanLogs: + rm -rf *.jou *.log + +cleanFPGA: + rm -rf WallyFPGA.* reports sim .Xil + +cleanAll: cleanIP cleanLogs cleanFPGA diff --git a/fpga/generator/xlnx_axi_clock_converter.tcl b/fpga/generator/xlnx_axi_clock_converter.tcl index c63d8761..9e581c29 100644 --- a/fpga/generator/xlnx_axi_clock_converter.tcl +++ b/fpga/generator/xlnx_axi_clock_converter.tcl @@ -11,7 +11,13 @@ set_property board_part $boardName [current_project] create_ip -name axi_clock_converter -vendor xilinx.com -library ip -module_name $ipName -set_property -dict [list CONFIG.ACLK_ASYNC {1} CONFIG.PROTOCOL {AXI4} CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {64} CONFIG.ID_WIDTH {4}] [get_ips $ipName] +set_property -dict [list CONFIG.ACLK_ASYNC {1} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.DATA_WIDTH {64} \ + CONFIG.ID_WIDTH {4} \ + CONFIG.MI_CLK.FREQ_HZ {208333333} \ + CONFIG.SI_CLK.FREQ_HZ {10000000}] [get_ips $ipName] generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] From 546f7fb4c2748eb1b3999f25a33dee14f4054f32 Mon Sep 17 00:00:00 2001 From: Skylar Litz Date: Fri, 3 Dec 2021 12:32:38 -0800 Subject: [PATCH 2/5] fix some interrupt timing bugs --- wally-pipelined/testbench/testbench-linux.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv index 2aaacee8..50559b9d 100644 --- a/wally-pipelined/testbench/testbench-linux.sv +++ b/wally-pipelined/testbench/testbench-linux.sv @@ -430,7 +430,7 @@ module testbench(); NextMIPexpected = ExpectedCSRArrayValueE[NumCSRE]; \ end \ if(ExpectedCSRArrayE[NumCSRE].substr(0,3) == "mepc") begin \ - $display("hello! we are here."); \ + // $display("hello! we are here."); \ MepcExpected = ExpectedCSRArrayValueE[NumCSRE]; \ $display("%tns: MepcExpected: %x",$time,MepcExpected); \ end \ @@ -469,7 +469,7 @@ module testbench(); // $display("%tns: ExpectedPCM %x",$time,ExpectedPCM); // $display("%tns: ExpectedPCE %x",$time,ExpectedPCE); // $display("%tns: ExpectedPCW %x",$time,ExpectedPCW); - if((ExpectedPCE != MepcExpected) & ((MepcExpected - ExpectedPCE) * (MepcExpected - ExpectedPCE) <= 16)) begin + if((ExpectedPCE != MepcExpected) & ((MepcExpected - ExpectedPCE) * (MepcExpected - ExpectedPCE) <= 200) || ~dut.hart.ieu.c.InstrValidM) begin RequestDelayedMIP <= 1; $display("%tns: Requesting Delayed MIP. Current MEPC value is %x",$time,MepcExpected); end else begin // update MIP immediately From 5b4ff4526efd9d684e5c4d2e5dae90481fe0c737 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 3 Dec 2021 17:47:54 -0600 Subject: [PATCH 3/5] Fixed a bunch of fpga issues. --- fpga/constraints/constraints.xdc | 3 +- fpga/generator/wally.tcl | 75 ++++++++++++++++++++++++++------ 2 files changed, 64 insertions(+), 14 deletions(-) diff --git a/fpga/constraints/constraints.xdc b/fpga/constraints/constraints.xdc index 51bc8722..9059dc7f 100644 --- a/fpga/constraints/constraints.xdc +++ b/fpga/constraints/constraints.xdc @@ -17,7 +17,8 @@ #create_generated_clock -name mmcm_clkout1 -source [get_pins xlnx_ddr4_c0/c0_sys_clk_p] -edges {1 2 3} -edge_shift {0.000 48.000 96.000} [get_pins xlnx_ddr4_c0/addn_ui_clkout1] -create_generated_clock -name mmcm_clkout1 xlnx_ddr4_c0/addn_ui_clkout1 +#create_generated_clock -name mmcm_clkout1 xlnx_ddr4_c0/addn_ui_clkout1 +#create_generated_clock -name mmcm_clkout1 mmcm_clkout1 create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 [get_pins wallypipelinedsoc/uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O] diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index 405ba439..affeb45b 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -21,50 +21,99 @@ set_property include_dirs {../../wally-pipelined/config/fpga ../../wally-pipelin # contrainsts generated by the IP blocks add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_0/bd_1ba7_microblaze_I_0.xdc +set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_0/bd_1ba7_microblaze_I_0.xdc] + +add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0_board.xdc +set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0_board.xdc] + add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0.xdc +set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0.xdc] + add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_2/bd_1ba7_ilmb_0.xdc +set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_2/bd_1ba7_ilmb_0.xdc] + add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_3/bd_1ba7_dlmb_0.xdc -add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/par/xlnx_ddr4.xdc +set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_3/bd_1ba7_dlmb_0.xdc] + +add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_10/bd_1ba7_iomodule_0_0_board.xdc +set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_10/bd_1ba7_iomodule_0_0_board.xdc] + +add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_board.xdc +set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_board.xdc] + +add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_board.xdc +set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_board.xdc] + +add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset.xdc +set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset.xdc] + +add_files -fileset constrs_1 -norecurse ../constraints/constraints.xdc +set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints.xdc] + add_files -fileset constrs_1 -norecurse IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_clocks.xdc +set_property PROCESSING_ORDER LATE [get_files IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_clocks.xdc] + +add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/xlnx_ddr4_board.xdc +set_property PROCESSING_ORDER LATE [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/xlnx_ddr4_board.xdc] + +add_files -fileset constrs_1 -norecurse IP/xlnx_ahblite_axi_bridge.gen/sources_1/ip/xlnx_ahblite_axi_bridge/xlnx_ahblite_axi_bridge_ooc.xdc +set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ahblite_axi_bridge.gen/sources_1/ip/xlnx_ahblite_axi_bridge/xlnx_ahblite_axi_bridge_ooc.xdc] + + +add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/par/xlnx_ddr4.xdc +set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/par/xlnx_ddr4.xdc] + + +add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_1/par/xlnx_ddr4_phy_ooc.xdc -#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_1/par/xlnx_ddr4_phy_ooc.xdc +add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_ooc.xdc + +add_files -fileset constrs_1 -norecurse IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_ooc.xdc + + +add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_ooc.xdc + -#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_10/bd_1ba7_iomodule_0_0_board.xdc -#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0_board.xdc #add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_0/bd_1ba7_microblaze_I_0_ooc_debug.xdc - #add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_9/bd_1ba7_second_lmb_bram_I_0_ooc.xdc #add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_6/bd_1ba7_lmb_bram_I_0_ooc.xdc #add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/bd_1ba7_ooc.xdc -#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_board.xdc -#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_ooc.xdc -#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/xlnx_ddr4_board.xdc #add_files -fileset constrs_1 -norecurse IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_ooc.xdc #add_files -fileset constrs_1 -norecurse IP/xlnx_ahblite_axi_bridge.runs/xlnx_ahblite_axi_bridge_synth_1/dont_touch.xdc -#add_files -fileset constrs_1 -norecurse IP/xlnx_ahblite_axi_bridge.gen/sources_1/ip/xlnx_ahblite_axi_bridge/xlnx_ahblite_axi_bridge_ooc.xdc + #add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.runs/xlnx_proc_sys_reset_synth_1/dont_touch.xdc -#add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_ooc.xdc -#add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset.xdc -#add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_board.xdc + + + #add_files -fileset constrs_1 -norecurse IP/xlnx_axi_clock_converter.runs/xlnx_axi_clock_converter_synth_1/.Xil/xlnx_axi_clock_converter_propImpl.xdc #add_files -fileset constrs_1 -norecurse IP/xlnx_axi_clock_converter.runs/xlnx_axi_clock_converter_synth_1/dont_touch.xdc #add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.runs/xlnx_ddr4_synth_1/.Xil/xlnx_ddr4_propImpl.xdc #add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.runs/xlnx_ddr4_synth_1/dont_touch.xdc # constraints for wally top level -add_files -fileset constrs_1 -norecurse ../constraints/constraints.xdc # define top level set_property top fpgaTop [current_fileset] +set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_ooc.xdc] +set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_1/par/xlnx_ddr4_phy_ooc.xdc] +set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_ooc.xdc] +set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_ooc.xdc] + + update_compile_order -fileset sources_1 +update_compile_order -fileset constrs_1 +# This is important as the ddr4 IP contains the generate clock constraint which the user constraints depend on. +report_compile_order -constraints > reports/compile_order.rpt # this is elaboration not synthesis. synth_design -rtl -name rtl_1 +report_clocks -file reports/clocks.rpt + # this does synthesis? wtf? launch_runs synth_1 -jobs 4 From 955ddcfbe1739d236440ff296b601a351330bcd7 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 3 Dec 2021 17:55:36 -0600 Subject: [PATCH 4/5] Fixed bug in the top level of fpga verilog. --- fpga/src/fpgaTop.v | 1 - 1 file changed, 1 deletion(-) diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v index eb78e89d..d9751c9c 100644 --- a/fpga/src/fpgaTop.v +++ b/fpga/src/fpgaTop.v @@ -44,7 +44,6 @@ module fpgaTop output calib, output cpu_reset, - output ddr4_sdram_c1_062, output ahblite_resetn, output [16 : 0] c0_ddr4_adr, From 64f33161bc5a681fc902245b684cc1708bce492b Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 4 Dec 2021 20:25:33 -0800 Subject: [PATCH 5/5] Added files to repo --- .gitignore | 1 + Makefile | 35 ++++-------- wally-pipelined/README.txt | 50 ++++++++++++++++++ .../linux-testgen/linux-testvectors/all.txt | 1 + .../linux-testvectors/bootmem.txt | 1 + .../linux-testvectors/checkpoint8500000 | 1 + .../linux-testgen/linux-testvectors/ram.txt | 1 + .../linux-testvectors/vmlinux.objdump | 1 + .../linux-testvectors/vmlinux.objdump.addr | 1 + .../linux-testvectors/vmlinux.objdump.lab | 1 + wally-pipelined/srt/sqrttestgen | Bin 0 -> 13168 bytes wally-pipelined/srt/testgen | Bin 0 -> 13088 bytes wally-setup.sh | 26 +++++++++ 13 files changed, 95 insertions(+), 24 deletions(-) create mode 100644 wally-pipelined/README.txt create mode 120000 wally-pipelined/linux-testgen/linux-testvectors/all.txt create mode 120000 wally-pipelined/linux-testgen/linux-testvectors/bootmem.txt create mode 120000 wally-pipelined/linux-testgen/linux-testvectors/checkpoint8500000 create mode 120000 wally-pipelined/linux-testgen/linux-testvectors/ram.txt create mode 120000 wally-pipelined/linux-testgen/linux-testvectors/vmlinux.objdump create mode 120000 wally-pipelined/linux-testgen/linux-testvectors/vmlinux.objdump.addr create mode 120000 wally-pipelined/linux-testgen/linux-testvectors/vmlinux.objdump.lab create mode 100755 wally-pipelined/srt/sqrttestgen create mode 100755 wally-pipelined/srt/testgen create mode 100644 wally-setup.sh diff --git a/.gitignore b/.gitignore index 2542dd88..1f1454f9 100644 --- a/.gitignore +++ b/.gitignore @@ -21,6 +21,7 @@ wlft* /imperas-riscv-tests/logs *.o *.d +*.vstf testsBP/*/*/*.elf* testsBP/*/OBJ/* testsBP/*/*.a diff --git a/Makefile b/Makefile index a8ca63fe..d715d72d 100644 --- a/Makefile +++ b/Makefile @@ -1,31 +1,18 @@ -#make all: submodules other -#make all: submodules other -#submodules: addins/riscv-isa-sim addins/riscv-arch-test -# git pull --recurse-submodules -# -#other: make all: # move these parts into compiling archtest separtately - cp -r addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/I addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/F - cp -r addins/riscv-isa-sim/arch_test_target/spike/device/rv64i_m/I addins/riscv-isa-sim/arch_test_target/spike/device/rv64i_m/D -<<<<<<< HEAD -#why cat - cat addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/F/Makefile.include -======= ->>>>>>> 29f2a1c5479d7a80debdb1ac337fcda628cc57a3 - sed -i 's/--isa=rv32i /--isa=32if/' addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/F/Makefile.include - sed -i 's/--isa=rv64i /--isa=64if/' addins/riscv-isa-sim/arch_test_target/spike/device/rv64i_m/D/Makefile.include - if [ -d "addins/riscv-isa-sim/build" ]; then echo "Build exists"; else mkdir addins/riscv-isa-sim/build; fi - cd addins/riscv-isa-sim/build; ../configure --prefix=/cad/riscv/gcc/bin - make -C addins/riscv-isa-sim/build -# does sudo work? - - sudo make install -C addins/riscv-isa-sim/build - - cp addins/riscv-isa-sim/arch_test_target/spike/Makefile.include addins/riscv-arch-test/ +# cp -r addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/I addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/F +# cp -r addins/riscv-isa-sim/arch_test_target/spike/device/rv64i_m/I addins/riscv-isa-sim/arch_test_target/spike/device/rv64i_m/D +# sed -i 's/--isa=rv32i /--isa=32if/' addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/F/Makefile.include +# sed -i 's/--isa=rv64i /--isa=64id/' addins/riscv-isa-sim/arch_test_target/spike/device/rv64i_m/D/Makefile.include +# if [ -d "addins/riscv-isa-sim/build" ]; then echo "Build exists"; else mkdir addins/riscv-isa-sim/build; fi +# cd addins/riscv-isa-sim/build; ../configure --prefix=/cad/riscv/gcc/bin +# make -C addins/riscv-isa-sim/build +# sudo make install -C addins/riscv-isa-sim/build +# cp addins/riscv-isa-sim/arch_test_target/spike/Makefile.include addins/riscv-arch-test/ # update with path including $RISCV_TOOLS # separate into make tests and make regression - sed -i '/export TARGETDIR ?=/c\export TARGETDIR ?= /home/harris/riscv-wally/addins/riscv-isa-sim/arch_test_target' tests/wally-riscv-arch-test/Makefile.include + cp $RISCV/riscv-isa-sim/arch_test_target/spike/Makefile.include addins/riscv-arch-test/ + sed -i '/export TARGETDIR ?=/c\export TARGETDIR ?= $RISCV/riscv-isa-sim/arch_test_target' tests/wally-riscv-arch-test/Makefile.include echo export RISCV_PREFIX = riscv64-unknown-elf- >> tests/wally-riscv-arch-test/Makefile.include make -C addins/riscv-arch-test make -C addins/riscv-arch-test XLEN=32 diff --git a/wally-pipelined/README.txt b/wally-pipelined/README.txt new file mode 100644 index 00000000..25055460 --- /dev/null +++ b/wally-pipelined/README.txt @@ -0,0 +1,50 @@ +Code Improvements +David_Harris@hmc.edu 15 Nov 2021 + +Remove depricated N-Mode stuff, including sd in privileged.sv +Look at version 13? of privileged spec. What should we add? +Reduce size of repo + +Timing optimization (Kip, Shreya) + Use ForwardSrcA instead of SrcA for mdu / fpu + Look at TLB -> PMP -> Access Fault -> Trap + may be able to precompute + Try flattening, see speedup + Take out Mul synthesis modes + +RISCV-Arch-tests + Port MMU tests + +FPU + spec difference on signaling/quiet NAN propagation + SRT Div/Sqrt (Katherine, maybe Udeema) + Get riscv-arch-tests running (James, Katherine) + Get testfloat all passing + Katherine's FPU optimization + +Linux Boot + Ben, Skyler + +FPGA Boot Linux (Ross) + +IFU/LSU + Block diagrams, code cleanup + Burst mode transfers to speed up IPC + Implications of no byte enables on subword write - do stores take extra cycle, should this be avoided? + +28 nm Implementation + Install processor + Memory macros + Synthesis & PNR + Timing review + +Benchmarking + +Flow + Kevin Kim has a makefile to check out and build all the pieces. Make sure this is running; change Repo README to use his makefile + +Code cleanup + .* fixes by thanksgiving + Rename top-level modules to abbreviations + Rename muldiv to mdu + Get rid of DESIGN_COMPILER flag and redundant multiplier \ No newline at end of file diff --git a/wally-pipelined/linux-testgen/linux-testvectors/all.txt b/wally-pipelined/linux-testgen/linux-testvectors/all.txt new file mode 120000 index 00000000..4275ab31 --- /dev/null +++ b/wally-pipelined/linux-testgen/linux-testvectors/all.txt @@ -0,0 +1 @@ +/courses/e190ax/buildroot_boot/all.txt \ No newline at end of file diff --git a/wally-pipelined/linux-testgen/linux-testvectors/bootmem.txt b/wally-pipelined/linux-testgen/linux-testvectors/bootmem.txt new file mode 120000 index 00000000..33bff4ce --- /dev/null +++ b/wally-pipelined/linux-testgen/linux-testvectors/bootmem.txt @@ -0,0 +1 @@ +/courses/e190ax/buildroot_boot/bootmem.txt \ No newline at end of file diff --git a/wally-pipelined/linux-testgen/linux-testvectors/checkpoint8500000 b/wally-pipelined/linux-testgen/linux-testvectors/checkpoint8500000 new file mode 120000 index 00000000..e4834441 --- /dev/null +++ b/wally-pipelined/linux-testgen/linux-testvectors/checkpoint8500000 @@ -0,0 +1 @@ +/courses/e190ax/buildroot_boot/checkpoint8500000 \ No newline at end of file diff --git a/wally-pipelined/linux-testgen/linux-testvectors/ram.txt b/wally-pipelined/linux-testgen/linux-testvectors/ram.txt new file mode 120000 index 00000000..209d4eed --- /dev/null +++ b/wally-pipelined/linux-testgen/linux-testvectors/ram.txt @@ -0,0 +1 @@ +/courses/e190ax/buildroot_boot/ram.txt \ No newline at end of file diff --git a/wally-pipelined/linux-testgen/linux-testvectors/vmlinux.objdump b/wally-pipelined/linux-testgen/linux-testvectors/vmlinux.objdump new file mode 120000 index 00000000..8f52aac0 --- /dev/null +++ b/wally-pipelined/linux-testgen/linux-testvectors/vmlinux.objdump @@ -0,0 +1 @@ +/courses/e190ax/buildroot_boot/vmlinux.objdump \ No newline at end of file diff --git a/wally-pipelined/linux-testgen/linux-testvectors/vmlinux.objdump.addr b/wally-pipelined/linux-testgen/linux-testvectors/vmlinux.objdump.addr new file mode 120000 index 00000000..62079f3a --- /dev/null +++ b/wally-pipelined/linux-testgen/linux-testvectors/vmlinux.objdump.addr @@ -0,0 +1 @@ +/courses/e190ax/buildroot_boot/vmlinux.objdump.addr \ No newline at end of file diff --git a/wally-pipelined/linux-testgen/linux-testvectors/vmlinux.objdump.lab b/wally-pipelined/linux-testgen/linux-testvectors/vmlinux.objdump.lab new file mode 120000 index 00000000..fe8ecc6e --- /dev/null +++ b/wally-pipelined/linux-testgen/linux-testvectors/vmlinux.objdump.lab @@ -0,0 +1 @@ +/courses/e190ax/buildroot_boot/vmlinux.objdump.lab \ No newline at end of file diff --git a/wally-pipelined/srt/sqrttestgen b/wally-pipelined/srt/sqrttestgen new file mode 100755 index 0000000000000000000000000000000000000000..d4b68062699e467b77274618e35a4e7cd2690e24 GIT binary patch literal 13168 zcmeHOeQ*=U6<3wtQk8~O1~PRZFm6gv-`m?K zpUzT~>7@U8&E4Dg+xOnSeY>~1yO-x)jfS@+@5?06W z6BK1JHJ#Rcm`}{+EKr$eh&JdjBT9N-06pG5QT}nnDFoJu`f|mEQ9J|{&1H)^f~_l- zE$Z-9bOb}O?uzcJ6%{L%xuRj$65ejKkFsmlw(y!LjuLR_^VM+S7{Kxqy%)zeto(KF z6F+}~mH%?#5BBH%rUm5-;Y#Ha*_d>GZ|(Za^Nd-;H^3Edvf5j z0GHr0r)2DAw$mF7u{90#HMQyz*Amxq@Wh(_!@P}i`W^kW@IS_Id`WP{<_Bls zNYWsW3Cl}?()iZPt?Badk}W94pK0UsLUF*k1;-bqViBL|0O&(dFOdv5ACy9&%z)d- z2+&FcPR}eBR~c~Qye1oPtecWzz|(yOg-r$=0+LR58St5Dl(8)a9LFrBb^|V^AYP>O zo-0uL@?V`NF=h9lmY@6sz)J5c1;eDN)70`8KqOWABHSG%GUSkN$HLJ>3R3C!k;hPu zj&S}v$YTgc2RZ)~@;2lTasDynF=V6P=KNQX$54&-bNpWk{JqFyh(?<@--n_fplCyR@Z2C)x9pUvf#3kL$&HXZ?zs$Eb~e)IxvU&i`W|`}s{%twr4O$7ZUxx$4kxF{+d$*Iqlhy~ zpHAYQgwodn7pgRlDe(hBWgk+L1ttEw{M3_OQjgbz^iTVQ|-^|g$r%c0|vtDqDL06aFJqU3H}63u2xUS*KPha$Pb z=u{;*l|-i!XYIW5^Nza)IS*WZ7dR1cxIBsNe?NPzD0UXM0(#!Dd5FY336RNe0Cf9X z)DaHUwSL+wmnf`apon+L&q;ZZ&$&|hcaH+lXp zUK85GSV5;aJ>w^a_2=Dvr#qf<-%%gGYHn}&tH@P>v z)#3hti{vj1Lr>ydET&!y{67A-w4MKAYyPOV&EKYlBT*q-8;*7OLN{p=|8bV^XWbwq z1%e%Z?0%8Ps`bpcpdSc&UeNaiy)5XJ>ixGq(|a+Ms($K8Oz&4O<>^9o`Nl_&UMw4{ zzV{c}SBvw;s_*+@-&^f$ta|Py?WAY!d(|yGofdkd)z=@t5B{C2MhDAEI|Aj>DhbF; zR@zO@0VV&Ktb>)D4yOJpTduR+itjr31JL!aRO%p589D)fkt(3q2Z6o-!z}@H4Lsra zBYy+TI1%iP?cpk!No z?nv)>5ML?;Xm6lwnyycKCNIM0UQF}&9d7WY8Pj$AKC#b)`(Bs|L^*!vz=YpvFkQTo z3L`yem64?Pe4TkZPkT3mR-LDhRXt2kw5L%l_-h0uVxtUve#b=LBnm`B>AMZ>z0BoO zj7j-2&k;T*{2{+9h1?85sebr`#M^U7$irt}&QrZ(g6|jQLjC_vXdl~LQ9$(THbM6Y z`ZYnH74&C<9uxEpLEjbhlAzNJ<7-WA?MkT(c7DsHWv(jMa%oBB;^mbqmMoRZ*7<#s z;?;D#V(E%<_KAg;Eh{%S!o=HPG*?+=6N3uPn3^EL*%5n_HY7TVxzBF!6__%#f7w#>=K zu7&d(+3>lH_JfT&HU>|vm=`kfd8{idKCzFUDNnQB1d7v39(zAEf#^A$Pc3Y+|2U6Y zA^uIKenHEK_n2^(z|He{9k)N9^$7oIK3~uA$?@DN>?BO~_i*{i{qhXp+1iz>y+7f0 z=CB^S47rIk1leqHK#6Sjf6G;`nlv8X=5{9c`#*%dd0c(S@yX+}5E@{~G9GROd=A7P zcY`s}JRS#Jf?q%LI9V#>ADf}e^KbQ_w-RtC$ZMu?<>vBeIWtvoeDZU5AcuTQ4jgyj zvzQ!i?{c0KFpcj|9GomohdB zIyzh27UaMe=fG=o;CBLEWSy5jmm{iWZ8_xM=6+6|=VLkKA4dDx&i%ASw5S#f1YB)! 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