diff --git a/.gitignore b/.gitignore index dd916061..b88dfa3e 100644 --- a/.gitignore +++ b/.gitignore @@ -21,6 +21,7 @@ wlft* /imperas-riscv-tests/logs *.o *.d +*.vstf testsBP/*/*/*.elf* testsBP/*/OBJ/* testsBP/*/*.a diff --git a/Makefile b/Makefile index a8ca63fe..d715d72d 100644 --- a/Makefile +++ b/Makefile @@ -1,31 +1,18 @@ -#make all: submodules other -#make all: submodules other -#submodules: addins/riscv-isa-sim addins/riscv-arch-test -# git pull --recurse-submodules -# -#other: make all: # move these parts into compiling archtest separtately - cp -r addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/I addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/F - cp -r addins/riscv-isa-sim/arch_test_target/spike/device/rv64i_m/I addins/riscv-isa-sim/arch_test_target/spike/device/rv64i_m/D -<<<<<<< HEAD -#why cat - cat addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/F/Makefile.include -======= ->>>>>>> 29f2a1c5479d7a80debdb1ac337fcda628cc57a3 - sed -i 's/--isa=rv32i /--isa=32if/' addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/F/Makefile.include - sed -i 's/--isa=rv64i /--isa=64if/' addins/riscv-isa-sim/arch_test_target/spike/device/rv64i_m/D/Makefile.include - if [ -d "addins/riscv-isa-sim/build" ]; then echo "Build exists"; else mkdir addins/riscv-isa-sim/build; fi - cd addins/riscv-isa-sim/build; ../configure --prefix=/cad/riscv/gcc/bin - make -C addins/riscv-isa-sim/build -# does sudo work? - - sudo make install -C addins/riscv-isa-sim/build - - cp addins/riscv-isa-sim/arch_test_target/spike/Makefile.include addins/riscv-arch-test/ +# cp -r addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/I addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/F +# cp -r addins/riscv-isa-sim/arch_test_target/spike/device/rv64i_m/I addins/riscv-isa-sim/arch_test_target/spike/device/rv64i_m/D +# sed -i 's/--isa=rv32i /--isa=32if/' addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/F/Makefile.include +# sed -i 's/--isa=rv64i /--isa=64id/' addins/riscv-isa-sim/arch_test_target/spike/device/rv64i_m/D/Makefile.include +# if [ -d "addins/riscv-isa-sim/build" ]; then echo "Build exists"; else mkdir addins/riscv-isa-sim/build; fi +# cd addins/riscv-isa-sim/build; ../configure --prefix=/cad/riscv/gcc/bin +# make -C addins/riscv-isa-sim/build +# sudo make install -C addins/riscv-isa-sim/build +# cp addins/riscv-isa-sim/arch_test_target/spike/Makefile.include addins/riscv-arch-test/ # update with path including $RISCV_TOOLS # separate into make tests and make regression - sed -i '/export TARGETDIR ?=/c\export TARGETDIR ?= /home/harris/riscv-wally/addins/riscv-isa-sim/arch_test_target' tests/wally-riscv-arch-test/Makefile.include + cp $RISCV/riscv-isa-sim/arch_test_target/spike/Makefile.include addins/riscv-arch-test/ + sed -i '/export TARGETDIR ?=/c\export TARGETDIR ?= $RISCV/riscv-isa-sim/arch_test_target' tests/wally-riscv-arch-test/Makefile.include echo export RISCV_PREFIX = riscv64-unknown-elf- >> tests/wally-riscv-arch-test/Makefile.include make -C addins/riscv-arch-test make -C addins/riscv-arch-test XLEN=32 diff --git a/fpga/constraints/constraints.xdc b/fpga/constraints/constraints.xdc index 51bc8722..9059dc7f 100644 --- a/fpga/constraints/constraints.xdc +++ b/fpga/constraints/constraints.xdc @@ -17,7 +17,8 @@ #create_generated_clock -name mmcm_clkout1 -source [get_pins xlnx_ddr4_c0/c0_sys_clk_p] -edges {1 2 3} -edge_shift {0.000 48.000 96.000} [get_pins xlnx_ddr4_c0/addn_ui_clkout1] -create_generated_clock -name mmcm_clkout1 xlnx_ddr4_c0/addn_ui_clkout1 +#create_generated_clock -name mmcm_clkout1 xlnx_ddr4_c0/addn_ui_clkout1 +#create_generated_clock -name mmcm_clkout1 mmcm_clkout1 create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 [get_pins wallypipelinedsoc/uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O] diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile index d397c5ed..c65e522f 100644 --- a/fpga/generator/Makefile +++ b/fpga/generator/Makefile @@ -1,7 +1,11 @@ dst := IP +all: FPGA -all: $(dst)/xlnx_proc_sys_reset.log \ +FPGA: IP + vivado -mode batch -source wally.tcl | tee wally.log + +IP: $(dst)/xlnx_proc_sys_reset.log \ $(dst)/xlnx_ddr4.log \ $(dst)/xlnx_axi_clock_converter.log \ $(dst)/xlnx_ahblite_axi_bridge.log @@ -11,5 +15,13 @@ $(dst)/%.log: %.tcl cd IP;\ vivado -mode batch -source ../$*.tcl | tee $*.log -clean: - rm -rf IP vivado.jou vivado.log +cleanIP: + rm -rf IP + +cleanLogs: + rm -rf *.jou *.log + +cleanFPGA: + rm -rf WallyFPGA.* reports sim .Xil + +cleanAll: cleanIP cleanLogs cleanFPGA diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index 405ba439..affeb45b 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -21,50 +21,99 @@ set_property include_dirs {../../wally-pipelined/config/fpga ../../wally-pipelin # contrainsts generated by the IP blocks add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_0/bd_1ba7_microblaze_I_0.xdc +set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_0/bd_1ba7_microblaze_I_0.xdc] + +add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0_board.xdc +set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0_board.xdc] + add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0.xdc +set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0.xdc] + add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_2/bd_1ba7_ilmb_0.xdc +set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_2/bd_1ba7_ilmb_0.xdc] + add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_3/bd_1ba7_dlmb_0.xdc -add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/par/xlnx_ddr4.xdc +set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_3/bd_1ba7_dlmb_0.xdc] + +add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_10/bd_1ba7_iomodule_0_0_board.xdc +set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_10/bd_1ba7_iomodule_0_0_board.xdc] + +add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_board.xdc +set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_board.xdc] + +add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_board.xdc +set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_board.xdc] + +add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset.xdc +set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset.xdc] + +add_files -fileset constrs_1 -norecurse ../constraints/constraints.xdc +set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints.xdc] + add_files -fileset constrs_1 -norecurse IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_clocks.xdc +set_property PROCESSING_ORDER LATE [get_files IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_clocks.xdc] + +add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/xlnx_ddr4_board.xdc +set_property PROCESSING_ORDER LATE [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/xlnx_ddr4_board.xdc] + +add_files -fileset constrs_1 -norecurse IP/xlnx_ahblite_axi_bridge.gen/sources_1/ip/xlnx_ahblite_axi_bridge/xlnx_ahblite_axi_bridge_ooc.xdc +set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ahblite_axi_bridge.gen/sources_1/ip/xlnx_ahblite_axi_bridge/xlnx_ahblite_axi_bridge_ooc.xdc] + + +add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/par/xlnx_ddr4.xdc +set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/par/xlnx_ddr4.xdc] + + +add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_1/par/xlnx_ddr4_phy_ooc.xdc -#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_1/par/xlnx_ddr4_phy_ooc.xdc +add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_ooc.xdc + +add_files -fileset constrs_1 -norecurse IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_ooc.xdc + + +add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_ooc.xdc + -#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_10/bd_1ba7_iomodule_0_0_board.xdc -#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0_board.xdc #add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_0/bd_1ba7_microblaze_I_0_ooc_debug.xdc - #add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_9/bd_1ba7_second_lmb_bram_I_0_ooc.xdc #add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_6/bd_1ba7_lmb_bram_I_0_ooc.xdc #add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/bd_1ba7_ooc.xdc -#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_board.xdc -#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_ooc.xdc -#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/xlnx_ddr4_board.xdc #add_files -fileset constrs_1 -norecurse IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_ooc.xdc #add_files -fileset constrs_1 -norecurse IP/xlnx_ahblite_axi_bridge.runs/xlnx_ahblite_axi_bridge_synth_1/dont_touch.xdc -#add_files -fileset constrs_1 -norecurse IP/xlnx_ahblite_axi_bridge.gen/sources_1/ip/xlnx_ahblite_axi_bridge/xlnx_ahblite_axi_bridge_ooc.xdc + #add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.runs/xlnx_proc_sys_reset_synth_1/dont_touch.xdc -#add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_ooc.xdc -#add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset.xdc -#add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_board.xdc + + + #add_files -fileset constrs_1 -norecurse IP/xlnx_axi_clock_converter.runs/xlnx_axi_clock_converter_synth_1/.Xil/xlnx_axi_clock_converter_propImpl.xdc #add_files -fileset constrs_1 -norecurse IP/xlnx_axi_clock_converter.runs/xlnx_axi_clock_converter_synth_1/dont_touch.xdc #add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.runs/xlnx_ddr4_synth_1/.Xil/xlnx_ddr4_propImpl.xdc #add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.runs/xlnx_ddr4_synth_1/dont_touch.xdc # constraints for wally top level -add_files -fileset constrs_1 -norecurse ../constraints/constraints.xdc # define top level set_property top fpgaTop [current_fileset] +set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_ooc.xdc] +set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_1/par/xlnx_ddr4_phy_ooc.xdc] +set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_ooc.xdc] +set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_ooc.xdc] + + update_compile_order -fileset sources_1 +update_compile_order -fileset constrs_1 +# This is important as the ddr4 IP contains the generate clock constraint which the user constraints depend on. +report_compile_order -constraints > reports/compile_order.rpt # this is elaboration not synthesis. synth_design -rtl -name rtl_1 +report_clocks -file reports/clocks.rpt + # this does synthesis? wtf? launch_runs synth_1 -jobs 4 diff --git a/fpga/generator/xlnx_axi_clock_converter.tcl b/fpga/generator/xlnx_axi_clock_converter.tcl index c63d8761..9e581c29 100644 --- a/fpga/generator/xlnx_axi_clock_converter.tcl +++ b/fpga/generator/xlnx_axi_clock_converter.tcl @@ -11,7 +11,13 @@ set_property board_part $boardName [current_project] create_ip -name axi_clock_converter -vendor xilinx.com -library ip -module_name $ipName -set_property -dict [list CONFIG.ACLK_ASYNC {1} CONFIG.PROTOCOL {AXI4} CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {64} CONFIG.ID_WIDTH {4}] [get_ips $ipName] +set_property -dict [list CONFIG.ACLK_ASYNC {1} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.DATA_WIDTH {64} \ + CONFIG.ID_WIDTH {4} \ + CONFIG.MI_CLK.FREQ_HZ {208333333} \ + CONFIG.SI_CLK.FREQ_HZ {10000000}] [get_ips $ipName] generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v index eb78e89d..d9751c9c 100644 --- a/fpga/src/fpgaTop.v +++ b/fpga/src/fpgaTop.v @@ -44,7 +44,6 @@ module fpgaTop output calib, output cpu_reset, - output ddr4_sdram_c1_062, output ahblite_resetn, output [16 : 0] c0_ddr4_adr, diff --git a/wally-pipelined/README.txt b/wally-pipelined/README.txt new file mode 100644 index 00000000..25055460 --- /dev/null +++ b/wally-pipelined/README.txt @@ -0,0 +1,50 @@ +Code Improvements +David_Harris@hmc.edu 15 Nov 2021 + +Remove depricated N-Mode stuff, including sd in privileged.sv +Look at version 13? of privileged spec. What should we add? +Reduce size of repo + +Timing optimization (Kip, Shreya) + Use ForwardSrcA instead of SrcA for mdu / fpu + Look at TLB -> PMP -> Access Fault -> Trap + may be able to precompute + Try flattening, see speedup + Take out Mul synthesis modes + +RISCV-Arch-tests + Port MMU tests + +FPU + spec difference on signaling/quiet NAN propagation + SRT Div/Sqrt (Katherine, maybe Udeema) + Get riscv-arch-tests running (James, Katherine) + Get testfloat all passing + Katherine's FPU optimization + +Linux Boot + Ben, Skyler + +FPGA Boot Linux (Ross) + +IFU/LSU + Block diagrams, code cleanup + Burst mode transfers to speed up IPC + Implications of no byte enables on subword write - do stores take extra cycle, should this be avoided? + +28 nm Implementation + Install processor + Memory macros + Synthesis & PNR + Timing review + +Benchmarking + +Flow + Kevin Kim has a makefile to check out and build all the pieces. Make sure this is running; change Repo README to use his makefile + +Code cleanup + .* fixes by thanksgiving + Rename top-level modules to abbreviations + Rename muldiv to mdu + Get rid of DESIGN_COMPILER flag and redundant multiplier \ No newline at end of file diff --git a/wally-pipelined/srt/sqrttestgen b/wally-pipelined/srt/sqrttestgen new file mode 100755 index 00000000..d4b68062 Binary files /dev/null and b/wally-pipelined/srt/sqrttestgen differ diff --git a/wally-pipelined/srt/testgen b/wally-pipelined/srt/testgen new file mode 100755 index 00000000..bb01f81b Binary files /dev/null and b/wally-pipelined/srt/testgen differ diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv index 2aaacee8..50559b9d 100644 --- a/wally-pipelined/testbench/testbench-linux.sv +++ b/wally-pipelined/testbench/testbench-linux.sv @@ -430,7 +430,7 @@ module testbench(); NextMIPexpected = ExpectedCSRArrayValueE[NumCSRE]; \ end \ if(ExpectedCSRArrayE[NumCSRE].substr(0,3) == "mepc") begin \ - $display("hello! we are here."); \ + // $display("hello! we are here."); \ MepcExpected = ExpectedCSRArrayValueE[NumCSRE]; \ $display("%tns: MepcExpected: %x",$time,MepcExpected); \ end \ @@ -469,7 +469,7 @@ module testbench(); // $display("%tns: ExpectedPCM %x",$time,ExpectedPCM); // $display("%tns: ExpectedPCE %x",$time,ExpectedPCE); // $display("%tns: ExpectedPCW %x",$time,ExpectedPCW); - if((ExpectedPCE != MepcExpected) & ((MepcExpected - ExpectedPCE) * (MepcExpected - ExpectedPCE) <= 16)) begin + if((ExpectedPCE != MepcExpected) & ((MepcExpected - ExpectedPCE) * (MepcExpected - ExpectedPCE) <= 200) || ~dut.hart.ieu.c.InstrValidM) begin RequestDelayedMIP <= 1; $display("%tns: Requesting Delayed MIP. Current MEPC value is %x",$time,MepcExpected); end else begin // update MIP immediately diff --git a/wally-setup.sh b/wally-setup.sh new file mode 100644 index 00000000..4dba5495 --- /dev/null +++ b/wally-setup.sh @@ -0,0 +1,26 @@ +#!/bin/bash + +# wally-setup.sh +# David_Harris@hmc.edu and kekim@hmc.edu 1 December 2021 +# Set up tools for riscv-wally + +echo "Executing wally-setup.sh" + +# Path to RISC-V Tools +export RISCV=/opt/riscv # change this if you installed the tools in a different location + +# Tools +export PATH=$RISCV/riscv-gnu-toolchain/bin:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/bin:$PATH # GCC tools +export PATH=~/riscv-wally/bin:$PATH # exe2memfile; change this if riscv-wally isn't at your home directory +export PATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin:$PATH # Change this for your path to Modelsim +export PATH=/usr/local/bin/verilator:$PATH # Change this for your path to Verilator +export LD_LIBRARY_PATH=$RISCV/riscv-gnu-toolchain/lib:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/lib:$LD_LIBRARY_PATH + +export MGLS_LICENSE_FILE=1717@solidworks.eng.hmc.edu # *** is this the right license server now + +# Imperas; *** remove if not using +PATH=/cad/riscv/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64:/cad/riscv/imperas-riscv-tests/riscv-ovpsim/bin/Liux64:$PATH # *** maybe take this out based on Imperas +export LD_LIBRARY_PATH=/cad/imperas/Imperas.20200630/bin/Linux64:$LD_LIBRARY_PATH # remove if no imperas +IMPERAS_HOME=/cad/imperas/Imperas.20200630 +source $IMPERAS_HOME/bin/setup.sh +setupImperas $IMPERAS_HOME