From 7f42ff06d2f7a6af5429147d1e996a3f1ef0342b Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 5 May 2022 15:15:02 +0000 Subject: [PATCH] SFENCE.VMA should be illegal in user mode --- pipelined/src/privileged/csr.sv | 3 +-- pipelined/src/privileged/privdec.sv | 12 +++++++----- pipelined/src/privileged/privileged.sv | 6 +++--- pipelined/testbench/tests.vh | 1 - 4 files changed, 11 insertions(+), 11 deletions(-) diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index 006ef4cc..afb9c5ef 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -57,7 +57,7 @@ module csr #(parameter input logic [1:0] NextPrivilegeModeM, PrivilegeModeW, input logic [`XLEN-1:0] CauseM, NextFaultMtvalM, output logic [1:0] STATUS_MPP, - output logic STATUS_SPP, STATUS_TSR, + output logic STATUS_SPP, STATUS_TSR, STATUS_TVM, output logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, STVEC_REGW, MTVEC_REGW, output logic [`XLEN-1:0] MEDELEG_REGW, output logic [`XLEN-1:0] SATP_REGW, @@ -86,7 +86,6 @@ module csr #(parameter logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW; logic WriteMSTATUSM, WriteSSTATUSM; logic CSRMWriteM, CSRSWriteM, CSRUWriteM; - logic STATUS_TVM; logic WriteFRMM, WriteFFLAGSM; logic [`XLEN-1:0] UnalignedNextEPCM, NextEPCM, NextCauseM, NextMtvalM; diff --git a/pipelined/src/privileged/privdec.sv b/pipelined/src/privileged/privdec.sv index 28851b13..ed5b51d4 100644 --- a/pipelined/src/privileged/privdec.sv +++ b/pipelined/src/privileged/privdec.sv @@ -36,12 +36,12 @@ module privdec ( input logic PrivilegedM, IllegalIEUInstrFaultM, IllegalCSRAccessM, IllegalFPUInstrM, input logic TrappedSRETM, WFITimeoutM, input logic [1:0] PrivilegeModeW, - input logic STATUS_TSR, + input logic STATUS_TSR, STATUS_TVM, input logic [1:0] STATUS_FS, output logic IllegalInstrFaultM, output logic sretM, mretM, ecallM, ebreakM, wfiM, sfencevmaM); - logic IllegalPrivilegedInstrM; + logic IllegalPrivilegedInstrM, IllegalOrDisabledFPUInstrM; // xRET defined in Privileged Spect 3.2.2 assign sretM = PrivilegedM & (InstrM[31:20] == 12'b000100000010) & `S_SUPPORTED & @@ -51,8 +51,10 @@ module privdec ( assign ecallM = PrivilegedM & (InstrM[31:20] == 12'b000000000000); assign ebreakM = PrivilegedM & (InstrM[31:20] == 12'b000000000001); assign wfiM = PrivilegedM & (InstrM[31:20] == 12'b000100000101); - assign sfencevmaM = PrivilegedM & (InstrM[31:25] == 7'b0001001) & (PrivilegedModeW == `M_MODE | (PrivilegeModeW == `S_MODE & ~STATUS_TVM)); // *** does this work in U mode? + assign sfencevmaM = PrivilegedM & (InstrM[31:25] == 7'b0001001) & + (PrivilegeModeW == `M_MODE | (PrivilegeModeW == `S_MODE & ~STATUS_TVM)); assign IllegalPrivilegedInstrM = PrivilegedM & ~(sretM|mretM|ecallM|ebreakM|wfiM|sfencevmaM); - assign IllegalInstrFaultM = (IllegalIEUInstrFaultM & (IllegalFPUInstrM | (STATUS_FS == 2'b00))) | IllegalPrivilegedInstrM | IllegalCSRAccessM | - TrappedSRETM | WFITimeoutM; // *** generalize this for other instructions + assign IllegalOrDisabledFPUInstrM = IllegalFPUInstrM | (STATUS_FS == 2'b00); + assign IllegalInstrFaultM = (IllegalIEUInstrFaultM & IllegalOrDisabledFPUInstrM) | IllegalPrivilegedInstrM | IllegalCSRAccessM | + TrappedSRETM | WFITimeoutM; endmodule diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index 96ec8401..5ae49a9d 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -99,7 +99,7 @@ module privileged ( logic MTrapM, STrapM, UTrapM; (* mark_debug = "true" *) logic InterruptM; - logic STATUS_SPP, STATUS_TSR, STATUS_TW; + logic STATUS_SPP, STATUS_TSR, STATUS_TW, STATUS_TVM; logic STATUS_MIE, STATUS_SIE; logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW; logic md; @@ -148,7 +148,7 @@ module privileged ( privdec pmd(.InstrM(InstrM[31:20]), .PrivilegedM, .IllegalIEUInstrFaultM, .IllegalCSRAccessM, .IllegalFPUInstrM, .TrappedSRETM, .WFITimeoutM, - .PrivilegeModeW, .STATUS_TSR, .STATUS_FS, .IllegalInstrFaultM, + .PrivilegeModeW, .STATUS_TSR, .STATUS_TVM, .STATUS_FS, .IllegalInstrFaultM, .sretM, .mretM, .ecallM, .ebreakM, .wfiM, .sfencevmaM); /////////////////////////////////////////// @@ -166,7 +166,7 @@ module privileged ( .BPPredClassNonCFIWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .NextPrivilegeModeM, .PrivilegeModeW, .CauseM, .NextFaultMtvalM, .STATUS_MPP, - .STATUS_SPP, .STATUS_TSR, + .STATUS_SPP, .STATUS_TSR, .STATUS_TVM, .MEPC_REGW, .SEPC_REGW, .STVEC_REGW, .MTVEC_REGW, .MEDELEG_REGW, .SATP_REGW, diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index 46295ce1..49ff0ff5 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -1483,7 +1483,6 @@ string imperas32f[] = '{ string wally32e[] = '{ `WALLYTEST, - "rv32i_m/I/E-beq-01", "03b010", "rv32i_m/I/E-add-01", "005010", "rv32i_m/I/E-addi-01", "004010", "rv32i_m/I/E-and-01", "005010",