From 7c7d40ad63a73f9f6ce12f12baec4bc0ca50ae36 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 31 Dec 2022 06:19:15 -0800
Subject: [PATCH] Broken commit starting to address radix 2 issues

---
 pipelined/config/shared/wally-shared.vh       |  4 +--
 pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv | 27 ++++++++++++-------
 2 files changed, 20 insertions(+), 11 deletions(-)

diff --git a/pipelined/config/shared/wally-shared.vh b/pipelined/config/shared/wally-shared.vh
index dd8371df..e79e5561 100644
--- a/pipelined/config/shared/wally-shared.vh
+++ b/pipelined/config/shared/wally-shared.vh
@@ -23,8 +23,8 @@
 ///////////////////////////////////////////
 
 // division constants
-`define RADIX       32'h4
-`define DIVCOPIES   32'h4
+`define RADIX       32'h2
+`define DIVCOPIES   32'h2
 
 // Memory synthesis configuration
 `define USE_SRAM 0
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
index 7ea7a9b8..476faaaa 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
@@ -53,7 +53,7 @@ module fdivsqrtpreproc (
 
   logic  [`DIVb-1:0] XPreproc;
   logic  [`DIVb:0] PreSqrtX;
-  logic  [`DIVb+3:0] DivX, SqrtX, PreShiftX;  // Variations of dividend, to be muxed
+  logic  [`DIVb+3:0] DivX, DivXShifted, SqrtX, PreShiftX;  // Variations of dividend, to be muxed
   logic  [`NE+1:0] QeE;                       // Quotient Exponent (FP only)
   logic  [`DIVb-1:0] IFNormLenX, IFNormLenD;  // Correctly-sized inputs for iterator
   logic  [`DIVBLEN:0] mE, ell;                // Leading zeros of inputs
@@ -63,8 +63,7 @@ module fdivsqrtpreproc (
     logic signedDiv, NegQuotE;
     logic AsBit, BsBit, AsE, BsE, ALTBE;
     logic [`XLEN-1:0] AE, BE, PosA, PosB;
-    logic [`DIVBLEN:0] TotalIntBits, ZeroDiff, IntSteps, p;
-    logic [`LOGRK-1:0] IntTrunc, RightShiftX;
+    logic [`DIVBLEN:0] ZeroDiff, p;
 
     // Extract inputs, signs, zero, depending on W64 mode if applicable
     assign signedDiv = ~Funct3E[0];
@@ -104,16 +103,26 @@ module fdivsqrtpreproc (
 
   /* verilator lint_off WIDTH */
     // calculate number of fractional digits nE and right shift amount RightShiftX to complete in discrete number of steps
-    assign TotalIntBits = `LOGR + p;                            // Total number of result bits (r integer bits plus p fractional bits)
-    assign IntTrunc = TotalIntBits % `RK;                       // Truncation check for ceiling operator
-    assign IntSteps = (TotalIntBits >> `LOGRK) + |IntTrunc;     // Number of steps for int div
-    assign nE = (IntSteps * `DIVCOPIES) - 1;                    // Fractional digits
-    assign RightShiftX = `RK - 1 - ((TotalIntBits - 1) % `RK);  // Right shift amount
+
+    if (`LOGRK > 0) begin // more than 1 bit per cycle
+      logic [`LOGRK-1:0] IntTrunc, RightShiftX;
+      logic [`DIVBLEN:0] TotalIntBits, IntSteps;
+
+      assign TotalIntBits = `LOGR + p;                            // Total number of result bits (r integer bits plus p fractional bits)
+      assign IntTrunc = TotalIntBits % `RK;                       // Truncation check for ceiling operator
+      assign IntSteps = (TotalIntBits >> `LOGRK) + |IntTrunc;     // Number of steps for int div
+      assign nE = (IntSteps * `DIVCOPIES) - 1;                    // Fractional digits
+      assign RightShiftX = `RK - 1 - ((TotalIntBits - 1) % `RK);  // Right shift amount
+      assign DivXShifted = DivX >> RightShiftX;                   // shift X to complete in nE steps
+    end else begin // radix 2 1 copy doesn't require shifting
+      assign nE = p + 1; 
+      assign DivXShifted = DivX;
+    end
   /* verilator lint_on WIDTH */
 
     // Selet integer or floating-point operands
     mux2 #(1)    numzmux(XZeroE, AZeroE, MDUE, NumerZeroE);
-    mux2 #(`DIVb+4) xmux(PreShiftX, DivX >> RightShiftX, MDUE, X);
+    mux2 #(`DIVb+4) xmux(PreShiftX, DivXShifted, MDUE, X);
 
     // pipeline registers
     flopen #(1)        mdureg(clk, IFDivStartE, MDUE,     MDUM);