diff --git a/pipelined/src/generic/flop/simpleram.sv b/pipelined/src/generic/flop/simpleram.sv
index 3621ce7c..2c434cb7 100644
--- a/pipelined/src/generic/flop/simpleram.sv
+++ b/pipelined/src/generic/flop/simpleram.sv
@@ -33,7 +33,7 @@
 module simpleram #(parameter BASE=0, RANGE = 65535) (
   input  logic             clk, 
   input  logic             HSELRam,
-  input  logic [31:0]      HADDR,
+  input  logic [31:0]      Adr,
   input  logic             HWRITE,
   input  logic             HREADY,
   input  logic [1:0]       HTRANS,
@@ -56,7 +56,7 @@ module simpleram #(parameter BASE=0, RANGE = 65535) (
 
   assign initTrans = HREADY & HSELRam & (HTRANS != 2'b00);
 
-  flopenr #(32)   haddrreg(clk, 1'b0, 1'b1, HADDR, A);
+  flopenr #(32)   Adrreg(clk, 1'b0, 1'b1, Adr, A);
   
   /* verilator lint_off WIDTH */
   if (`XLEN == 64)  begin:ramrw
diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index 4f437e2e..b6e74824 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -236,7 +236,7 @@ module ifu (
     simpleram #(
         .BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
         .clk, 
-        .HSELRam(1'b1), .HADDR(CPUBusy ? PCPF[31:0] : PCNextFMux[31:0]), // mux is also inside $, have to replay address if CPU is stalled.
+        .HSELRam(1'b1), .Adr(CPUBusy ? PCPF[31:0] : PCNextFMux[31:0]), // mux is also inside $, have to replay address if CPU is stalled.
         .HWRITE(1'b0), .HREADY(1'b1),
         .HTRANS(2'b10), .HWDATA(0), .HREADRam(FinalInstrRawF_FIXME),
         .HRESPRam(), .HREADYRam());
diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index 1192d62a..08e0f51c 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -247,7 +247,7 @@ module lsu (
   if (`MEM_DTIM) begin : dtim
     simpleram #(.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
         .clk, 
-        .HSELRam(1'b1), .HADDR(CPUBusy ? IEUAdrM[31:0] : IEUAdrE[31:0]),
+        .HSELRam(1'b1), .Adr(CPUBusy ? IEUAdrM[31:0] : IEUAdrE[31:0]),
         .HWRITE(LSURWM[0]), .HREADY(1'b1),
         .HTRANS(|LSURWM ? 2'b10 : 2'b00), .HWDATA(FinalWriteDataM), .HREADRam(ReadDataWordM),
         .HRESPRam(), .HREADYRam());