From 7a25d577ba0ed61b3164a2dfaaa53988206d272c Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 11 Mar 2022 15:41:53 -0600 Subject: [PATCH] Added new asserts to testbench. --- pipelined/testbench/testbench.sv | 2 ++ 1 file changed, 2 insertions(+) diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 33c29548..775a21a7 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -359,6 +359,8 @@ module riscvassertions; // assert (`MEM_DCACHE == 0 | `MEM_DTIM == 0) else $error("Can't simultaneously have a data cache and TIM"); assert (`DMEM == `MEM_CACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache"); assert (`IMEM == `MEM_CACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache"); + assert (`DMEM == `MEM_CACHE | `DBUS ==0) else $error("Dcache rquires DBUS."); + assert (`IMEM == `MEM_CACHE | `IBUS ==0) else $error("Icache rquires IBUS."); end endmodule