diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 012e67a9..9bd5ea1f 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -207,10 +207,10 @@ module ifu ( .WordCount(), .CacheFetchLine(ICacheFetchLine), .CacheWriteLine(1'b0), .CacheBusAck(ICacheBusAck), - .FetchBuffer, .PAdrM(PCPF), + .FetchBuffer, .PAdr(PCPF), .SelUncachedAdr, - .IgnoreRequest(ITLBMissF), .RWM(2'b10), .CPUBusy, .CacheableM(CacheableF), - .BusStall, .BusCommittedM()); + .IgnoreRequest(ITLBMissF), .RW(2'b10), .CPUBusy, .Cacheable(CacheableF), + .BusStall, .BusCommitted()); mux2 #(32) UnCachedDataMux(.d0(FinalInstrRawF), .d1(FetchBuffer[32-1:0]), diff --git a/pipelined/src/lsu/busdp.sv b/pipelined/src/lsu/busdp.sv index 65843809..448fd313 100644 --- a/pipelined/src/lsu/busdp.sv +++ b/pipelined/src/lsu/busdp.sv @@ -60,15 +60,15 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) output logic SelUncachedAdr, // lsu/ifu interface - input logic [`PA_BITS-1:0] PAdrM, + input logic [`PA_BITS-1:0] PAdr, input logic IgnoreRequest, - input logic [1:0] RWM, + input logic [1:0] RW, input logic CPUBusy, - input logic CacheableM, + input logic Cacheable, input logic [2:0] Funct3, output logic SelLSUBusWord, output logic BusStall, - output logic BusCommittedM); + output logic BusCommitted); localparam integer WordCountThreshold = CACHE_ENABLED ? WORDSPERLINE - 1 : 0; logic [`PA_BITS-1:0] LocalHADDR; @@ -83,13 +83,13 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) .q(FetchBuffer[(index+1)*`XLEN-1:index*`XLEN])); end - mux2 #(`PA_BITS) localadrmux(CacheBusAdr, PAdrM, SelUncachedAdr, LocalHADDR); + mux2 #(`PA_BITS) localadrmux(CacheBusAdr, PAdr, SelUncachedAdr, LocalHADDR); assign HADDR = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalHADDR; mux2 #(3) sizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(Funct3), .s(SelUncachedAdr), .y(HSIZE)); busfsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) busfsm( - .clk, .reset, .IgnoreRequest, .RWM, .CacheFetchLine, .CacheWriteLine, - .BusAck, .BusInit, .CPUBusy, .CacheableM, .BusStall, .BusWrite, .SelLSUBusWord, .BusRead, .BufferCaptureEn, - .HBURST, .HTRANS, .BusTransComplete, .CacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount, .WordCountDelayed); + .clk, .reset, .IgnoreRequest, .RW, .CacheFetchLine, .CacheWriteLine, + .BusAck, .BusInit, .CPUBusy, .Cacheable, .BusStall, .BusWrite, .SelLSUBusWord, .BusRead, .BufferCaptureEn, + .HBURST, .HTRANS, .BusTransComplete, .CacheBusAck, .BusCommitted, .SelUncachedAdr, .WordCount, .WordCountDelayed); endmodule diff --git a/pipelined/src/lsu/busfsm.sv b/pipelined/src/lsu/busfsm.sv index f95f77dd..72a17d94 100644 --- a/pipelined/src/lsu/busfsm.sv +++ b/pipelined/src/lsu/busfsm.sv @@ -37,13 +37,13 @@ module busfsm #(parameter integer WordCountThreshold, input logic reset, input logic IgnoreRequest, - input logic [1:0] RWM, + input logic [1:0] RW, input logic CacheFetchLine, input logic CacheWriteLine, input logic BusAck, input logic BusInit, // This might be better as LSUBusLock, or to send this using BusAck. input logic CPUBusy, - input logic CacheableM, + input logic Cacheable, output logic BusStall, output logic BusWrite, @@ -53,7 +53,7 @@ module busfsm #(parameter integer WordCountThreshold, output logic BusTransComplete, output logic [1:0] HTRANS, output logic CacheBusAck, - output logic BusCommittedM, + output logic BusCommitted, output logic SelUncachedAdr, output logic BufferCaptureEn, output logic [LOGWPL-1:0] WordCount, WordCountDelayed); @@ -105,7 +105,7 @@ module busfsm #(parameter integer WordCountThreshold, assign WordCountFlag = (WordCountDelayed == WordCountThreshold[LOGWPL-1:0]); // Detect when we are waiting on the final access. assign CntEn = (PreCntEn & BusAck | (BusInit)) & ~WordCountFlag & ~UnCachedRW; // Want to count when doing cache accesses and we aren't wrapping up. - assign UnCachedAccess = ~CACHE_ENABLED | ~CacheableM; + assign UnCachedAccess = ~CACHE_ENABLED | ~Cacheable; always_ff @(posedge clk) if (reset) BusCurrState <= #1 STATE_BUS_READY; @@ -114,8 +114,8 @@ module busfsm #(parameter integer WordCountThreshold, always_comb begin case(BusCurrState) STATE_BUS_READY: if(IgnoreRequest) BusNextState = STATE_BUS_READY; - else if(RWM[0] & UnCachedAccess) BusNextState = STATE_BUS_UNCACHED_WRITE; - else if(RWM[1] & UnCachedAccess) BusNextState = STATE_BUS_UNCACHED_READ; + else if(RW[0] & UnCachedAccess) BusNextState = STATE_BUS_UNCACHED_WRITE; + else if(RW[1] & UnCachedAccess) BusNextState = STATE_BUS_UNCACHED_READ; else if(CacheFetchLine) BusNextState = STATE_BUS_FETCH; else if(CacheWriteLine) BusNextState = STATE_BUS_WRITE; else BusNextState = STATE_BUS_READY; @@ -160,30 +160,30 @@ module busfsm #(parameter integer WordCountThreshold, // Reset if we aren't initiating a transaction or if we are finishing a transaction. assign CntReset = BusCurrState == STATE_BUS_READY & ~(CacheFetchLine | CacheWriteLine) | BusTransComplete; - assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|RWM)) | CacheFetchLine | CacheWriteLine)) | + assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|RW)) | CacheFetchLine | CacheWriteLine)) | (BusCurrState == STATE_BUS_UNCACHED_WRITE) | (BusCurrState == STATE_BUS_UNCACHED_READ) | (BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_WRITE); - assign UnCachedBusWrite = (BusCurrState == STATE_BUS_READY & UnCachedAccess & RWM[0] & ~IgnoreRequest) | + assign UnCachedBusWrite = (BusCurrState == STATE_BUS_READY & UnCachedAccess & RW[0] & ~IgnoreRequest) | (BusCurrState == STATE_BUS_UNCACHED_WRITE); assign BusWrite = UnCachedBusWrite | (BusCurrState == STATE_BUS_WRITE & ~WordCountFlag); - assign SelLSUBusWord = (BusCurrState == STATE_BUS_READY & UnCachedAccess & RWM[0]) | + assign SelLSUBusWord = (BusCurrState == STATE_BUS_READY & UnCachedAccess & RW[0]) | (BusCurrState == STATE_BUS_UNCACHED_WRITE) | (BusCurrState == STATE_BUS_WRITE); - assign UnCachedBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & RWM[1] & ~IgnoreRequest) | + assign UnCachedBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & RW[1] & ~IgnoreRequest) | (BusCurrState == STATE_BUS_UNCACHED_READ); assign BusRead = UnCachedBusRead | (BusCurrState == STATE_BUS_FETCH & ~(WordCountFlag)) | (BusCurrState == STATE_BUS_READY & CacheFetchLine); assign BufferCaptureEn = UnCachedBusRead | BusCurrState == STATE_BUS_FETCH; - // Makes bus only do uncached reads/writes when we actually do uncached reads/writes. Needed because CacheableM is 0 when flushing cache. + // Makes bus only do uncached reads/writes when we actually do uncached reads/writes. Needed because Cacheable is 0 when flushing cache. assign UnCachedRW = UnCachedBusWrite | UnCachedBusRead; assign CacheBusAck = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & BusAck) | (BusCurrState == STATE_BUS_WRITE & WordCountFlag & BusAck); - assign BusCommittedM = BusCurrState != STATE_BUS_READY; - assign SelUncachedAdr = (BusCurrState == STATE_BUS_READY & (|RWM & UnCachedAccess)) | + assign BusCommitted = BusCurrState != STATE_BUS_READY; + assign SelUncachedAdr = (BusCurrState == STATE_BUS_READY & (|RW & UnCachedAccess)) | (BusCurrState == STATE_BUS_UNCACHED_READ | BusCurrState == STATE_BUS_UNCACHED_READ_DONE | BusCurrState == STATE_BUS_UNCACHED_WRITE | diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 1028a1e7..e009feac 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -228,9 +228,9 @@ module lsu ( .BusRead(LSUBusRead), .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .BusTransComplete(LSUTransComplete), .WordCount, .SelLSUBusWord, .Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheFetchLine(DCacheFetchLine), - .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdrM(LSUPAdrM), - .SelUncachedAdr, .IgnoreRequest, .RWM(LSURWM), .CPUBusy, .CacheableM, - .BusStall, .BusCommittedM); + .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(LSUPAdrM), + .SelUncachedAdr, .IgnoreRequest, .RW(LSURWM), .CPUBusy, .Cacheable(CacheableM), + .BusStall, .BusCommitted(BusCommittedM)); mux2 #(`LLEN) UnCachedDataMux(.d0(LittleEndianReadDataWordM), .d1({{`LLEN-`XLEN{1'b0}}, FetchBuffer[`XLEN-1:0]}), .s(SelUncachedAdr), .y(ReadDataWordMuxM));